rggen 0.33.3 → 0.33.4

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -19,6 +19,8 @@ RgGen has following features:
         * SystemVerilog
         * Verilog
             * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
+        * [Veryl](https://veryl-lang.org)
+            * Need [rggen-veryl](https://github.com/rggen/rggen-veryl) plugin
         * VHDL
             * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
         * Supports standard bus protocols
@@ -112,7 +114,7 @@ Following EDA tools can accept the generated source files.
     * Synopsys VCS
     * Cadence Xcelium
     * Metrics DSim
-    * Xilinx Vivado Simulator
+    * AMD Vivado Simulator
     * Verilator
         * Need `-Wno-unoptflat` switch for Verilog RTL
     * Icarus Verilog
@@ -120,7 +122,7 @@ Following EDA tools can accept the generated source files.
 * Synthesis tools
     * Synopsys Design Compiler
     * Intel Quartus
-    * Xilinx Vivado
+    * AMD Vivado
     * [Yosys](http://www.clifford.at/yosys/)
         * Verilog RTL
 
@@ -145,20 +147,22 @@ $ rggen -c config.yml -o out uart_csr.yml
 
 Then, generated files will be written to the `out` directory.
 
-If you want to generate Verilog RTL and/or VHDL RTL then you need to instll optional plugins listed below.
+If you want to generate Verilog RTL, Veryl RTL and VHDL RTL then you need to instll optional plugins listed below.
 
 * Verilog writer plugin: [rggen-verilog](https://github.com/rggen/rggen-verilog)
+* Veryl writer plugin: [rggen-veryl](https://github.com/rggen/rggen-veryl)
 * VHDL writer plugin: [rggen-vhdl](https://github.com/rggen/rggen-vhdl)
 
 ```
 $ gem install rggen-verilog
+$ gem install rggen-veryl
 $ gem install rggen-vhdl
 ```
 
 In addition, you need to tell RgGen to use these plugins by using the `--plugin` option switch:
 
 ```
-rggen -c config.yml --plugin rggen-verilog --plugin rggen-vhdl uart_csr.yml
+$ rggen -c config.yml --plugin rggen-verilog --plugin rggen-veryl --plugin rggen-vhdl uart_csr.yml
 ```
 
 RgGen will generate following source files from the [`uart_csr.yml`](https://github.com/rggen/rggen-sample/blob/master/uart_csr.yml) register map specification:
@@ -169,6 +173,8 @@ RgGen will generate following source files from the [`uart_csr.yml`](https://git
 * Verilog RTL
     * https://github.com/rggen/rggen-sample/blob/master/uart_csr.v
     * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vh
+* Veryl RTL
+    * https://github.com/rggen/rggen-sample/blob/master/uart_csr.veryl
 * VHDL RTL
     * https://github.com/rggen/rggen-sample/blob/master/uart_csr.vhd
 * UVM register model
@@ -202,6 +208,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 * https://github.com/rggen/rggen-spreadsheet-loader
 * https://github.com/rggen/rggen-duh
 * https://github.com/rggen/rggen-verilog
+* https://github.com/rggen/rggen-veryl
 * https://github.com/rggen/rggen-vhdl
 * https://github.com/rggen/rggen-docker
 

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.33.3'
+  VERSION = '0.33.4'
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.33.3
+  version: 0.33.4
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-07-20 00:00:00.000000000 Z
+date: 2024-11-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-c-header
@@ -86,14 +86,14 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
 description: |
   RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
   It will automatically generate source code related to control and status registers (CSR),
@@ -136,7 +136,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.5
+rubygems_version: 3.5.16
 signing_key: 
 specification_version: 4
 summary: Code generation tool for control and status registers