rggen 0.3.2 → 0.3.3

checksums.yaml

@@ -1,7 +1,7 @@
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-  data.tar.gz: 2c08390336ae73726a619515cc9ed8a61d08eafa
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+  data.tar.gz: 4880ac0a2c985415276dc82ad19bebdf95126dc3
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data/README.md

@@ -6,7 +6,7 @@
 # RgGen
 
 RgGen is a code generation tool for SoC designers.
-It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
+It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
 Also RgGen is customizable so you can build your specific generate tool.
 
 ## Ruby

data/lib/rggen/builtins/bit_field/type.rb

@@ -86,7 +86,7 @@ list_item :bit_field, :type do
       class_delegator :same_width
 
       build do |cell|
-        @type = cell.to_sym.downcase
+        @type = cell
       end
 
       validate do
@@ -146,9 +146,14 @@ list_item :bit_field, :type do
 
     factory do
       def select_target_item(cell)
-        type  = cell.value.to_sym.downcase
-        @target_items.fetch(type) do
-          error "unknown bit field type: #{type}", cell
+        @target_items.fetch(cell.value) do
+          error "unknown bit field type: #{cell.value}", cell
+        end
+      end
+
+      def convert(cell)
+        @target_items.keys.find(proc { cell }) do |type|
+          type.to_sym.casecmp(cell.to_sym) == 0
         end
       end
     end

data/lib/rggen/builtins/register/array.rb

@@ -96,38 +96,48 @@ simple_item :register, :array do
       register_block.registers.take_while { |r| !register.equal?(r) }
     end
 
-    generate_pre_code :module_item do |buffer|
-      register.dimensions.each_with_index do |dimension, level|
-        generate_for_begin_code(dimension, level, buffer)
-      end if register.array?
+    generate_pre_code :module_item do |code|
+      if register.array?
+        generate_header(code)
+        generate_for_headers(code)
+      end
     end
 
-    generate_post_code :module_item do |buffer|
-      register.dimensions.size.times do
-        generate_for_end_code(buffer)
-      end if register.array?
+    generate_post_code :module_item do |code|
+      if register.array?
+        generate_for_footers(code)
+        generate_footer(code)
+      end
     end
 
-    def generate_for_begin_code(dimension, level, buffer)
-      buffer << generate_for_header(dimension, level)
-      buffer << ' begin : '
-      buffer << block_name(level)
-      buffer << nl
-      buffer.indent += 2
+    def generate_header(code)
+      code << "generate if (1) begin : g_#{register.name}" << nl
+      code.indent += 2
+      code << "genvar #{loop_variables.join(', ')};" << nl
     end
 
-    def generate_for_end_code(buffer)
-      buffer.indent -= 2
-      buffer << 'end' << nl
+    def generate_for_headers(code)
+      register.dimensions.each_with_index do |dimension, level|
+        code << generate_for_header(dimension, level) << nl
+        code.indent += 2
+      end
     end
 
     def generate_for_header(dimension, level)
-      genvar  = loop_variable(level)
-      "for (genvar #{genvar} = 0;#{genvar} < #{dimension};#{genvar}++)"
+      gv  = loop_variable(level)
+      "for (#{gv} = 0;#{gv} < #{dimension};#{gv}++) begin : g"
+    end
+
+    def generate_for_footers(code)
+      register.dimensions.size.times do
+        code.indent -= 2
+        code << :end << nl
+      end
     end
 
-    def block_name(level)
-      "gen_#{register.name}_#{level}"
+    def generate_footer(code)
+      code.indent -= 2
+      code << :end << space << :endgenerate << nl
     end
   end
 end

data/lib/rggen/builtins/register_block/apb.rb

@@ -1,4 +1,17 @@
 list_item :register_block, :host_if, :apb do
+  configuration do
+    validate do
+      if configuration.address_width > 32
+        error 'apb supports 32 or less bits address width only' \
+              ": #{configuration.address_width}"
+      end
+      if configuration.data_width > 32
+        error 'apb supports 32 or less bits data width only' \
+              ": #{configuration.data_width}"
+      end
+    end
+  end
+
   rtl do
     build do
       group(:apb) do

data/lib/rggen/builtins/register_block/axi4lite.erb

@@ -0,0 +1,37 @@
+rggen_host_if_axi4lite #(
+  .DATA_WIDTH           (<%= data_width %>),
+  .HOST_ADDRESS_WIDTH   (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .WRITE_PRIORITY       (<%= write_priority %>)
+) u_host_if (
+  .clk              (<%= clock %>),
+  .rst_n            (<%= reset %>),
+  .i_awvalid        (<%= axi4lite.awvalid %>),
+  .o_awready        (<%= axi4lite.awready %>),
+  .i_awaddr         (<%= axi4lite.awaddr %>),
+  .i_awprot         (<%= axi4lite.awprot %>),
+  .i_wvalid         (<%= axi4lite.wvalid %>),
+  .o_wready         (<%= axi4lite.wready %>),
+  .i_wdata          (<%= axi4lite.wdata %>),
+  .i_wstrb          (<%= axi4lite.wstrb %>),
+  .o_bvalid         (<%= axi4lite.bvalid %>),
+  .i_bready         (<%= axi4lite.bready %>),
+  .o_bresp          (<%= axi4lite.bresp %>),
+  .i_arvalid        (<%= axi4lite.arvalid %>),
+  .o_arready        (<%= axi4lite.arready %>),
+  .i_araddr         (<%= axi4lite.araddr %>),
+  .i_arprot         (<%= axi4lite.arprot %>),
+  .o_rvalid         (<%= axi4lite.rvalid %>),
+  .i_rready         (<%= axi4lite.rready %>),
+  .o_rdata          (<%= axi4lite.rdata %>),
+  .o_rresp          (<%= axi4lite.rresp %>),
+  .o_command_valid  (<%= host_if.command_valid %>),
+  .o_write          (<%= host_if.write %>),
+  .o_read           (<%= host_if.read %>),
+  .o_address        (<%= host_if.address %>),
+  .o_write_data     (<%= host_if.write_data %>),
+  .o_write_mask     (<%= host_if.write_mask %>),
+  .i_response_ready (<%= host_if.response_ready %>),
+  .i_read_data      (<%= host_if.read_data %>),
+  .i_status         (<%= host_if.status %>)
+);

data/lib/rggen/builtins/register_block/axi4lite.rb

@@ -0,0 +1,46 @@
+list_item :register_block, :host_if, :axi4lite do
+  configuration do
+    validate do
+      unless [32, 64].include?(configuration.data_width)
+        error 'axi4lite supports either 32 or 64 bits data width only' \
+              ": #{configuration.data_width}"
+      end
+    end
+  end
+
+  rtl do
+    delegate [
+      :address_width, :data_width, :byte_width
+    ] => :configuration
+    delegate [
+      :local_address_width, :clock, :reset
+    ] => :register_block
+
+    build do
+      parameter :write_priority, name: 'WRITE_PRIORITY', default: 1
+      group :axi4lite do
+        input  :awvalid, name: 'i_awvalid', width: 1
+        output :awready, name: 'o_awready', width: 1
+        input  :awaddr , name: 'i_awaddr' , width: address_width
+        input  :awprot , name: 'i_awprot' , width: 3
+        input  :wvalid , name: 'i_wvalid' , width: 1
+        output :wready , name: 'o_wready' , width: 1
+        input  :wdata  , name: 'i_wdata'  , width: data_width
+        input  :wstrb  , name: 'i_wstrb'  , width: byte_width
+        output :bvalid , name: 'o_bvalid' , width: 1
+        input  :bready , name: 'i_bready' , width: 1
+        output :bresp  , name: 'o_bresp'  , width: 2
+        input  :arvalid, name: 'i_arvalid', width: 1
+        output :arready, name: 'o_arready', width: 1
+        input  :araddr , name: 'i_araddr' , width: address_width
+        input  :arprot , name: 'i_arprot' , width: 3
+        output :rvalid , name: 'o_rvalid' , width: 1
+        input  :rready , name: 'i_rready' , width: 1
+        output :rdata  , name: 'o_rdata'  , width: data_width
+        output :rresp  , name: 'o_rresp'  , width: 2
+      end
+    end
+
+    generate_code_from_template :module_item
+  end
+end

data/lib/rggen/builtins/register_block/host_if.rb

@@ -4,16 +4,34 @@ list_item :register_block, :host_if do
   end
 
   configuration do
-    item_class do
+    item_base do
       field :host_if do
         @host_if || shared_context.enabled_host_ifs.first
       end
 
       build do |value|
-        @host_if  = shared_context.enabled_host_ifs.find do |host_if|
+        @host_if  = value
+      end
+    end
+
+    default_item do
+    end
+
+    factory do
+      def select_target_item(value)
+        @target_items[value]
+      end
+
+      def convert(value)
+        find_host_if(value) do
+          error "unknown host interface: #{value}"
+        end
+      end
+
+      def find_host_if(value, &ifnone)
+        shared_context.enabled_host_ifs.find(ifnone) do |host_if|
           host_if.to_sym.casecmp(value.to_sym) == 0
         end
-        error "unknown host interface: #{value}" if @host_if.nil?
       end
     end
   end

data/lib/rggen/builtins.rb

@@ -43,6 +43,7 @@ require_relative 'builtins/register_block/byte_size'
 require_relative 'builtins/register_block/clock_reset'
 require_relative 'builtins/register_block/host_if'
 require_relative 'builtins/register_block/apb'
+require_relative 'builtins/register_block/axi4lite'
 require_relative 'builtins/register_block/module_definition'
 require_relative 'builtins/register_block/name'
 require_relative 'builtins/register_block/ral_package_definition'

data/lib/rggen/core_components/configuration/item.rb

@@ -0,0 +1,11 @@
+module RgGen
+  module Configuration
+    class Item < InputBase::Item
+      include RaiseError
+
+      def configuration
+        @owner
+      end
+    end
+  end
+end

data/lib/rggen/core_components/configuration/item_factory.rb

@@ -4,9 +4,16 @@ module RgGen
       include RaiseError
 
       def create(configuration, data = nil)
-        item  = create_item(configuration, data)
-        item.build(data) unless data.nil?
-        item
+        data  &&= convert(data)
+        create_item(configuration, data).tap do |item|
+          item.build(data) unless data.nil?
+        end
+      end
+
+      private
+
+      def convert(data)
+        data
       end
     end
   end

data/lib/rggen/core_components/configuration/setup.rb

@@ -4,7 +4,7 @@ module RgGen
       entry do
         component_class   InputBase::Component
         component_factory ConfigurationFactory
-        item_base         InputBase::Item, include: RaiseError
+        item_base         Item
         item_factory      ItemFactory
       end
 

data/lib/rggen/core_components/register_map/item.rb

@@ -14,8 +14,10 @@ module RgGen
 
       def build(configuration, cell)
         @configuration  = configuration
-        @position       = cell.position
-        super(cell.value)
+        unless cell.nil?
+          @position = cell.position
+          super(cell.value)
+        end
       end
     end
   end

data/lib/rggen/core_components/register_map/item_factory.rb

@@ -4,9 +4,22 @@ module RgGen
       include RaiseError
 
       def create(component, configuration, cell = nil)
-        item  = create_item(component, cell)
-        item.build(configuration, cell) unless cell.nil?
-        item
+        convert_cell_value(cell)
+        create_item(component, cell).tap do |item|
+          item.build(configuration, cell)
+        end
+      end
+
+      private
+
+      def convert_cell_value(cell)
+        return if cell.nil?
+        return if cell.empty?
+        cell.value  = convert(cell.value)
+      end
+
+      def convert(cell)
+        cell
       end
     end
   end

data/lib/rggen/core_components.rb

@@ -1,4 +1,5 @@
 require_relative 'core_components/configuration/raise_error'
+require_relative 'core_components/configuration/item'
 require_relative 'core_components/configuration/configuration_factory'
 require_relative 'core_components/configuration/item_factory'
 require_relative 'core_components/configuration/setup'

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
   MINOR   = 3
-  TEENY   = 2
+  TEENY   = 3
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/rtl/compile.f

@@ -1,4 +1,5 @@
 +libext+.sv
++incdir+${RGGEN_HOME}/rtl/register_block
 -y ${RGGEN_HOME}/rtl/bit_field
 -y ${RGGEN_HOME}/rtl/register
 -y ${RGGEN_HOME}/rtl/register_block

data/rtl/register/rggen_address_decoder.sv

@@ -23,27 +23,35 @@ module rggen_address_decoder #(
 
   assign  match = (match_address && match_shadow_index) ? 1'b1 : 1'b0;
 
-  if (START_ADDRESS == END_ADDRESS) begin
-    assign  match_address = (i_address == START_ADDRESS) ? 1'b1 : 1'b0;
-  end
-  else begin
-    assign  match_address = (i_address inside {[START_ADDRESS:END_ADDRESS]}) ? 1'b1 : 1'b0;
-  end
+  generate
+    if (START_ADDRESS == END_ADDRESS) begin
+      assign  match_address = (i_address == START_ADDRESS) ? 1'b1 : 1'b0;
+    end
+    else begin
+      assign  match_address = (
+        (i_address >= START_ADDRESS) && (i_address <= END_ADDRESS)
+      ) ? 1'b1 : 1'b0;
+    end
+  endgenerate
 
-  if (USE_SHADOW_INDEX) begin
-    assign  match_shadow_index  = (i_shadow_index == SHADOW_INDEX_VALUE) ? 1'b1 : 1'b0;
-  end
-  else begin
-    assign  match_shadow_index  = 1'b1;
-  end
+  generate
+    if (USE_SHADOW_INDEX) begin
+      assign  match_shadow_index  = (i_shadow_index == SHADOW_INDEX_VALUE) ? 1'b1 : 1'b0;
+    end
+    else begin
+      assign  match_shadow_index  = 1'b1;
+    end
+  endgenerate
 
-  if (READ_ONLY) begin
-    assign  o_select  = (match && i_read) ? 1'b1 : 1'b0;
-  end
-  else if (WRITE_ONLY) begin
-    assign  o_select  = (match && i_write) ? 1'b1 : 1'b0;
-  end
-  else begin
-    assign  o_select  = match;
-  end
+  generate
+    if (READ_ONLY) begin
+      assign  o_select  = (match && i_read) ? 1'b1 : 1'b0;
+    end
+    else if (WRITE_ONLY) begin
+      assign  o_select  = (match && i_write) ? 1'b1 : 1'b0;
+    end
+    else begin
+      assign  o_select  = match;
+    end
+  endgenerate
 endmodule

data/rtl/register_block/rggen_host_if_apb.sv

@@ -25,6 +25,8 @@ module rggen_host_if_apb #(
   input   [DATA_WIDTH-1:0]          i_read_data,
   input   [1:0]                     i_status
 );
+  `include "rggen_host_if_common.svh"
+
   assign  o_pready  = i_response_ready;
   assign  o_prdata  = i_read_data;
   assign  o_pslverr = i_status[0];
@@ -34,7 +36,5 @@ module rggen_host_if_apb #(
   assign  o_read          = ~i_pwrite;
   assign  o_address       = i_paddr[LOCAL_ADDRESS_WIDTH-1:0];
   assign  o_write_data    = i_pwdata;
-  for (genvar i = 0;i < DATA_WIDTH / 8;i++) begin
-    assign  o_write_mask[i*8+:8]  = {8{i_pstrb[i]}};
-  end
+  assign  o_write_mask    = get_write_mask(i_pstrb);
 endmodule

data/rtl/register_block/rggen_host_if_axi4lite.sv

@@ -0,0 +1,251 @@
+module rggen_host_if_axi4lite #(
+  parameter DATA_WIDTH          = 32,
+  parameter HOST_ADDRESS_WIDTH  = 16,
+  parameter LOCAL_ADDRESS_WIDTH = 16,
+  parameter WRITE_PRIORITY      = 1
+)(
+  input                             clk,
+  input                             rst_n,
+  input                             i_awvalid,
+  output                            o_awready,
+  input   [HOST_ADDRESS_WIDTH-1:0]  i_awaddr,
+  input   [2:0]                     i_awprot,
+  input                             i_wvalid,
+  output                            o_wready,
+  input   [DATA_WIDTH-1:0]          i_wdata,
+  input   [DATA_WIDTH/8-1:0]        i_wstrb,
+  output                            o_bvalid,
+  input                             i_bready,
+  output  [1:0]                     o_bresp,
+  input                             i_arvalid,
+  output                            o_arready,
+  input   [HOST_ADDRESS_WIDTH-1:0]  i_araddr,
+  input   [2:0]                     i_arprot,
+  output                            o_rvalid,
+  input                             i_rready,
+  output  [DATA_WIDTH-1:0]          o_rdata,
+  output  [1:0]                     o_rresp,
+  output                            o_command_valid,
+  output                            o_write,
+  output                            o_read,
+  output  [LOCAL_ADDRESS_WIDTH-1:0] o_address,
+  output  [DATA_WIDTH-1:0]          o_write_data,
+  output  [DATA_WIDTH-1:0]          o_write_mask,
+  input                             i_response_ready,
+  input   [DATA_WIDTH-1:0]          i_read_data,
+  input   [1:0]                     i_status
+);
+  `include "rggen_host_if_common.svh"
+
+  typedef enum logic [5:0] {
+    IDLE              = 6'b000001,
+    WAIT_WDATA        = 6'b000010,
+    WRITE_IN_PROGRESS = 6'b000100,
+    WAIT_BRESP_READY  = 6'b001000,
+    READ_IN_PROGRESS  = 6'b010000,
+    WAIT_RDATA_READY  = 6'b100000
+  } e_state;
+
+  typedef enum logic [1:0] {
+    OKAY    = 2'b00,
+    EXOKAY  = 2'b01,
+    SLVERR  = 2'b10,
+    DECERR  = 2'b11
+  } e_resp;
+
+  function e_resp get_resp(logic [1:0] status);
+    case (1'b1)
+      status[0]:  return SLVERR;
+      status[1]:  return EXOKAY;
+      default:    return OKAY;
+    endcase
+  endfunction
+
+  e_state                         state;
+  logic                           awready;
+  logic                           wready;
+  logic                           bvalid;
+  e_resp                          bresp;
+  logic                           arready;
+  logic                           rvalid;
+  logic [DATA_WIDTH-1:0]          rdata;
+  e_resp                          rresp;
+  logic                           awack;
+  logic                           wack;
+  logic                           back;
+  logic                           arack;
+  logic                           rack;
+  logic                           command_valid;
+  logic                           local_done;
+  logic [LOCAL_ADDRESS_WIDTH-1:0] address;
+  logic [DATA_WIDTH-1:0]          write_data;
+  logic [DATA_WIDTH-1:0]          write_mask;
+
+//--------------------------------------------------------------
+// State machine
+//--------------------------------------------------------------
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      state <= IDLE;
+    end
+    else begin
+      unique case (state)
+        IDLE: begin
+          if (awack && wack) begin
+            state <= WRITE_IN_PROGRESS;
+          end
+          else if (awack) begin
+            state <= WAIT_WDATA;
+          end
+          else if (arack) begin
+            state <= READ_IN_PROGRESS;
+          end
+        end
+        WAIT_WDATA: begin
+          if (wack) begin
+            state <= WRITE_IN_PROGRESS;
+          end
+        end
+        WRITE_IN_PROGRESS: begin
+          if (local_done) begin
+            state <= WAIT_BRESP_READY;
+          end
+        end
+        WAIT_BRESP_READY: begin
+          if (back) begin
+            state <= IDLE;
+          end
+        end
+        READ_IN_PROGRESS: begin
+          if (local_done) begin
+            state <= WAIT_RDATA_READY;
+          end
+        end
+        WAIT_RDATA_READY: begin
+          if (rack) begin
+            state <= IDLE;
+          end
+        end
+        default: begin
+          state <= IDLE;
+        end
+      endcase
+    end
+  end
+
+//--------------------------------------------------------------
+// AXI4-Lite
+//--------------------------------------------------------------
+  assign  o_awready = awready;
+  assign  o_wready  = wready;
+  assign  o_bvalid  = bvalid;
+  assign  o_bresp   = bresp;
+  assign  o_arready = arready;
+  assign  o_rvalid  = rvalid;
+  assign  o_rdata   = rdata;
+  assign  o_rresp   = rresp;
+
+  assign  awack = i_awvalid & awready;
+  assign  wack  = i_wvalid  & wready;
+  assign  back  = bvalid    & i_bready;
+  assign  arack = i_arvalid & arready;
+  assign  rack  = rvalid    & i_rready;
+
+  generate
+    if (WRITE_PRIORITY) begin
+      assign  awready = state[0];
+      assign  wready  = (state[0] || state[1]) ? 1'b1 : 1'b0;
+      assign  bvalid  = state[3];
+      assign  arready = (state[0] && (!i_awvalid)) ? 1'b1 : 1'b0;
+      assign  rvalid  = state[5];
+    end
+    else begin
+      assign  awready = (state[0] && (!i_arvalid)) ? 1'b1 : 1'b0;
+      assign  wready  = ((state[0] && (!i_arvalid)) || state[1]) ? 1'b1 : 1'b0;
+      assign  bvalid  = state[3];
+      assign  arready = state[0];
+      assign  rvalid  = state[5];
+    end
+  endgenerate
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      bresp <= OKAY;
+    end
+    else if (state[2] && local_done) begin
+      bresp <= get_resp(i_status);
+    end
+    else if (back) begin
+      bresp <= OKAY;
+    end
+  end
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      rdata <= '0;
+      rresp <= OKAY;
+    end
+    else if (state[4] && local_done) begin
+      rdata <= i_read_data;
+      rresp <= get_resp(i_status);
+    end
+    else if (rack) begin
+      rdata <= '0;
+      rresp <= OKAY;
+    end
+  end
+
+//--------------------------------------------------------------
+// Local bus
+//--------------------------------------------------------------
+  assign  o_command_valid = command_valid;
+  assign  o_address       = address;
+  assign  o_write         = state[2];
+  assign  o_read          = state[4];
+  assign  o_write_data    = write_data;
+  assign  o_write_mask    = write_mask;
+
+  assign  local_done  = command_valid & i_response_ready;
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      command_valid <= 1'b0;
+    end
+    else if (wack || arack) begin
+      command_valid <= 1'b1;
+    end
+    else if (local_done) begin
+      command_valid <= 1'b0;
+    end
+  end
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      address <= '0;
+    end
+    else if (awack) begin
+      address <= i_awaddr[LOCAL_ADDRESS_WIDTH-1:0];
+    end
+    else if (arack) begin
+      address <= i_araddr[LOCAL_ADDRESS_WIDTH-1:0];
+    end
+    else if (local_done) begin
+      address <= '0;
+    end
+  end
+
+  always_ff @(posedge clk or negedge rst_n) begin
+    if (!rst_n) begin
+      write_data  <= '0;
+      write_mask  <= '0;
+    end
+    else if (wack) begin
+      write_data  <= i_wdata;
+      write_mask  <= get_write_mask(i_wstrb);
+    end
+    else if (local_done) begin
+      write_data  <= '0;
+      write_mask  <= '0;
+    end
+  end
+endmodule

data/rtl/register_block/rggen_host_if_common.svh

@@ -0,0 +1,9 @@
+function automatic logic [DATA_WIDTH-1:0] get_write_mask(
+  input [DATA_WIDTH/8-1:0]  strobe
+);
+  logic [DATA_WIDTH-1:0]  write_mask;
+  for (int i = 0;i < $size(strobe);i++) begin
+    write_mask[i*8+:8]  = {8{strobe[i]}};
+  end
+  return write_mask;
+endfunction

data/rtl/register_block/rggen_response_mux.sv

@@ -57,26 +57,27 @@ module rggen_response_mux #(
   assign  o_read_data = read_data;
   always_ff @(posedge clk or negedge rst_n) begin
     if (!rst_n)  begin
-      read_data <= {DATA_WIDTH{1'b0}};
+      read_data <= '0;
     end
     else if (response_valid && i_read) begin
-      read_data <= selected_data;
+      read_data <= select_read_data(
+        .select     (i_register_select    ),
+        .read_data  (i_register_read_data )
+      );
     end
     else begin
-      read_data <= {DATA_WIDTH{1'b0}};
+      read_data <= '0;
     end
   end
 
-  if (TOTAL_REGISTERS > 1) begin
-    for (genvar i = 0;i < DATA_WIDTH;i++) begin
-      logic [TOTAL_REGISTERS-1:0] temp;
-      assign  selected_data[i]  = |temp;
-      for (genvar j = 0;j < TOTAL_REGISTERS;j++) begin
-        assign  temp[j] = i_register_select[j] & i_register_read_data[j][i];
-      end
+  function automatic logic [DATA_WIDTH-1:0] select_read_data(
+    input logic [TOTAL_REGISTERS-1:0] select,
+    input logic [DATA_WIDTH-1:0]      read_data[TOTAL_REGISTERS]
+  );
+    logic [DATA_WIDTH-1:0]  masked_read_data[TOTAL_REGISTERS];
+    for (int i = 0;i < TOTAL_REGISTERS;i++) begin
+      masked_read_data[i] = {DATA_WIDTH{select[i]}} & read_data[i];
     end
-  end
-  else begin
-    assign  selected_data = i_register_read_data[0];
-  end
+    return masked_read_data.or();
+  endfunction
 endmodule

data/sample/sample_0.sv

@@ -211,75 +211,81 @@ module sample_0 (
   );
   assign register_read_data[3] = {bit_field_3_0_value};
   assign bit_field_3_0_value = i_bit_field_3_0;
-  for (genvar g_i = 0;g_i < 4;g_i++) begin : gen_register_4_0
-    rggen_address_decoder #(
-      .READABLE           (1),
-      .WRITABLE           (1),
-      .ADDRESS_WIDTH      (6),
-      .START_ADDRESS      (6'h04 + g_i),
-      .END_ADDRESS        (6'h04 + g_i),
-      .USE_SHADOW_INDEX   (0),
-      .SHADOW_INDEX_WIDTH (1),
-      .SHADOW_INDEX_VALUE (1'h0)
-    ) u_register_4_address_decoder (
-      .i_read         (read),
-      .i_write        (write),
-      .i_address      (address[7:2]),
-      .i_shadow_index (1'h0),
-      .o_select       (register_select[4+g_i])
-    );
-    assign register_read_data[4+g_i] = {bit_field_4_0_value[g_i], bit_field_4_1_value[g_i]};
-    assign bit_field_4_0_value[g_i] = i_bit_field_4_0[g_i];
-    assign o_bit_field_4_1[g_i] = bit_field_4_1_value[g_i];
-    rggen_bit_field_rw #(
-      .WIDTH          (16),
-      .INITIAL_VALUE  (16'h0000)
-    ) u_bit_field_4_1 (
-      .clk              (clk),
-      .rst_n            (rst_n),
-      .i_command_valid  (command_valid),
-      .i_select         (register_select[4+g_i]),
-      .i_write          (write),
-      .i_write_data     (write_data[15:0]),
-      .i_write_mask     (write_mask[15:0]),
-      .o_value          (bit_field_4_1_value[g_i])
-    );
-  end
-  for (genvar g_i = 0;g_i < 2;g_i++) begin : gen_register_5_0
-    for (genvar g_j = 0;g_j < 4;g_j++) begin : gen_register_5_1
-      assign register_5_shadow_index[g_i][g_j] = {bit_field_2_1_value, bit_field_0_0_value, bit_field_0_1_value};
+  generate if (1) begin : g_register_4
+    genvar g_i;
+    for (g_i = 0;g_i < 4;g_i++) begin : g
       rggen_address_decoder #(
         .READABLE           (1),
         .WRITABLE           (1),
         .ADDRESS_WIDTH      (6),
-        .START_ADDRESS      (6'h08),
-        .END_ADDRESS        (6'h08),
-        .USE_SHADOW_INDEX   (1),
-        .SHADOW_INDEX_WIDTH (33),
-        .SHADOW_INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]})
-      ) u_register_5_address_decoder (
+        .START_ADDRESS      (6'h04 + g_i),
+        .END_ADDRESS        (6'h04 + g_i),
+        .USE_SHADOW_INDEX   (0),
+        .SHADOW_INDEX_WIDTH (1),
+        .SHADOW_INDEX_VALUE (1'h0)
+      ) u_register_4_address_decoder (
         .i_read         (read),
         .i_write        (write),
         .i_address      (address[7:2]),
-        .i_shadow_index (register_5_shadow_index[g_i][g_j]),
-        .o_select       (register_select[8+4*g_i+g_j])
+        .i_shadow_index (1'h0),
+        .o_select       (register_select[4+g_i])
       );
-      assign register_read_data[8+4*g_i+g_j] = {bit_field_5_0_value[g_i][g_j], bit_field_5_1_value[g_i][g_j]};
-      assign bit_field_5_0_value[g_i][g_j] = i_bit_field_5_0[g_i][g_j];
-      assign o_bit_field_5_1[g_i][g_j] = bit_field_5_1_value[g_i][g_j];
+      assign register_read_data[4+g_i] = {bit_field_4_0_value[g_i], bit_field_4_1_value[g_i]};
+      assign bit_field_4_0_value[g_i] = i_bit_field_4_0[g_i];
+      assign o_bit_field_4_1[g_i] = bit_field_4_1_value[g_i];
       rggen_bit_field_rw #(
         .WIDTH          (16),
         .INITIAL_VALUE  (16'h0000)
-      ) u_bit_field_5_1 (
+      ) u_bit_field_4_1 (
         .clk              (clk),
         .rst_n            (rst_n),
         .i_command_valid  (command_valid),
-        .i_select         (register_select[8+4*g_i+g_j]),
+        .i_select         (register_select[4+g_i]),
         .i_write          (write),
         .i_write_data     (write_data[15:0]),
         .i_write_mask     (write_mask[15:0]),
-        .o_value          (bit_field_5_1_value[g_i][g_j])
+        .o_value          (bit_field_4_1_value[g_i])
       );
     end
-  end
+  end endgenerate
+  generate if (1) begin : g_register_5
+    genvar g_i, g_j;
+    for (g_i = 0;g_i < 2;g_i++) begin : g
+      for (g_j = 0;g_j < 4;g_j++) begin : g
+        assign register_5_shadow_index[g_i][g_j] = {bit_field_2_1_value, bit_field_0_0_value, bit_field_0_1_value};
+        rggen_address_decoder #(
+          .READABLE           (1),
+          .WRITABLE           (1),
+          .ADDRESS_WIDTH      (6),
+          .START_ADDRESS      (6'h08),
+          .END_ADDRESS        (6'h08),
+          .USE_SHADOW_INDEX   (1),
+          .SHADOW_INDEX_WIDTH (33),
+          .SHADOW_INDEX_VALUE ({1'h1, g_i[15:0], g_j[15:0]})
+        ) u_register_5_address_decoder (
+          .i_read         (read),
+          .i_write        (write),
+          .i_address      (address[7:2]),
+          .i_shadow_index (register_5_shadow_index[g_i][g_j]),
+          .o_select       (register_select[8+4*g_i+g_j])
+        );
+        assign register_read_data[8+4*g_i+g_j] = {bit_field_5_0_value[g_i][g_j], bit_field_5_1_value[g_i][g_j]};
+        assign bit_field_5_0_value[g_i][g_j] = i_bit_field_5_0[g_i][g_j];
+        assign o_bit_field_5_1[g_i][g_j] = bit_field_5_1_value[g_i][g_j];
+        rggen_bit_field_rw #(
+          .WIDTH          (16),
+          .INITIAL_VALUE  (16'h0000)
+        ) u_bit_field_5_1 (
+          .clk              (clk),
+          .rst_n            (rst_n),
+          .i_command_valid  (command_valid),
+          .i_select         (register_select[8+4*g_i+g_j]),
+          .i_write          (write),
+          .i_write_data     (write_data[15:0]),
+          .i_write_mask     (write_mask[15:0]),
+          .o_value          (bit_field_5_1_value[g_i][g_j])
+        );
+      end
+    end
+  end endgenerate
 endmodule

data/setup/default.rb

@@ -4,7 +4,7 @@ enable :register      , [:offset_address, :name, :array, :shadow, :accessibility
 enable :bit_field     , [:bit_assignment, :name, :type, :initial_value, :reference]
 enable :bit_field     , :type, [:rw, :ro, :reserved]
 enable :register_block, [:module_definition, :signal_declarations, :clock_reset, :host_if, :response_mux]
-enable :register_block, :host_if, [:apb]
+enable :register_block, :host_if, [:apb, :axi4lite]
 enable :register      , [:address_decoder, :read_data]
 enable :register_block, [:ral_package_definition, :block_model_definition, :reg_model_declarations, :block_model_constructor, :reg_model_creator, :block_model_default_map_creator]
 enable :register      , [:reg_model_definition, :field_model_declarations, :reg_model_constructor, :field_model_creator, :shadow_index_configurator, :reg_model_declaration, :reg_model_creation]

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.3.2
+  version: 0.3.3
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2016-04-15 00:00:00.000000000 Z
+date: 2016-04-20 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: baby_erubis
@@ -110,7 +110,7 @@ dependencies:
         version: '0.35'
 description: |2
       RgGen is a code generation tool for SoC designers.
-      It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
+      It will automatically generate source code for control registers in a SoC design, e.g. RTL, UVM RAL model, from its register map document.
       Also RgGen is customizable so you can build your specific generate tool.
 email:
 - taichi730@gmail.com
@@ -119,8 +119,6 @@ executables:
 extensions: []
 extra_rdoc_files: []
 files:
-- ".rubocop.yml"
-- ".rubocop_todo.yml"
 - CODE_OF_CONDUCT.md
 - LICENSE.txt
 - README.md
@@ -179,6 +177,8 @@ files:
 - lib/rggen/builtins/register/uniqueness_validator.rb
 - lib/rggen/builtins/register_block/apb.erb
 - lib/rggen/builtins/register_block/apb.rb
+- lib/rggen/builtins/register_block/axi4lite.erb
+- lib/rggen/builtins/register_block/axi4lite.rb
 - lib/rggen/builtins/register_block/base_address.rb
 - lib/rggen/builtins/register_block/block_model_constructor.rb
 - lib/rggen/builtins/register_block/block_model_default_map_creator.rb
@@ -197,6 +197,7 @@ files:
 - lib/rggen/commands.rb
 - lib/rggen/core_components.rb
 - lib/rggen/core_components/configuration/configuration_factory.rb
+- lib/rggen/core_components/configuration/item.rb
 - lib/rggen/core_components/configuration/item_factory.rb
 - lib/rggen/core_components/configuration/raise_error.rb
 - lib/rggen/core_components/configuration/setup.rb
@@ -253,11 +254,12 @@ files:
 - ral/rggen_ral_pkg.sv
 - ral/rggen_ral_reg.svh
 - ral/rggen_ral_shadow_reg.svh
-- rggen.gemspec
 - rtl/bit_field/rggen_bit_field_rw.sv
 - rtl/compile.f
 - rtl/register/rggen_address_decoder.sv
 - rtl/register_block/rggen_host_if_apb.sv
+- rtl/register_block/rggen_host_if_axi4lite.sv
+- rtl/register_block/rggen_host_if_common.svh
 - rtl/register_block/rggen_response_mux.sv
 - sample/sample.csv
 - sample/sample.json
@@ -270,7 +272,7 @@ files:
 - sample/sample_1_ral_pkg.sv
 - sample/sample_setup.rb
 - setup/default.rb
-homepage: ''
+homepage: https://github.com/taichi-ishitani/rggen
 licenses:
 - MIT
 metadata: {}

data/.rubocop.yml

@@ -1,7 +0,0 @@
-inherit_from: .rubocop_todo.yml
-
-AllCops:
-  Exclude:
-    - 'sample/*'
-    - 'setup/*'
-    - 'spec/**/*'

data/.rubocop_todo.yml

@@ -1,91 +0,0 @@
-# This configuration was generated by
-# `rubocop --auto-gen-config`
-# on 2015-12-27 19:46:19 +0900 using RuboCop version 0.35.1.
-# The point is for the user to remove these configuration records
-# one by one as the offenses are removed from the code base.
-# Note that changes in the inspected code, or installation of new
-# versions of RuboCop, may require this file to be generated again.
-
-# Offense count: 2
-Lint/FormatParameterMismatch:
-  Exclude:
-    - 'lib/rgen/core_components/rtl/item.rb'
-
-# Offense count: 3
-Metrics/AbcSize:
-  Max: 18
-
-# Offense count: 1
-Metrics/CyclomaticComplexity:
-  Max: 7
-
-# Offense count: 8
-# Configuration parameters: AllowURI, URISchemes.
-Metrics/LineLength:
-  Max: 142
-
-# Offense count: 1
-# Configuration parameters: CountComments.
-Metrics/MethodLength:
-  Max: 11
-
-# Offense count: 72
-# Configuration parameters: Exclude.
-Style/Documentation:
-  Enabled: false
-
-# Offense count: 56
-# Cop supports --auto-correct.
-# Configuration parameters: AllowForAlignment.
-Style/ExtraSpacing:
-  Enabled: false
-
-# Offense count: 2
-# Cop supports --auto-correct.
-# Configuration parameters: EnforcedStyle, SupportedStyles, UseHashRocketsWithSymbolValues.
-Style/HashSyntax:
-  Enabled: false
-
-# Offense count: 33
-# Cop supports --auto-correct.
-Style/SingleSpaceBeforeFirstArg:
-  Exclude:
-    - 'lib/rgen/builtins/register_block/apb.rb'
-    - 'lib/rgen/core_components/configuration/setup.rb'
-    - 'lib/rgen/core_components/register_map/generic_map.rb'
-    - 'lib/rgen/core_components/register_map/setup.rb'
-    - 'lib/rgen/core_components/rtl/setup.rb'
-    - 'lib/rgen/output_base/line.rb'
-
-# Offense count: 28
-# Cop supports --auto-correct.
-# Configuration parameters: MultiSpaceAllowedForOperators.
-Style/SpaceAroundOperators:
-  Enabled: false
-
-# Offense count: 42
-# Cop supports --auto-correct.
-Style/SpaceBeforeComma:
-  Exclude:
-    - 'lib/rgen/builder/list_item_entry.rb'
-    - 'lib/rgen/builtins/bit_field/type.rb'
-    - 'lib/rgen/builtins/register_block/apb.rb'
-    - 'lib/rgen/builtins/register_block/clock_reset.rb'
-    - 'lib/rgen/builtins/register_block/host_if.rb'
-    - 'lib/rgen/builtins/register_block/response_mux.rb'
-    - 'lib/rgen/commands.rb'
-    - 'lib/rgen/core_extensions/forwardable.rb'
-    - 'rgen.gemspec'
-
-# Offense count: 5
-# Cop supports --auto-correct.
-Style/SpaceInsideBrackets:
-  Exclude:
-    - 'lib/rgen/commands.rb'
-
-# Offense count: 2
-# Cop supports --auto-correct.
-Style/SpaceInsideParens:
-  Exclude:
-    - 'lib/rgen/builder/category.rb'
-

data/rggen.gemspec

@@ -1,46 +0,0 @@
-# coding: utf-8
-lib = File.expand_path('../lib', __FILE__)
-$LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
-require 'rggen/version'
-
-Gem::Specification.new do |spec|
-  spec.name                   = 'rggen'
-  spec.version                = RgGen::VERSION
-  spec.required_ruby_version  = '>= 2.0'
-  spec.authors                = ['Taichi Ishitani']
-  spec.email                  = ['taichi730@gmail.com']
-  spec.homepage               = 'https://github.com/taichi-ishitani/rggen'
-
-  spec.summary        = 'Code generation tool for control registers in a SoC design.'
-  spec.description    = <<-EOS
-    RgGen is a code generation tool for SoC designers.
-    It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
-    Also RgGen is customizable so you can build your specific generate tool.
-  EOS
-  spec.homepage       = ''
-  spec.license        = 'MIT'
-
-  spec.files          = `git ls-files -z`.split("\x0").reject { |f|
-    f =~ %r{^(?:
-      bin/setup
-      |spec/.*
-      |Gemfile
-      |Rakefile
-      |.gitignore
-      |.rspec
-      |.travis.yml
-    )$}x
-  }
-  spec.bindir         = 'bin'
-  spec.executables    = ['rggen']
-  spec.require_paths  = ['lib']
-
-  spec.add_runtime_dependency 'baby_erubis', '>= 2.0'
-  spec.add_runtime_dependency 'facets'     , '>= 3.0'
-  spec.add_runtime_dependency 'roo'        , '>= 2.1.1'
-  spec.add_runtime_dependency 'spreadsheet', '>= 1.0.3'
-
-  spec.add_development_dependency 'rake'   , '~> 10.0'
-  spec.add_development_dependency 'rspec'  , '>=  3.3'
-  spec.add_development_dependency 'rubocop', '>=  0.35'
-end