rggen 0.3.1 → 0.3.2
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +30 -17
- data/bin/rggen +0 -0
- data/lib/rggen/generator.rb +9 -0
- data/lib/rggen/version.rb +1 -1
- data/ral/compile.f +1 -3
- data/ral/rggen_ral_shadow_reg.svh +41 -41
- data/rtl/compile.f +4 -0
- data/sample/sample.xls +0 -0
- metadata +3 -2
checksums.yaml
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SHA1:
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metadata.gz:
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data.tar.gz: 2c08390336ae73726a619515cc9ed8a61d08eafa
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SHA512:
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data.tar.gz: ad4a174a3355412060839b9af4e38de1b79438eb001d52c809756c7addc357124beb1c8503700bb95f826751811f722dc0337ec6610536a5ca83debfe8177ac1
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data/README.md
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@@ -9,6 +9,12 @@ RgGen is a code generation tool for SoC designers.
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It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
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Also RgGen is customizable so you can build your specific generate tool.
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## Ruby
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RgGen is written in the [*Ruby*](https://www.ruby-lang.org/en/about/) programing language and supports version 2.0 or later.
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If you don't have above version of Ruby, you need to install the Ruby at first.
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To install the Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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## Installation
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To install RgGen and required libraries, use the following command:
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$ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
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$ export GEM_PATH=YOUR_INSTALL_DIRECTORY
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-
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## Usage
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###
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### Writing Configuration File
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A configuration file is to describe attributes of your design, e.g. data bus width, address bus width, host interface protocol.
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RgGen supports YAML and JSON for its file format and allows to use Hash notation to describe attributes of your design like below.
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These attributes have default values. If you use a default value, you don't specify its value.
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In addition, if you use default values for all of attributes, you don't need to write a configuration file.
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###
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### Writing Register Map Document
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RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
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To do this, you need to write your register map document according to below table format.
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By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
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###
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### Generating Source Code
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To generate soruce code from your register map document, use the following command:
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- RTL
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- `your_block_name`.sv
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- RAL model
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- `your_block_name`_ral_pkg.sv
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- `your_block_name`_ral_pkg.sv
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### Compiling Your Design
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-
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RgGen has base RTL modules and RAL model package (the base library) to build generated RTL and UVM RAL models.
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Therefore, To compile your design with the base library, you need followins steps:
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1. Set the RGGEN_HOME environment variable
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2. Link the base library with you design
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**RGGEN_HOME** environement variable is to show the install direcoty.
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To set the variable, you can use `--show-home` option like below:
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$ export RGGEN_HOME=`rggen --show-home`
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To link the base library with your design, RgGen has file lists for the base library.
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By using the lists, you can compile your design and the base library like below:
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$ simulator \
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ral/your_register_block_ral_pkg.sv \
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your_design.v
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-f $RGGEN_HOME/rtl/compile.f \
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-f $RGGEN_HOME/ral/compile.f \
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rtl/your_register_block.sv \
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ral/your_register_block_ral_pkg.sv \
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your_test_bench.sv \
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your_design.v
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### Note
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@@ -115,7 +129,6 @@ To install this gem onto your local machine, run `bundle exec rake install`. To
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Bug reports and pull requests are welcome on GitHub at https://github.com/taichi-ishitani/rggen. This project is intended to be a safe, welcoming space for collaboration, and contributors are expected to adhere to the [Contributor Covenant](http://contributor-covenant.org) code of conduct.
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-
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## License
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Copyright © 2015-2016 [Taichi Ishitani](mailto:taichi730@gmail.com).
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data/bin/rggen
CHANGED
File without changes
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data/lib/rggen/generator.rb
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@@ -92,6 +92,15 @@ module RgGen
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end
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end
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add_option :show_home do |option|
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option.long = '--show-home'
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option.description = 'Display the path of RgGen tool home directory'
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option.body = proc do
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puts RGGEN_HOME
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exit
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end
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end
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add_option :version do |option|
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option.short = '-v'
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option.long = '--version'
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data/lib/rggen/version.rb
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data/ral/compile.f
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`ifndef
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`define
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typedef class
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typedef class
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`ifndef __RGGEN_RAL_SHADOW_REG_SVH__
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`define __RGGEN_RAL_SHADOW_REG_SVH__
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typedef class rggen_ral_shadow_reg_index;
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typedef class rggen_ral_shadow_reg_ftdr_seq;
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class
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protected
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class rggen_ral_shadow_reg extends rggen_ral_reg;
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protected rggen_ral_shadow_reg_index shadow_reg_indexes[$];
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extern function new(string name, int unsigned n_bits, int has_coverage);
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extern protected function void set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
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endclass
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function
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function rggen_ral_shadow_reg::new(string name, int unsigned n_bits, int has_coverage);
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super.new(name, n_bits, has_coverage);
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endfunction
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function void
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function void rggen_ral_shadow_reg::configure(
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uvm_object cfg,
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uvm_reg_block blk_parent,
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uvm_reg_file regfile_parent,
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configure_shadow_indexes();
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endfunction
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function uvm_reg_frontdoor
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function uvm_reg_frontdoor rggen_ral_shadow_reg::create_frontdoor();
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rggen_ral_shadow_reg_ftdr_seq fd = new(shadow_reg_indexes);
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return fd;
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endfunction
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function bit
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function bit rggen_ral_shadow_reg::is_active();
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foreach (shadow_reg_indexes[i]) begin
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if (!shadow_reg_indexes[i].is_matched()) begin
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return 0;
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return 1;
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endfunction
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function void
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function void rggen_ral_shadow_reg::configure_shadow_indexes();
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endfunction
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function void
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function void rggen_ral_shadow_reg::set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
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rggen_ral_shadow_reg_index shadow_reg_index;
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shadow_reg_index = new(this, reg_name, field_name, value);
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shadow_reg_indexes.push_back(shadow_reg_index);
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endfunction
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class
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protected string
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protected string
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protected uvm_reg_data_t
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protected uvm_reg_field
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class rggen_ral_shadow_reg_index;
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protected rggen_ral_shadow_reg shadow_reg;
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protected string reg_name;
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protected string field_name;
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protected uvm_reg_data_t value;
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protected uvm_reg_field index_field;
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extern function new(
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string
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string
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uvm_reg_data_t
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rggen_ral_shadow_reg shadow_reg,
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string reg_name,
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string field_name,
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uvm_reg_data_t value
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);
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extern virtual function bit is_matched();
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extern protected virtual function uvm_reg_field get_index_field();
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endclass
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function
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function rggen_ral_shadow_reg_index::new(
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rggen_ral_shadow_reg shadow_reg,
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string reg_name,
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string field_name,
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uvm_reg_data_t value
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);
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this.shadow_reg = shadow_reg;
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this.reg_name = reg_name;
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this.value = value;
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endfunction
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function bit
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function bit rggen_ral_shadow_reg_index::is_matched();
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uvm_reg_field field = get_index_field();
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return (field.value == value) ? 1 : 0;
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endfunction
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task
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task rggen_ral_shadow_reg_index::update(
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output uvm_status_e status,
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input uvm_path_e path,
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input uvm_reg_map map,
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parent_reg.update(status, path, map, parent, prior, extension, fname, lineno);
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endtask
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function uvm_reg_field
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function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
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if (index_field == null) begin
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uvm_reg_block parent_block = shadow_reg.get_parent();
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uvm_reg index_reg;
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index_reg = parent_block.get_reg_by_name(reg_name);
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if (index_reg == null) begin
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`uvm_fatal("
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`uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
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return null;
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end
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index_field = index_reg.get_field_by_name(field_name);
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if (index_field == null) begin
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`uvm_fatal("
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`uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
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return null;
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end
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end
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return index_field;
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endfunction
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class
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class rggen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
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protected rggen_ral_shadow_reg_index shadow_indexes[$];
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extern function new(ref
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extern function new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
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extern virtual task body();
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endclass
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function
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super.new("
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function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
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super.new("rggen_ral_shadow_reg_ftdr_seq");
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foreach (shadow_indexes[i]) begin
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this.shadow_indexes.push_back(shadow_indexes[i]);
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end
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endfunction
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task
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task rggen_ral_shadow_reg_ftdr_seq::body();
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foreach (shadow_indexes[i]) begin
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uvm_status_e status;
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shadow_indexes[i].update(
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rw_info.lineno
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);
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if (status == UVM_NOT_OK) begin
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`uvm_warning("
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`uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
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rw_info.status = status;
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return;
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end
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data/rtl/compile.f
ADDED
data/sample/sample.xls
CHANGED
Binary file
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metadata
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--- !ruby/object:Gem::Specification
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name: rggen
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version: !ruby/object:Gem::Version
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version: 0.3.
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version: 0.3.2
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2016-04-
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date: 2016-04-15 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: baby_erubis
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- ral/rggen_ral_shadow_reg.svh
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- rggen.gemspec
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- rtl/bit_field/rggen_bit_field_rw.sv
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- rtl/compile.f
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- rtl/register/rggen_address_decoder.sv
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- rtl/register_block/rggen_host_if_apb.sv
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- rtl/register_block/rggen_response_mux.sv
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