rggen 0.3.1 → 0.3.2

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -9,6 +9,12 @@ RgGen is a code generation tool for SoC designers.
 It will automatically generate source code for control registers in a SoC design, e.g. RLT, UVM RAL model, from its register map document.
 Also RgGen is customizable so you can build your specific generate tool.
 
+## Ruby
+
+RgGen is written in the [*Ruby*](https://www.ruby-lang.org/en/about/) programing language and supports version 2.0 or later.
+If you don't have above version of Ruby, you need to install the Ruby at first.
+To install the Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
+
 ## Installation
 
 To install RgGen and required libraries, use the following command:
@@ -22,10 +28,9 @@ If you want to install them on other location, you need to specify the install d
     $ gem install --install-dir YOUR_INSTALL_DIRECTORY rggen
     $ export GEM_PATH=YOUR_INSTALL_DIRECTORY
 
-
 ## Usage
 
-### Write Configuration File
+### Writing Configuration File
 
 A configuration file is to describe attributes of your design, e.g. data bus width, address bus width, host interface protocol.
 RgGen supports YAML and JSON for its file format and allows to use Hash notation to describe attributes of your design like below.
@@ -48,7 +53,7 @@ host_if: apb
 These attributes have default values. If you use a default value, you don't specify its value.
 In addition, if you use default values for all of attributes, you don't need to write a configuration file.
 
-### Write Register Map Document
+### Writing Register Map Document
 
 RgGen allows to use a spreadsheet to input the register map of your design so you can directly input your register map document to RgGen.
 To do this, you need to write your register map document according to below table format.
@@ -68,7 +73,7 @@ To do this, you need to write your register map document according to below tabl
 
 By default, RgGen supports CSV, ODS, XLS and XLSX sparedsheet file types.
 
-### Generate Source Code
+### Generating Source Code
 
 To generate soruce code from your register map document, use the following command:
 
@@ -83,22 +88,31 @@ In addition, file name of generated files is accoding to below rule.
 - RTL
   - `your_block_name`.sv
 - RAL model
-  - `your_block_name`_ral_pkg.sv 
+  - `your_block_name`_ral_pkg.sv
+
+### Compiling Your Design
 
-### Compile Your Design
+RgGen has base RTL modules and RAL model package (the base library) to build generated RTL and UVM RAL models.
+Therefore, To compile your design with the base library, you need followins steps:
 
-RgGen has base RTL modules and RAL model classes to build RTL and UVM RAL model.
-Therefore, when you compile your design, you need to add these base modules and classes like below.
+1. Set the RGGEN_HOME environment variable
+2. Link the base library with you design
+
+**RGGEN_HOME** environement variable is to show the install direcoty.
+To set the variable, you can use `--show-home` option like below:
+
+    $ export RGGEN_HOME=`rggen --show-home`
+
+To link the base library with your design, RgGen has file lists for the base library.
+By using the lists, you can compile your design and the base library like below:
 
     $ simulator \
-        +libext+.sv \
-        -y $RGGEN_INSTALL_DIRECTORY/rtl/register_block \
-        -y $RGGEN_INSTALL_DIRECTORY/rtl/register \
-        -y $RGGEN_INSTALL_DIRECTORY/rtl/bit_field \
-        -f $RGGEN_INSTALL_DIRECTORY/ral/compile.f \
-        rtl/your_register_block.sv \
-        ral/your_register_block_ral_pkg.sv \
-        your_design.v
+      -f $RGGEN_HOME/rtl/compile.f \
+      -f $RGGEN_HOME/ral/compile.f \
+      rtl/your_register_block.sv \
+      ral/your_register_block_ral_pkg.sv \
+      your_test_bench.sv \
+      your_design.v
 
 ### Note
 
@@ -115,7 +129,6 @@ To install this gem onto your local machine, run `bundle exec rake install`. To
 
 Bug reports and pull requests are welcome on GitHub at https://github.com/taichi-ishitani/rggen. This project is intended to be a safe, welcoming space for collaboration, and contributors are expected to adhere to the [Contributor Covenant](http://contributor-covenant.org) code of conduct.
 
-
 ## License
 
 Copyright © 2015-2016 [Taichi Ishitani](mailto:taichi730@gmail.com).

data/lib/rggen/generator.rb

@@ -92,6 +92,15 @@ module RgGen
       end
     end
 
+    add_option :show_home do |option|
+      option.long         = '--show-home'
+      option.description  = 'Display the path of RgGen tool home directory'
+      option.body         = proc do
+        puts RGGEN_HOME
+        exit
+      end
+    end
+
     add_option :version do |option|
       option.short        = '-v'
       option.long         = '--version'

data/lib/rggen/version.rb

@@ -1,6 +1,6 @@
 module RgGen
   MAJOR   = 0
   MINOR   = 3
-  TEENY   = 1
+  TEENY   = 2
   VERSION = "#{MAJOR}.#{MINOR}.#{TEENY}".freeze
 end

data/ral/compile.f

@@ -1,4 +1,2 @@
-+incdir+${UVM_HOME}/src
 +incdir+${RGGEN_HOME}/ral
-${UVM_HOME}/src/uvm_pkg.sv
-${RGGEN_HOME}/ral/rgen_ral_pkg.sv
+${RGGEN_HOME}/ral/rggen_ral_pkg.sv

data/ral/rggen_ral_shadow_reg.svh

@@ -1,10 +1,10 @@
-`ifndef __RGEN_RAL_SHADOW_REG_SVH__
-`define __RGEN_RAL_SHADOW_REG_SVH__
-typedef class rgen_ral_shadow_reg_index;
-typedef class rgen_ral_shadow_reg_ftdr_seq;
+`ifndef __RGGEN_RAL_SHADOW_REG_SVH__
+`define __RGGEN_RAL_SHADOW_REG_SVH__
+typedef class rggen_ral_shadow_reg_index;
+typedef class rggen_ral_shadow_reg_ftdr_seq;
 
-class rgen_ral_shadow_reg extends rgen_ral_reg;
-  protected rgen_ral_shadow_reg_index shadow_reg_indexes[$];
+class rggen_ral_shadow_reg extends rggen_ral_reg;
+  protected rggen_ral_shadow_reg_index  shadow_reg_indexes[$];
 
   extern function new(string name, int unsigned n_bits, int has_coverage);
 
@@ -23,11 +23,11 @@ class rgen_ral_shadow_reg extends rgen_ral_reg;
   extern protected function void set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
 endclass
 
-function rgen_ral_shadow_reg::new(string name, int unsigned n_bits, int has_coverage);
+function rggen_ral_shadow_reg::new(string name, int unsigned n_bits, int has_coverage);
   super.new(name, n_bits, has_coverage);
 endfunction
 
-function void rgen_ral_shadow_reg::configure(
+function void rggen_ral_shadow_reg::configure(
   uvm_object    cfg,
   uvm_reg_block blk_parent,
   uvm_reg_file  regfile_parent,
@@ -38,12 +38,12 @@ function void rgen_ral_shadow_reg::configure(
   configure_shadow_indexes();
 endfunction
 
-function uvm_reg_frontdoor rgen_ral_shadow_reg::create_frontdoor();
-  rgen_ral_shadow_reg_ftdr_seq  fd  = new(shadow_reg_indexes);
+function uvm_reg_frontdoor rggen_ral_shadow_reg::create_frontdoor();
+  rggen_ral_shadow_reg_ftdr_seq fd  = new(shadow_reg_indexes);
   return fd;
 endfunction
 
-function bit rgen_ral_shadow_reg::is_active();
+function bit rggen_ral_shadow_reg::is_active();
   foreach (shadow_reg_indexes[i]) begin
     if (!shadow_reg_indexes[i].is_matched()) begin
       return 0;
@@ -52,27 +52,27 @@ function bit rgen_ral_shadow_reg::is_active();
   return 1;
 endfunction
 
-function void rgen_ral_shadow_reg::configure_shadow_indexes();
+function void rggen_ral_shadow_reg::configure_shadow_indexes();
 endfunction
 
-function void rgen_ral_shadow_reg::set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
-  rgen_ral_shadow_reg_index shadow_reg_index;
+function void rggen_ral_shadow_reg::set_shadow_index(string reg_name, string field_name, uvm_reg_data_t value);
+  rggen_ral_shadow_reg_index shadow_reg_index;
   shadow_reg_index  = new(this, reg_name, field_name, value);
   shadow_reg_indexes.push_back(shadow_reg_index);
 endfunction
 
-class rgen_ral_shadow_reg_index;
-  protected rgen_ral_shadow_reg shadow_reg;
-  protected string              reg_name;
-  protected string              field_name;
-  protected uvm_reg_data_t      value;
-  protected uvm_reg_field       index_field;
+class rggen_ral_shadow_reg_index;
+  protected rggen_ral_shadow_reg  shadow_reg;
+  protected string                reg_name;
+  protected string                field_name;
+  protected uvm_reg_data_t        value;
+  protected uvm_reg_field         index_field;
 
   extern function new(
-    rgen_ral_shadow_reg shadow_reg,
-    string              reg_name,
-    string              field_name,
-    uvm_reg_data_t      value
+    rggen_ral_shadow_reg  shadow_reg,
+    string                reg_name,
+    string                field_name,
+    uvm_reg_data_t        value
   );
 
   extern virtual function bit is_matched();
@@ -90,11 +90,11 @@ class rgen_ral_shadow_reg_index;
   extern protected virtual function uvm_reg_field get_index_field();
 endclass
 
-function rgen_ral_shadow_reg_index::new(
-  rgen_ral_shadow_reg shadow_reg,
-  string              reg_name,
-  string              field_name,
-  uvm_reg_data_t      value
+function rggen_ral_shadow_reg_index::new(
+  rggen_ral_shadow_reg  shadow_reg,
+  string                reg_name,
+  string                field_name,
+  uvm_reg_data_t        value
 );
   this.shadow_reg = shadow_reg;
   this.reg_name   = reg_name;
@@ -102,12 +102,12 @@ function rgen_ral_shadow_reg_index::new(
   this.value      = value;
 endfunction
 
-function bit rgen_ral_shadow_reg_index::is_matched();
+function bit rggen_ral_shadow_reg_index::is_matched();
   uvm_reg_field field = get_index_field();
   return (field.value == value) ? 1 : 0;
 endfunction
 
-task rgen_ral_shadow_reg_index::update(
+task rggen_ral_shadow_reg_index::update(
   output  uvm_status_e      status,
   input   uvm_path_e        path,
   input   uvm_reg_map       map,
@@ -123,42 +123,42 @@ task rgen_ral_shadow_reg_index::update(
   parent_reg.update(status, path, map, parent, prior, extension, fname, lineno);
 endtask
 
-function uvm_reg_field rgen_ral_shadow_reg_index::get_index_field();
+function uvm_reg_field rggen_ral_shadow_reg_index::get_index_field();
   if (index_field == null) begin
     uvm_reg_block parent_block  = shadow_reg.get_parent();
     uvm_reg       index_reg;
 
     index_reg = parent_block.get_reg_by_name(reg_name);
     if (index_reg == null) begin
-      `uvm_fatal("rgen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
+      `uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index register: %s", reg_name))
       return null;
     end
 
     index_field = index_reg.get_field_by_name(field_name);
     if (index_field == null) begin
-      `uvm_fatal("rgen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
+      `uvm_fatal("rggen_ral_shadow_reg_index", $sformatf("Unable to locate index field: %s", field_name))
       return null;
     end
   end
   return index_field;
 endfunction
 
-class rgen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
-  protected rgen_ral_shadow_reg_index shadow_indexes[$];
+class rggen_ral_shadow_reg_ftdr_seq extends uvm_reg_frontdoor;
+  protected rggen_ral_shadow_reg_index  shadow_indexes[$];
 
-  extern function new(ref rgen_ral_shadow_reg_index shadow_indexes[$]);
+  extern function new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
 
   extern virtual task body();
 endclass
 
-function rgen_ral_shadow_reg_ftdr_seq::new(ref rgen_ral_shadow_reg_index shadow_indexes[$]);
-  super.new("rgen_ral_shadow_reg_ftdr_seq");
+function rggen_ral_shadow_reg_ftdr_seq::new(ref rggen_ral_shadow_reg_index shadow_indexes[$]);
+  super.new("rggen_ral_shadow_reg_ftdr_seq");
   foreach (shadow_indexes[i]) begin
     this.shadow_indexes.push_back(shadow_indexes[i]);
   end
 endfunction
 
-task rgen_ral_shadow_reg_ftdr_seq::body();
+task rggen_ral_shadow_reg_ftdr_seq::body();
   foreach (shadow_indexes[i]) begin
     uvm_status_e  status;
     shadow_indexes[i].update(
@@ -172,7 +172,7 @@ task rgen_ral_shadow_reg_ftdr_seq::body();
       rw_info.lineno
     );
     if (status == UVM_NOT_OK) begin
-      `uvm_warning("rgen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
+      `uvm_warning("rggen_ral_shadow_reg_ftdr_seq", "Updating index field failed")
       rw_info.status  = status;
       return;
     end

data/rtl/compile.f

@@ -0,0 +1,4 @@
++libext+.sv
+-y ${RGGEN_HOME}/rtl/bit_field
+-y ${RGGEN_HOME}/rtl/register
+-y ${RGGEN_HOME}/rtl/register_block

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.3.1
+  version: 0.3.2
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2016-04-14 00:00:00.000000000 Z
+date: 2016-04-15 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: baby_erubis
@@ -255,6 +255,7 @@ files:
 - ral/rggen_ral_shadow_reg.svh
 - rggen.gemspec
 - rtl/bit_field/rggen_bit_field_rw.sv
+- rtl/compile.f
 - rtl/register/rggen_address_decoder.sv
 - rtl/register_block/rggen_host_if_apb.sv
 - rtl/register_block/rggen_response_mux.sv