rggen 0.28.0 → 0.29.0

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Files changed (5) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE +1 -1
  3. data/README.md +5 -5
  4. data/lib/rggen/version.rb +1 -1
  5. metadata +17 -17
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data/LICENSE CHANGED
@@ -1,6 +1,6 @@
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  The MIT License (MIT)
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- Copyright (c) 2019-2022 Taichi Ishitani
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+ Copyright (c) 2019-2023 Taichi Ishitani
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  Permission is hereby granted, free of charge, to any person obtaining a copy
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  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -11,7 +11,7 @@
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  # RgGen
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- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.
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+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate source code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), C header file, Wiki documents, from human readable register map specifications.
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  RgGen has following features:
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@@ -44,7 +44,7 @@ RgGen has following features:
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  ### Ruby
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- RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.6 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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+ RgGen is written in the [Ruby](https://www.ruby-lang.org/en/about/) programing language and its required version is 2.7 or later. You need to install any of these versions of Ruby before installing RgGen tool. To install Ruby, see [this page](https://www.ruby-lang.org/en/downloads/).
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  ### Installatin Command
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@@ -101,13 +101,11 @@ Following EDA tools can accept the generated source files.
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  * Xilinx Vivado Simulator
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  * Verilator
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  * Need `-Wno-fatal` switch
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- * Need to define `RGGEN_NAIVE_MUX_IMPLEMENTATION` macro
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  * Icarus Verilog
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  * Verilog RTL only
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  * Synthesis tools
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  * Synopsys Design Compiler
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  * Intel Quartus
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- * Need to define `RGGEN_NAIVE_MUX_IMPLEMENTATION` macro
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  * Xilinx Vivado
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  * [Yosys](http://www.clifford.at/yosys/)
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  * Verilog RTL
@@ -135,7 +133,9 @@ Then, generated files listed below will be written to `out` directory.
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  * SystemVerilog RTL
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  * https://github.com/rggen/rggen-sample/blob/master/block_0.sv
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+ * https://github.com/rggen/rggen-sample/blob/master/block_0_rtl_pkg.sv
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  * https://github.com/rggen/rggen-sample/blob/master/block_1.sv
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+ * https://github.com/rggen/rggen-sample/blob/master/block_1_rtl_pkg.sv
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  * UVM register model
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  * https://github.com/rggen/rggen-sample/blob/master/block_0_ral_pkg.sv
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  * https://github.com/rggen/rggen-sample/blob/master/block_1_ral_pkg.sv
@@ -174,7 +174,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
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  ## Copyright & License
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- Copyright © 2019-2022 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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+ Copyright © 2019-2023 Taichi Ishitani. RgGen is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher detils.
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  ## Code of Conduct
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data/lib/rggen/version.rb CHANGED
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  # frozen_string_literal: true
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  module RgGen
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- VERSION = '0.28.0'
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+ VERSION = '0.29.0'
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  end
metadata CHANGED
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  --- !ruby/object:Gem::Specification
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  name: rggen
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  version: !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  platform: ruby
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  authors:
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  - Taichi Ishitani
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  autorequire:
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  bindir: bin
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  cert_chain: []
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- date: 2022-10-10 00:00:00.000000000 Z
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+ date: 2023-01-02 00:00:00.000000000 Z
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  dependencies:
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  - !ruby/object:Gem::Dependency
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  name: rggen-c-header
@@ -16,84 +16,84 @@ dependencies:
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.2.0
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+ version: 0.3.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.2.0
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+ version: 0.3.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-core
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-default-register-map
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-markdown
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.24.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.24.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-spreadsheet-loader
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.24.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.23.0
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+ version: 0.24.0
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  - !ruby/object:Gem::Dependency
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  name: rggen-systemverilog
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  requirement: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  type: :runtime
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  prerelease: false
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  version_requirements: !ruby/object:Gem::Requirement
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  requirements:
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  - - "~>"
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  - !ruby/object:Gem::Version
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- version: 0.28.0
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+ version: 0.29.0
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  - !ruby/object:Gem::Dependency
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  name: bundler
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  requirement: !ruby/object:Gem::Requirement
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  version: '0'
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  description: |
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  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
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- It will automatically generate soruce code related to configuration and status registers (CSR),
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+ It will automatically generate source code related to configuration and status registers (CSR),
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  e.g. SytemVerilog RTL, UVM RAL model, C header file, Wiki documents, from human readable register map specifications.
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  email:
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  - rggen@googlegroups.com
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  requirements:
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  - - ">="
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  - !ruby/object:Gem::Version
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- version: '2.6'
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+ version: '2.7'
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  required_rubygems_version: !ruby/object:Gem::Requirement
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  requirements:
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  - - ">="
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  - !ruby/object:Gem::Version
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  version: '0'
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  requirements: []
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- rubygems_version: 3.3.7
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+ rubygems_version: 3.4.1
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  signing_key:
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  specification_version: 4
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  summary: Code generation tool for configuration and status registers