rggen 0.26.0 → 0.26.1

checksums.yaml

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data/README.md

@@ -11,17 +11,22 @@
 
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL), Wiki documents, from human readable register map specifications.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to configuration and status registers (CSR), e.g. SytemVerilog RTL, UVM register model (UVM RAL/uvm_reg), Wiki documents, from human readable register map specifications.
 
 RgGen has following features:
 
 * Generate source files related to CSR from register map specifications
-    * SystemVerilog RTL
-    * Verilog RTL
-        * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
-    * VHDL RTL
-        * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
-    * UVM register model (UVM RAL)
+    * RTL module
+        * SystemVerilog
+        * Verilog
+            * Need [rggen-verilog](https://github.com/rggen/rggen-verilog) plugin
+        * VHDL
+            * Need [rggen-vhdl](https://github.com/rggen/rggen-vhdl) plugin
+        * Supports standard bus protocols
+            * AMBA APB
+            * AMBA AXI4-Lite
+            * Wishbone
+    * UVM register model (UVM RAL/uvm_reg)
     * Register map documents written in Markdown
 * Register map specifications can be written in human readable format
     * Ruby with APIs to describe register map information
@@ -92,8 +97,6 @@ Following EDA tools can accept the generated source files.
     * Synopsys VCS
     * Cadence Xcelium
     * Xilinx Vivado Simulator
-        * Confirmed RTL only
-        * Not sure if UVM register models are accepted
     * Verilator
         * Need `-Wno-fatal` switch
     * Icarus Verilog

data/lib/rggen/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module RgGen
-  VERSION = '0.26.0'
+  VERSION = '0.26.1'
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.26.0
+  version: 0.26.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-03-25 00:00:00.000000000 Z
+date: 2022-06-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-core
@@ -72,14 +72,14 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.26.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.26.1
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement