rggen 0.11.0 → 0.12.0

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data/README.md CHANGED
@@ -7,14 +7,14 @@
7
7
 
8
8
  # RgGen
9
9
 
10
- RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map specifications.
10
+ RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
11
11
 
12
12
  RgGen has following features:
13
13
 
14
14
  * Generate source files related to CSR from register map specifications
15
- * Source files listed below will be generated:
16
- * SystemVerilog RTL
17
- * UVM RAL model
15
+ * SystemVerilog RTL
16
+ * UVM RAL model
17
+ * Register map documents written in Markdown
18
18
  * Register map specifications can be written in human readable format
19
19
  * Supported formats are listed below:
20
20
  * Ruby with APIs to describe register map information
@@ -1,6 +1,7 @@
1
1
  # frozen_string_literal: true
2
2
 
3
3
  require 'rggen/systemverilog'
4
+ require 'rggen/markdown'
4
5
  require_relative 'built_in/version'
5
6
 
6
7
  module RgGen
@@ -11,12 +12,14 @@ module RgGen
11
12
  'built_in/global/bus_width',
12
13
  'built_in/global/fold_sv_interface_port',
13
14
  'built_in/register_block/byte_size',
15
+ 'built_in/register_block/markdown',
14
16
  'built_in/register_block/name',
15
17
  'built_in/register_block/protocol',
16
18
  'built_in/register_block/protocol/apb',
17
19
  'built_in/register_block/protocol/axi4lite',
18
20
  'built_in/register_block/sv_ral_package',
19
21
  'built_in/register_block/sv_rtl_top',
22
+ 'built_in/register/markdown',
20
23
  'built_in/register/name',
21
24
  'built_in/register/offset_address',
22
25
  'built_in/register/size',
@@ -54,6 +54,12 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
54
54
  message { 'overlap with existing bit field(s)' }
55
55
  end
56
56
 
57
+ printable(:bit_assignments) do
58
+ Array.new(@sequence_size || 1) do |i|
59
+ width > 1 && "[#{msb(i)}:#{lsb(i)}]" || "[#{lsb(i)}]"
60
+ end
61
+ end
62
+
57
63
  private
58
64
 
59
65
  KEYS = [:lsb, :width, :sequence_size, :step].freeze
@@ -12,5 +12,7 @@ RgGen.define_simple_feature(:bit_field, :comment) do
12
12
  value.to_s
13
13
  end
14
14
  end
15
+
16
+ printable :comment
15
17
  end
16
18
  end
@@ -15,7 +15,7 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
15
15
  end
16
16
 
17
17
  verify(:component) do
18
- error_condition { option[:require] && !initial_value? }
18
+ error_condition { settings[:require] && !initial_value? }
19
19
  message { 'no initial value is given' }
20
20
  end
21
21
 
@@ -44,11 +44,19 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
44
44
  end
45
45
  end
46
46
 
47
+ printable(:initial_value) do
48
+ @initial_value &&
49
+ begin
50
+ print_width = (bit_field.width + 3) / 4
51
+ format('0x%0*x', print_width, @initial_value)
52
+ end
53
+ end
54
+
47
55
  private
48
56
 
49
- def option
50
- @option ||=
51
- (bit_field.options && bit_field.options[:initial_value]) || {}
57
+ def settings
58
+ @settings ||=
59
+ (bit_field.settings && bit_field.settings[:initial_value]) || {}
52
60
  end
53
61
 
54
62
  def min_initial_value
@@ -60,8 +68,8 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
60
68
  end
61
69
 
62
70
  def match_valid_condition?
63
- !option.key?(:valid_condition) ||
64
- instance_exec(@initial_value, &option[:valid_condition])
71
+ !settings.key?(:valid_condition) ||
72
+ instance_exec(@initial_value, &settings[:valid_condition])
65
73
  end
66
74
  end
67
75
  end
@@ -26,6 +26,8 @@ RgGen.define_simple_feature(:bit_field, :name) do
26
26
  message { "duplicated bit field name: #{name}" }
27
27
  end
28
28
 
29
+ printable :name
30
+
29
31
  private
30
32
 
31
33
  def get_full_name(separator = '.')
@@ -86,17 +86,17 @@ RgGen.define_simple_feature(:bit_field, :reference) do
86
86
 
87
87
  private
88
88
 
89
- def option
90
- @option ||=
91
- (bit_field.options && bit_field.options[:reference]) || {}
89
+ def settings
90
+ @settings ||=
91
+ (bit_field.settings && bit_field.settings[:reference]) || {}
92
92
  end
93
93
 
94
94
  def use_reference?
95
- option.fetch(:use, false)
95
+ settings.fetch(:use, false)
96
96
  end
97
97
 
98
98
  def require_reference?
99
- use_reference? && option[:require]
99
+ use_reference? && settings[:require]
100
100
  end
101
101
 
102
102
  def no_reference?
@@ -129,7 +129,7 @@ RgGen.define_simple_feature(:bit_field, :reference) do
129
129
  end
130
130
 
131
131
  def required_width
132
- option[:width] || bit_field.width
132
+ settings[:width] || bit_field.width
133
133
  end
134
134
 
135
135
  def match_width?
@@ -46,16 +46,16 @@ RgGen.define_list_feature(:bit_field, :type) do
46
46
 
47
47
  attr_reader :volatility
48
48
 
49
- def options
50
- @options ||= {}
49
+ def settings
50
+ @settings ||= {}
51
51
  end
52
52
 
53
- def initial_value(**option)
54
- options[:initial_value] = option
53
+ def initial_value(**setting)
54
+ settings[:initial_value] = setting
55
55
  end
56
56
 
57
- def reference(**option)
58
- options[:reference] = option
57
+ def reference(**setting)
58
+ settings[:reference] = setting
59
59
  end
60
60
  end
61
61
 
@@ -66,10 +66,12 @@ RgGen.define_list_feature(:bit_field, :type) do
66
66
  property :write_only?, body: -> { writable? && !readable? }
67
67
  property :reserved?, body: -> { !(readable? || writable?) }
68
68
  property :volatile?, forward_to: :volatility
69
- property :options, forward_to_helper: true
69
+ property :settings, forward_to_helper: true
70
70
 
71
71
  build { |value| @type = value }
72
72
 
73
+ printable :type
74
+
73
75
  private
74
76
 
75
77
  def volatility
@@ -22,6 +22,8 @@ RgGen.define_simple_feature(:global, :address_width) do
22
22
  end
23
23
  end
24
24
 
25
+ printable :address_width
26
+
25
27
  private
26
28
 
27
29
  def min_address_width
@@ -24,6 +24,8 @@ RgGen.define_simple_feature(:global, :bus_width) do
24
24
  message { "input bus width is not power of 2: #{bus_width}" }
25
25
  end
26
26
 
27
+ printable :bus_width
28
+
27
29
  private
28
30
 
29
31
  def power_of_2?(value)
@@ -0,0 +1,11 @@
1
+
2
+ ### <%= anchor(anchor_id) %><%= register.name %>
3
+
4
+ <% register.printables.each do |name, printable| %>
5
+ * <%= name %>
6
+ * <%= printable || 'NA' %>
7
+ <% end %>
8
+ <% if register.bit_fields? %>
9
+
10
+ <%= bit_field_table %>
11
+ <% end%>
@@ -0,0 +1,26 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_simple_feature(:register, :markdown) do
4
+ markdown do
5
+ export def anchor_id
6
+ [register_block.anchor_id, register.name].join('-')
7
+ end
8
+
9
+ main_code :markdown, from_template: true
10
+
11
+ private
12
+
13
+ def bit_field_table
14
+ column_names = bit_field_printables.first.keys
15
+ rows =
16
+ bit_field_printables
17
+ .map(&:values)
18
+ .map { |row| row.map { |cell| Array(cell).join("\n") } }
19
+ table(column_names, rows)
20
+ end
21
+
22
+ def bit_field_printables
23
+ @bit_field_printables ||= register.bit_fields.map(&:printables)
24
+ end
25
+ end
26
+ end
@@ -25,6 +25,8 @@ RgGen.define_simple_feature(:register, :name) do
25
25
  message { "duplicated register name: #{name}" }
26
26
  end
27
27
 
28
+ printable :name
29
+
28
30
  private
29
31
 
30
32
  def duplicated_name?
@@ -55,6 +55,11 @@ RgGen.define_simple_feature(:register, :offset_address) do
55
55
  end
56
56
  end
57
57
 
58
+ printable(:offset_address) do
59
+ [start_address, end_address]
60
+ .map(&method(:printable_address)).join(' - ')
61
+ end
62
+
58
63
  private
59
64
 
60
65
  def bus_width
@@ -89,8 +94,13 @@ RgGen.define_simple_feature(:register, :offset_address) do
89
94
  end
90
95
 
91
96
  def support_unique_range_only?(other_register)
92
- !(register.support_overlapped_address? &&
97
+ !(register.settings[:support_overlapped_address] &&
93
98
  register.match_type?(other_register))
94
99
  end
100
+
101
+ def printable_address(address)
102
+ print_width = (register_block.local_address_width + 3) / 4
103
+ format('0x%0*x', print_width, address)
104
+ end
95
105
  end
96
106
  end
@@ -3,6 +3,12 @@
3
3
  RgGen.define_simple_feature(:register, :size) do
4
4
  register_map do
5
5
  property :size
6
+ property :width, body: -> { @width ||= calc_width }
7
+ property :byte_width, body: -> { width / 8 }
8
+ property :byte_size, body: -> { @byte_size ||= calc_byte_size }
9
+ property :array?, forward_to: :array_register?
10
+ property :array_size, forward_to: :array_registers
11
+ property :count, body: -> { @count ||= calc_count }
6
12
 
7
13
  input_pattern [
8
14
  /(#{integer}(:?,#{integer})*)/,
@@ -20,6 +26,10 @@ RgGen.define_simple_feature(:register, :size) do
20
26
  end
21
27
  end
22
28
 
29
+ printable(:array_size) do
30
+ (array_register? || nil) && "[#{array_registers.join(', ')}]"
31
+ end
32
+
23
33
  private
24
34
 
25
35
  def parse_values(values)
@@ -45,5 +55,41 @@ RgGen.define_simple_feature(:register, :size) do
45
55
  rescue ArgumentError, TypeError
46
56
  error "cannot convert #{value.inspect} into register size"
47
57
  end
58
+
59
+ def calc_width
60
+ bus_width = configuration.bus_width
61
+ if register.bit_fields.empty?
62
+ bus_width
63
+ else
64
+ ((max_msb + bus_width) / bus_width) * bus_width
65
+ end
66
+ end
67
+
68
+ def max_msb
69
+ register
70
+ .bit_fields
71
+ .map { |bit_field| bit_field.msb((bit_field.sequence_size || 1) - 1) }
72
+ .max
73
+ end
74
+
75
+ def calc_byte_size
76
+ if register.settings[:byte_size]
77
+ instance_exec(&register.settings[:byte_size])
78
+ else
79
+ Array(@size).reduce(1, :*) * byte_width
80
+ end
81
+ end
82
+
83
+ def array_register?
84
+ register.settings[:support_array] && !@size.nil? || false
85
+ end
86
+
87
+ def array_registers
88
+ array_register? && @size || nil
89
+ end
90
+
91
+ def calc_count
92
+ Array(array_registers).reduce(1, :*)
93
+ end
48
94
  end
49
95
  end
@@ -23,39 +23,28 @@ RgGen.define_list_feature(:register, :type) do
23
23
  !@no_bit_fields
24
24
  end
25
25
 
26
- def support_array_register
27
- @support_array_register = true
26
+ def settings
27
+ @settings ||= {}
28
28
  end
29
29
 
30
- def support_array_register?
31
- @support_array_register || false
30
+ def support_array_register
31
+ settings[:support_array] = true
32
32
  end
33
33
 
34
34
  def byte_size(&block)
35
- @byte_size = block if block_given?
36
- @byte_size
35
+ settings[:byte_size] = block
37
36
  end
38
37
 
39
38
  def support_overlapped_address
40
- @support_overlapped_address = true
41
- end
42
-
43
- def support_overlapped_address?
44
- @support_overlapped_address || false
39
+ settings[:support_overlapped_address] = true
45
40
  end
46
41
  end
47
42
 
48
43
  property :type, body: -> { @type || :default }
44
+ property :match_type?, body: ->(register) { register.type == type }
49
45
  property :writable?, forward_to: :writability
50
46
  property :readable?, forward_to: :readability
51
- property :width, body: -> { @width ||= calc_width }
52
- property :byte_width, body: -> { @byte_width ||= width / 8 }
53
- property :array?, forward_to: :array_register?
54
- property :array_size, body: -> { (array? && register.size) || nil }
55
- property :count, body: -> { @count ||= calc_count }
56
- property :byte_size, body: -> { @byte_size ||= calc_byte_size }
57
- property :match_type?, body: ->(register) { register.type == type }
58
- property :support_overlapped_address?, forward_to_helper: true
47
+ property :settings, forward_to_helper: true
59
48
 
60
49
  build do |value|
61
50
  @type = value[:type]
@@ -100,37 +89,6 @@ RgGen.define_list_feature(:register, :type) do
100
89
  register.bit_fields.any?(&block)
101
90
  end
102
91
  end
103
-
104
- def calc_width
105
- bus_width = configuration.bus_width
106
- if helper.need_bit_fields?
107
- ((collect_msb.max + bus_width) / bus_width) * bus_width
108
- else
109
- bus_width
110
- end
111
- end
112
-
113
- def collect_msb
114
- register.bit_fields.collect do |bit_field|
115
- bit_field.msb((bit_field.sequence_size || 1) - 1)
116
- end
117
- end
118
-
119
- def array_register?
120
- helper.support_array_register? && !register.size.nil?
121
- end
122
-
123
- def calc_count
124
- Array(array_size).reduce(1, :*)
125
- end
126
-
127
- def calc_byte_size
128
- if helper.byte_size
129
- instance_exec(&helper.byte_size)
130
- else
131
- Array(register.size).reduce(1, :*) * byte_width
132
- end
133
- end
134
92
  end
135
93
 
136
94
  default_feature do
@@ -42,6 +42,8 @@ RgGen.define_simple_feature(:register_block, :byte_size) do
42
42
  end
43
43
  end
44
44
 
45
+ printable :byte_size
46
+
45
47
  private
46
48
 
47
49
  def max_byte_size
@@ -0,0 +1,8 @@
1
+ ## <%= register_block.name %>
2
+
3
+ <% register_block.printables.each do |name, printable| %>
4
+ * <%= name %>
5
+ * <%= printable || 'NA' %>
6
+ <% end %>
7
+
8
+ <%= register_table %>
@@ -0,0 +1,36 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_simple_feature(:register_block, :markdown) do
4
+ markdown do
5
+ export def anchor_id
6
+ register_block.name
7
+ end
8
+
9
+ write_file '<%= register_block.name %>.md' do |file|
10
+ file.body do |code|
11
+ register_block.generate_code(:markdown, :top_down, code)
12
+ end
13
+ end
14
+
15
+ main_code :markdown, from_template: true
16
+
17
+ private
18
+
19
+ def register_table
20
+ table([:name, :offset_address], table_rows)
21
+ end
22
+
23
+ def table_rows
24
+ register_block.registers
25
+ .zip(register_block.registers.map(&:printables))
26
+ .map { |register, printables| table_row(register, printables) }
27
+ end
28
+
29
+ def table_row(register, printables)
30
+ [
31
+ anchor_link(printables[:name], register.anchor_id),
32
+ printables[:offset_address]
33
+ ]
34
+ end
35
+ end
36
+ end
@@ -25,6 +25,8 @@ RgGen.define_simple_feature(:register_block, :name) do
25
25
  message { "duplicated register block name: #{name}" }
26
26
  end
27
27
 
28
+ printable :name
29
+
28
30
  private
29
31
 
30
32
  def duplicated_name?
@@ -22,6 +22,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
22
22
  base_feature do
23
23
  property :protocol
24
24
  build { |protocol| @protocol = protocol }
25
+ printable :protocol
25
26
  end
26
27
 
27
28
  default_feature do
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module BuiltIn
5
- VERSION = '0.11.0'
5
+ VERSION = '0.12.0'
6
6
  end
7
7
  end
@@ -25,3 +25,6 @@ RgGen.enable :register, [:sv_rtl_top]
25
25
  RgGen.enable :bit_field, [:sv_rtl_top]
26
26
 
27
27
  RgGen.enable :register_block, [:sv_ral_package]
28
+
29
+ RgGen.enable :register_block, [:markdown]
30
+ RgGen.enable :register, [:markdown]
@@ -0,0 +1,155 @@
1
+ ## block_0
2
+
3
+ * name
4
+ * block_0
5
+ * byte_size
6
+ * 256
7
+
8
+ |name|offset_address|
9
+ |:--|:--|
10
+ |[register_0](#block_0-register_0)|0x00 - 0x03|
11
+ |[register_1](#block_0-register_1)|0x04 - 0x07|
12
+ |[register_2](#block_0-register_2)|0x04 - 0x07|
13
+ |[register_3](#block_0-register_3)|0x08 - 0x0b|
14
+ |[register_4](#block_0-register_4)|0x0c - 0x0f|
15
+ |[register_5](#block_0-register_5)|0x10 - 0x13|
16
+ |[register_6](#block_0-register_6)|0x20 - 0x3f|
17
+ |[register_7](#block_0-register_7)|0x40 - 0x47|
18
+ |[register_8](#block_0-register_8)|0x80 - 0xff|
19
+
20
+ ### <div id="block_0-register_0"></div>register_0
21
+
22
+ * name
23
+ * register_0
24
+ * offset_address
25
+ * 0x00 - 0x03
26
+ * array_size
27
+ * NA
28
+
29
+ |name|bit_assignments|type|initial_value|comment|
30
+ |:--|:--|:--|:--|:--|
31
+ |bit_field_0|[3:0]|rw|0x0||
32
+ |bit_field_1|[7:4]|rw|0x0||
33
+ |bit_field_2|[8]|rw|0x0||
34
+
35
+ ### <div id="block_0-register_1"></div>register_1
36
+
37
+ * name
38
+ * register_1
39
+ * offset_address
40
+ * 0x04 - 0x07
41
+ * array_size
42
+ * NA
43
+
44
+ |name|bit_assignments|type|initial_value|comment|
45
+ |:--|:--|:--|:--|:--|
46
+ |bit_field_0|[3:0]|ro|||
47
+ |bit_field_1|[11:8]|ro|||
48
+ |bit_field_2|[23:16]|rof|0xab||
49
+ |bit_field_3|[31:24]|reserved|||
50
+
51
+ ### <div id="block_0-register_2"></div>register_2
52
+
53
+ * name
54
+ * register_2
55
+ * offset_address
56
+ * 0x04 - 0x07
57
+ * array_size
58
+ * NA
59
+
60
+ |name|bit_assignments|type|initial_value|comment|
61
+ |:--|:--|:--|:--|:--|
62
+ |bit_field_0|[3:0]|wo|0x0||
63
+ |bit_field_1|[11:8]|w0trg|||
64
+ |bit_field_2|[19:16]|w1trg|||
65
+
66
+ ### <div id="block_0-register_3"></div>register_3
67
+
68
+ * name
69
+ * register_3
70
+ * offset_address
71
+ * 0x08 - 0x0b
72
+ * array_size
73
+ * NA
74
+
75
+ |name|bit_assignments|type|initial_value|comment|
76
+ |:--|:--|:--|:--|:--|
77
+ |bit_field_0|[3:0]|rc|0x0||
78
+ |bit_field_1|[11:8]|rc|0x0||
79
+ |bit_field_2|[15:12]|ro|||
80
+ |bit_field_3|[19:16]|rs|0x0||
81
+
82
+ ### <div id="block_0-register_4"></div>register_4
83
+
84
+ * name
85
+ * register_4
86
+ * offset_address
87
+ * 0x0c - 0x0f
88
+ * array_size
89
+ * NA
90
+
91
+ |name|bit_assignments|type|initial_value|comment|
92
+ |:--|:--|:--|:--|:--|
93
+ |bit_field_0|[3:0]|rwc|0x0||
94
+ |bit_field_1|[7:4]|rwc|0x0||
95
+ |bit_field_2|[11:8]|rwe|0x0||
96
+ |bit_field_3|[15:12]|rwe|0x0||
97
+ |bit_field_4|[19:16]|rwl|0x0||
98
+ |bit_field_5|[23:20]|rwl|0x0||
99
+
100
+ ### <div id="block_0-register_5"></div>register_5
101
+
102
+ * name
103
+ * register_5
104
+ * offset_address
105
+ * 0x10 - 0x13
106
+ * array_size
107
+ * NA
108
+
109
+ |name|bit_assignments|type|initial_value|comment|
110
+ |:--|:--|:--|:--|:--|
111
+ |bit_field_0|[3:0]|w0c|0x0||
112
+ |bit_field_1|[7:4]|w0c|0x0||
113
+ |bit_field_2|[11:8]|ro|||
114
+ |bit_field_3|[15:12]|w1c|0x0||
115
+ |bit_field_4|[19:16]|w1c|0x0||
116
+ |bit_field_5|[23:20]|ro|||
117
+ |bit_field_6|[27:24]|w0s|0x0||
118
+ |bit_field_7|[31:28]|w1s|0x0||
119
+
120
+ ### <div id="block_0-register_6"></div>register_6
121
+
122
+ * name
123
+ * register_6
124
+ * offset_address
125
+ * 0x20 - 0x3f
126
+ * array_size
127
+ * [4]
128
+
129
+ |name|bit_assignments|type|initial_value|comment|
130
+ |:--|:--|:--|:--|:--|
131
+ |bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
132
+ |bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
133
+
134
+ ### <div id="block_0-register_7"></div>register_7
135
+
136
+ * name
137
+ * register_7
138
+ * offset_address
139
+ * 0x40 - 0x47
140
+ * array_size
141
+ * [2, 4]
142
+
143
+ |name|bit_assignments|type|initial_value|comment|
144
+ |:--|:--|:--|:--|:--|
145
+ |bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
146
+ |bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
147
+
148
+ ### <div id="block_0-register_8"></div>register_8
149
+
150
+ * name
151
+ * register_8
152
+ * offset_address
153
+ * 0x80 - 0xff
154
+ * array_size
155
+ * NA
@@ -0,0 +1,39 @@
1
+ ## block_1
2
+
3
+ * name
4
+ * block_1
5
+ * byte_size
6
+ * 128
7
+
8
+ |name|offset_address|
9
+ |:--|:--|
10
+ |[register_0](#block_1-register_0)|0x00 - 0x3f|
11
+ |[register_1](#block_1-register_1)|0x40 - 0x7f|
12
+
13
+ ### <div id="block_1-register_0"></div>register_0
14
+
15
+ * name
16
+ * register_0
17
+ * offset_address
18
+ * 0x00 - 0x3f
19
+ * array_size
20
+ * [2, 4]
21
+
22
+ |name|bit_assignments|type|initial_value|comment|
23
+ |:--|:--|:--|:--|:--|
24
+ |bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
25
+ |bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|ro|||
26
+
27
+ ### <div id="block_1-register_1"></div>register_1
28
+
29
+ * name
30
+ * register_1
31
+ * offset_address
32
+ * 0x40 - 0x7f
33
+ * array_size
34
+ * [2, 4]
35
+
36
+ |name|bit_assignments|type|initial_value|comment|
37
+ |:--|:--|:--|:--|:--|
38
+ |bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|ro|||
39
+ |bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.11.0
4
+ version: 0.12.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2019-08-11 00:00:00.000000000 Z
11
+ date: 2019-08-19 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-core
@@ -16,14 +16,28 @@ dependencies:
16
16
  requirements:
17
17
  - - "~>"
18
18
  - !ruby/object:Gem::Version
19
- version: '0.11'
19
+ version: '0.12'
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - "~>"
25
25
  - !ruby/object:Gem::Version
26
- version: '0.11'
26
+ version: '0.12'
27
+ - !ruby/object:Gem::Dependency
28
+ name: rggen-markdown
29
+ requirement: !ruby/object:Gem::Requirement
30
+ requirements:
31
+ - - "~>"
32
+ - !ruby/object:Gem::Version
33
+ version: '0.12'
34
+ type: :runtime
35
+ prerelease: false
36
+ version_requirements: !ruby/object:Gem::Requirement
37
+ requirements:
38
+ - - "~>"
39
+ - !ruby/object:Gem::Version
40
+ version: '0.12'
27
41
  - !ruby/object:Gem::Dependency
28
42
  name: rggen-spreadsheet-loader
29
43
  requirement: !ruby/object:Gem::Requirement
@@ -68,8 +82,8 @@ dependencies:
68
82
  version: '0'
69
83
  description: |
70
84
  RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
71
- It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
72
- from human readable register map specifications.
85
+ It will automatically generate soruce code related to control/status registers (CSR),
86
+ e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
73
87
  email:
74
88
  - rggen@googlegroups.com
75
89
  executables: []
@@ -108,6 +122,8 @@ files:
108
122
  - lib/rggen/built_in/global/array_port_format.rb
109
123
  - lib/rggen/built_in/global/bus_width.rb
110
124
  - lib/rggen/built_in/global/fold_sv_interface_port.rb
125
+ - lib/rggen/built_in/register/markdown.erb
126
+ - lib/rggen/built_in/register/markdown.rb
111
127
  - lib/rggen/built_in/register/name.rb
112
128
  - lib/rggen/built_in/register/offset_address.rb
113
129
  - lib/rggen/built_in/register/size.rb
@@ -121,6 +137,8 @@ files:
121
137
  - lib/rggen/built_in/register/type/indirect_sv_ral.erb
122
138
  - lib/rggen/built_in/register/type/indirect_sv_rtl.erb
123
139
  - lib/rggen/built_in/register_block/byte_size.rb
140
+ - lib/rggen/built_in/register_block/markdown.erb
141
+ - lib/rggen/built_in/register_block/markdown.rb
124
142
  - lib/rggen/built_in/register_block/name.rb
125
143
  - lib/rggen/built_in/register_block/protocol.rb
126
144
  - lib/rggen/built_in/register_block/protocol/apb.erb
@@ -135,11 +153,13 @@ files:
135
153
  - lib/rggen/default_setup_file.rb
136
154
  - lib/rggen/setup/default.rb
137
155
  - lib/rggen/version.rb
156
+ - sample/block_0.md
138
157
  - sample/block_0.rb
139
158
  - sample/block_0.sv
140
159
  - sample/block_0.xlsx
141
160
  - sample/block_0.yml
142
161
  - sample/block_0_ral_pkg.sv
162
+ - sample/block_1.md
143
163
  - sample/block_1.rb
144
164
  - sample/block_1.sv
145
165
  - sample/block_1.xlsx