rggen 0.11.0 → 0.12.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -7,14 +7,14 @@
 
 # RgGen
 
-RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, from human readable register map specifications.
+RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers. It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
 
 RgGen has following features:
 
 * Generate source files related to CSR from register map specifications
-    * Source files listed below will be generated:
-        * SystemVerilog RTL
-        * UVM RAL model
+    * SystemVerilog RTL
+    * UVM RAL model
+    * Register map documents written in Markdown
 * Register map specifications can be written in human readable format
     * Supported formats are listed below:
         * Ruby with APIs to describe register map information

data/lib/rggen/built_in.rb

@@ -1,6 +1,7 @@
 # frozen_string_literal: true
 
 require 'rggen/systemverilog'
+require 'rggen/markdown'
 require_relative 'built_in/version'
 
 module RgGen
@@ -11,12 +12,14 @@ module RgGen
       'built_in/global/bus_width',
       'built_in/global/fold_sv_interface_port',
       'built_in/register_block/byte_size',
+      'built_in/register_block/markdown',
       'built_in/register_block/name',
       'built_in/register_block/protocol',
       'built_in/register_block/protocol/apb',
       'built_in/register_block/protocol/axi4lite',
       'built_in/register_block/sv_ral_package',
       'built_in/register_block/sv_rtl_top',
+      'built_in/register/markdown',
       'built_in/register/name',
       'built_in/register/offset_address',
       'built_in/register/size',

data/lib/rggen/built_in/bit_field/bit_assignment.rb

@@ -54,6 +54,12 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
       message { 'overlap with existing bit field(s)' }
     end
 
+    printable(:bit_assignments) do
+      Array.new(@sequence_size || 1) do |i|
+        width > 1 && "[#{msb(i)}:#{lsb(i)}]" || "[#{lsb(i)}]"
+      end
+    end
+
     private
 
     KEYS = [:lsb, :width, :sequence_size, :step].freeze

data/lib/rggen/built_in/bit_field/comment.rb

@@ -12,5 +12,7 @@ RgGen.define_simple_feature(:bit_field, :comment) do
           value.to_s
         end
     end
+
+    printable :comment
   end
 end

data/lib/rggen/built_in/bit_field/initial_value.rb

@@ -15,7 +15,7 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
     end
 
     verify(:component) do
-      error_condition { option[:require] && !initial_value? }
+      error_condition { settings[:require] && !initial_value? }
       message { 'no initial value is given' }
     end
 
@@ -44,11 +44,19 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
       end
     end
 
+    printable(:initial_value) do
+      @initial_value &&
+        begin
+          print_width = (bit_field.width + 3) / 4
+          format('0x%0*x', print_width, @initial_value)
+        end
+    end
+
     private
 
-    def option
-      @option ||=
-        (bit_field.options && bit_field.options[:initial_value]) || {}
+    def settings
+      @settings ||=
+        (bit_field.settings && bit_field.settings[:initial_value]) || {}
     end
 
     def min_initial_value
@@ -60,8 +68,8 @@ RgGen.define_simple_feature(:bit_field, :initial_value) do
     end
 
     def match_valid_condition?
-      !option.key?(:valid_condition) ||
-        instance_exec(@initial_value, &option[:valid_condition])
+      !settings.key?(:valid_condition) ||
+        instance_exec(@initial_value, &settings[:valid_condition])
     end
   end
 end

data/lib/rggen/built_in/bit_field/name.rb

@@ -26,6 +26,8 @@ RgGen.define_simple_feature(:bit_field, :name) do
       message { "duplicated bit field name: #{name}" }
     end
 
+    printable :name
+
     private
 
     def get_full_name(separator = '.')

data/lib/rggen/built_in/bit_field/reference.rb

@@ -86,17 +86,17 @@ RgGen.define_simple_feature(:bit_field, :reference) do
 
     private
 
-    def option
-      @option ||=
-        (bit_field.options && bit_field.options[:reference]) || {}
+    def settings
+      @settings ||=
+        (bit_field.settings && bit_field.settings[:reference]) || {}
     end
 
     def use_reference?
-      option.fetch(:use, false)
+      settings.fetch(:use, false)
     end
 
     def require_reference?
-      use_reference? && option[:require]
+      use_reference? && settings[:require]
     end
 
     def no_reference?
@@ -129,7 +129,7 @@ RgGen.define_simple_feature(:bit_field, :reference) do
     end
 
     def required_width
-      option[:width] || bit_field.width
+      settings[:width] || bit_field.width
     end
 
     def match_width?

data/lib/rggen/built_in/bit_field/type.rb

@@ -46,16 +46,16 @@ RgGen.define_list_feature(:bit_field, :type) do
 
         attr_reader :volatility
 
-        def options
-          @options ||= {}
+        def settings
+          @settings ||= {}
         end
 
-        def initial_value(**option)
-          options[:initial_value] = option
+        def initial_value(**setting)
+          settings[:initial_value] = setting
         end
 
-        def reference(**option)
-          options[:reference] = option
+        def reference(**setting)
+          settings[:reference] = setting
         end
       end
 
@@ -66,10 +66,12 @@ RgGen.define_list_feature(:bit_field, :type) do
       property :write_only?, body: -> { writable? && !readable? }
       property :reserved?, body: -> { !(readable? || writable?) }
       property :volatile?, forward_to: :volatility
-      property :options, forward_to_helper: true
+      property :settings, forward_to_helper: true
 
       build { |value| @type = value }
 
+      printable :type
+
       private
 
       def volatility

data/lib/rggen/built_in/global/address_width.rb

@@ -22,6 +22,8 @@ RgGen.define_simple_feature(:global, :address_width) do
       end
     end
 
+    printable :address_width
+
     private
 
     def min_address_width

data/lib/rggen/built_in/global/bus_width.rb

@@ -24,6 +24,8 @@ RgGen.define_simple_feature(:global, :bus_width) do
       message { "input bus width is not power of 2: #{bus_width}" }
     end
 
+    printable :bus_width
+
     private
 
     def power_of_2?(value)

data/lib/rggen/built_in/register/markdown.erb

@@ -0,0 +1,11 @@
+
+### <%= anchor(anchor_id) %><%= register.name %>
+
+<% register.printables.each do |name, printable| %>
+* <%= name %>
+    * <%= printable || 'NA' %>
+<% end %>
+<% if register.bit_fields? %>
+
+<%= bit_field_table %>
+<% end%>

data/lib/rggen/built_in/register/markdown.rb

@@ -0,0 +1,26 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register, :markdown) do
+  markdown do
+    export def anchor_id
+      [register_block.anchor_id, register.name].join('-')
+    end
+
+    main_code :markdown, from_template: true
+
+    private
+
+    def bit_field_table
+      column_names = bit_field_printables.first.keys
+      rows =
+        bit_field_printables
+          .map(&:values)
+          .map { |row| row.map { |cell| Array(cell).join("\n") } }
+      table(column_names, rows)
+    end
+
+    def bit_field_printables
+      @bit_field_printables ||= register.bit_fields.map(&:printables)
+    end
+  end
+end

data/lib/rggen/built_in/register/name.rb

@@ -25,6 +25,8 @@ RgGen.define_simple_feature(:register, :name) do
       message { "duplicated register name: #{name}" }
     end
 
+    printable :name
+
     private
 
     def duplicated_name?

data/lib/rggen/built_in/register/offset_address.rb

@@ -55,6 +55,11 @@ RgGen.define_simple_feature(:register, :offset_address) do
       end
     end
 
+    printable(:offset_address) do
+      [start_address, end_address]
+        .map(&method(:printable_address)).join(' - ')
+    end
+
     private
 
     def bus_width
@@ -89,8 +94,13 @@ RgGen.define_simple_feature(:register, :offset_address) do
     end
 
     def support_unique_range_only?(other_register)
-      !(register.support_overlapped_address? &&
+      !(register.settings[:support_overlapped_address] &&
         register.match_type?(other_register))
     end
+
+    def printable_address(address)
+      print_width = (register_block.local_address_width + 3) / 4
+      format('0x%0*x', print_width, address)
+    end
   end
 end

data/lib/rggen/built_in/register/size.rb

@@ -3,6 +3,12 @@
 RgGen.define_simple_feature(:register, :size) do
   register_map do
     property :size
+    property :width, body: -> { @width ||= calc_width }
+    property :byte_width, body: -> { width / 8 }
+    property :byte_size, body: -> { @byte_size ||= calc_byte_size }
+    property :array?, forward_to: :array_register?
+    property :array_size, forward_to: :array_registers
+    property :count, body: -> { @count ||= calc_count }
 
     input_pattern [
       /(#{integer}(:?,#{integer})*)/,
@@ -20,6 +26,10 @@ RgGen.define_simple_feature(:register, :size) do
       end
     end
 
+    printable(:array_size) do
+      (array_register? || nil) && "[#{array_registers.join(', ')}]"
+    end
+
     private
 
     def parse_values(values)
@@ -45,5 +55,41 @@ RgGen.define_simple_feature(:register, :size) do
     rescue ArgumentError, TypeError
       error "cannot convert #{value.inspect} into register size"
     end
+
+    def calc_width
+      bus_width = configuration.bus_width
+      if register.bit_fields.empty?
+        bus_width
+      else
+        ((max_msb + bus_width) / bus_width) * bus_width
+      end
+    end
+
+    def max_msb
+      register
+        .bit_fields
+        .map { |bit_field| bit_field.msb((bit_field.sequence_size || 1) - 1) }
+        .max
+    end
+
+    def calc_byte_size
+      if register.settings[:byte_size]
+        instance_exec(&register.settings[:byte_size])
+      else
+        Array(@size).reduce(1, :*) * byte_width
+      end
+    end
+
+    def array_register?
+      register.settings[:support_array] && !@size.nil? || false
+    end
+
+    def array_registers
+      array_register? && @size || nil
+    end
+
+    def calc_count
+      Array(array_registers).reduce(1, :*)
+    end
   end
 end

data/lib/rggen/built_in/register/type.rb

@@ -23,39 +23,28 @@ RgGen.define_list_feature(:register, :type) do
           !@no_bit_fields
         end
 
-        def support_array_register
-          @support_array_register = true
+        def settings
+          @settings ||= {}
         end
 
-        def support_array_register?
-          @support_array_register || false
+        def support_array_register
+          settings[:support_array] = true
         end
 
         def byte_size(&block)
-          @byte_size = block if block_given?
-          @byte_size
+          settings[:byte_size] = block
         end
 
         def support_overlapped_address
-          @support_overlapped_address = true
-        end
-
-        def support_overlapped_address?
-          @support_overlapped_address || false
+          settings[:support_overlapped_address] = true
         end
       end
 
       property :type, body: -> { @type || :default }
+      property :match_type?, body: ->(register) { register.type == type }
       property :writable?, forward_to: :writability
       property :readable?, forward_to: :readability
-      property :width, body: -> { @width ||= calc_width }
-      property :byte_width, body: -> { @byte_width ||= width / 8 }
-      property :array?, forward_to: :array_register?
-      property :array_size, body: -> { (array? && register.size) || nil }
-      property :count, body: -> { @count ||= calc_count }
-      property :byte_size, body: -> { @byte_size ||= calc_byte_size }
-      property :match_type?, body: ->(register) { register.type == type }
-      property :support_overlapped_address?, forward_to_helper: true
+      property :settings, forward_to_helper: true
 
       build do |value|
         @type = value[:type]
@@ -100,37 +89,6 @@ RgGen.define_list_feature(:register, :type) do
           register.bit_fields.any?(&block)
         end
       end
-
-      def calc_width
-        bus_width = configuration.bus_width
-        if helper.need_bit_fields?
-          ((collect_msb.max + bus_width) / bus_width) * bus_width
-        else
-          bus_width
-        end
-      end
-
-      def collect_msb
-        register.bit_fields.collect do |bit_field|
-          bit_field.msb((bit_field.sequence_size || 1) - 1)
-        end
-      end
-
-      def array_register?
-        helper.support_array_register? && !register.size.nil?
-      end
-
-      def calc_count
-        Array(array_size).reduce(1, :*)
-      end
-
-      def calc_byte_size
-        if helper.byte_size
-          instance_exec(&helper.byte_size)
-        else
-          Array(register.size).reduce(1, :*) * byte_width
-        end
-      end
     end
 
     default_feature do

data/lib/rggen/built_in/register_block/byte_size.rb

@@ -42,6 +42,8 @@ RgGen.define_simple_feature(:register_block, :byte_size) do
       end
     end
 
+    printable :byte_size
+
     private
 
     def max_byte_size

data/lib/rggen/built_in/register_block/markdown.erb

@@ -0,0 +1,8 @@
+## <%= register_block.name %>
+
+<% register_block.printables.each do |name, printable| %>
+* <%= name %>
+    * <%= printable || 'NA' %>
+<% end %>
+
+<%= register_table %>

data/lib/rggen/built_in/register_block/markdown.rb

@@ -0,0 +1,36 @@
+# frozen_string_literal: true
+
+RgGen.define_simple_feature(:register_block, :markdown) do
+  markdown do
+    export def anchor_id
+      register_block.name
+    end
+
+    write_file '<%= register_block.name %>.md' do |file|
+      file.body do |code|
+        register_block.generate_code(:markdown, :top_down, code)
+      end
+    end
+
+    main_code :markdown, from_template: true
+
+    private
+
+    def register_table
+      table([:name, :offset_address], table_rows)
+    end
+
+    def table_rows
+      register_block.registers
+        .zip(register_block.registers.map(&:printables))
+        .map { |register, printables| table_row(register, printables) }
+    end
+
+    def table_row(register, printables)
+      [
+        anchor_link(printables[:name], register.anchor_id),
+        printables[:offset_address]
+      ]
+    end
+  end
+end

data/lib/rggen/built_in/register_block/name.rb

@@ -25,6 +25,8 @@ RgGen.define_simple_feature(:register_block, :name) do
       message { "duplicated register block name: #{name}" }
     end
 
+    printable :name
+
     private
 
     def duplicated_name?

data/lib/rggen/built_in/register_block/protocol.rb

@@ -22,6 +22,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
     base_feature do
       property :protocol
       build { |protocol| @protocol = protocol }
+      printable :protocol
     end
 
     default_feature do

data/lib/rggen/built_in/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module BuiltIn
-    VERSION = '0.11.0'
+    VERSION = '0.12.0'
   end
 end

data/lib/rggen/setup/default.rb

@@ -25,3 +25,6 @@ RgGen.enable :register, [:sv_rtl_top]
 RgGen.enable :bit_field, [:sv_rtl_top]
 
 RgGen.enable :register_block, [:sv_ral_package]
+
+RgGen.enable :register_block, [:markdown]
+RgGen.enable :register, [:markdown]

data/sample/block_0.md

@@ -0,0 +1,155 @@
+## block_0
+
+* name
+    * block_0
+* byte_size
+    * 256
+
+|name|offset_address|
+|:--|:--|
+|[register_0](#block_0-register_0)|0x00 - 0x03|
+|[register_1](#block_0-register_1)|0x04 - 0x07|
+|[register_2](#block_0-register_2)|0x04 - 0x07|
+|[register_3](#block_0-register_3)|0x08 - 0x0b|
+|[register_4](#block_0-register_4)|0x0c - 0x0f|
+|[register_5](#block_0-register_5)|0x10 - 0x13|
+|[register_6](#block_0-register_6)|0x20 - 0x3f|
+|[register_7](#block_0-register_7)|0x40 - 0x47|
+|[register_8](#block_0-register_8)|0x80 - 0xff|
+
+### <div id="block_0-register_0"></div>register_0
+
+* name
+    * register_0
+* offset_address
+    * 0x00 - 0x03
+* array_size
+    * NA
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[3:0]|rw|0x0||
+|bit_field_1|[7:4]|rw|0x0||
+|bit_field_2|[8]|rw|0x0||
+
+### <div id="block_0-register_1"></div>register_1
+
+* name
+    * register_1
+* offset_address
+    * 0x04 - 0x07
+* array_size
+    * NA
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[3:0]|ro|||
+|bit_field_1|[11:8]|ro|||
+|bit_field_2|[23:16]|rof|0xab||
+|bit_field_3|[31:24]|reserved|||
+
+### <div id="block_0-register_2"></div>register_2
+
+* name
+    * register_2
+* offset_address
+    * 0x04 - 0x07
+* array_size
+    * NA
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[3:0]|wo|0x0||
+|bit_field_1|[11:8]|w0trg|||
+|bit_field_2|[19:16]|w1trg|||
+
+### <div id="block_0-register_3"></div>register_3
+
+* name
+    * register_3
+* offset_address
+    * 0x08 - 0x0b
+* array_size
+    * NA
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[3:0]|rc|0x0||
+|bit_field_1|[11:8]|rc|0x0||
+|bit_field_2|[15:12]|ro|||
+|bit_field_3|[19:16]|rs|0x0||
+
+### <div id="block_0-register_4"></div>register_4
+
+* name
+    * register_4
+* offset_address
+    * 0x0c - 0x0f
+* array_size
+    * NA
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[3:0]|rwc|0x0||
+|bit_field_1|[7:4]|rwc|0x0||
+|bit_field_2|[11:8]|rwe|0x0||
+|bit_field_3|[15:12]|rwe|0x0||
+|bit_field_4|[19:16]|rwl|0x0||
+|bit_field_5|[23:20]|rwl|0x0||
+
+### <div id="block_0-register_5"></div>register_5
+
+* name
+    * register_5
+* offset_address
+    * 0x10 - 0x13
+* array_size
+    * NA
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[3:0]|w0c|0x0||
+|bit_field_1|[7:4]|w0c|0x0||
+|bit_field_2|[11:8]|ro|||
+|bit_field_3|[15:12]|w1c|0x0||
+|bit_field_4|[19:16]|w1c|0x0||
+|bit_field_5|[23:20]|ro|||
+|bit_field_6|[27:24]|w0s|0x0||
+|bit_field_7|[31:28]|w1s|0x0||
+
+### <div id="block_0-register_6"></div>register_6
+
+* name
+    * register_6
+* offset_address
+    * 0x20 - 0x3f
+* array_size
+    * [4]
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
+|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
+
+### <div id="block_0-register_7"></div>register_7
+
+* name
+    * register_7
+* offset_address
+    * 0x40 - 0x47
+* array_size
+    * [2, 4]
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
+|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||
+
+### <div id="block_0-register_8"></div>register_8
+
+* name
+    * register_8
+* offset_address
+    * 0x80 - 0xff
+* array_size
+    * NA

data/sample/block_1.md

@@ -0,0 +1,39 @@
+## block_1
+
+* name
+    * block_1
+* byte_size
+    * 128
+
+|name|offset_address|
+|:--|:--|
+|[register_0](#block_1-register_0)|0x00 - 0x3f|
+|[register_1](#block_1-register_1)|0x40 - 0x7f|
+
+### <div id="block_1-register_0"></div>register_0
+
+* name
+    * register_0
+* offset_address
+    * 0x00 - 0x3f
+* array_size
+    * [2, 4]
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|rw|0x00||
+|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|ro|||
+
+### <div id="block_1-register_1"></div>register_1
+
+* name
+    * register_1
+* offset_address
+    * 0x40 - 0x7f
+* array_size
+    * [2, 4]
+
+|name|bit_assignments|type|initial_value|comment|
+|:--|:--|:--|:--|:--|
+|bit_field_0|[7:0]<br>[23:16]<br>[39:32]<br>[55:48]|ro|||
+|bit_field_1|[15:8]<br>[31:24]<br>[47:40]<br>[63:56]|rw|0x00||

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen
 version: !ruby/object:Gem::Version
-  version: 0.11.0
+  version: 0.12.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-08-11 00:00:00.000000000 Z
+date: 2019-08-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-core
@@ -16,14 +16,28 @@ dependencies:
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: '0.11'
+        version: '0.12'
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - "~>"
       - !ruby/object:Gem::Version
-        version: '0.11'
+        version: '0.12'
+- !ruby/object:Gem::Dependency
+  name: rggen-markdown
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '0.12'
+  type: :runtime
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '0.12'
 - !ruby/object:Gem::Dependency
   name: rggen-spreadsheet-loader
   requirement: !ruby/object:Gem::Requirement
@@ -68,8 +82,8 @@ dependencies:
         version: '0'
 description: |
   RgGen is a code generation tool for ASIC/IP/FPGA/RTL engineers.
-  It will automatically generate soruce code related to control/status registers (CSR), e.g. SytemVerilog RTL, UVM RAL model,
-  from human readable register map specifications.
+  It will automatically generate soruce code related to control/status registers (CSR),
+  e.g. SytemVerilog RTL, UVM RAL model, Wiki documents, from human readable register map specifications.
 email:
 - rggen@googlegroups.com
 executables: []
@@ -108,6 +122,8 @@ files:
 - lib/rggen/built_in/global/array_port_format.rb
 - lib/rggen/built_in/global/bus_width.rb
 - lib/rggen/built_in/global/fold_sv_interface_port.rb
+- lib/rggen/built_in/register/markdown.erb
+- lib/rggen/built_in/register/markdown.rb
 - lib/rggen/built_in/register/name.rb
 - lib/rggen/built_in/register/offset_address.rb
 - lib/rggen/built_in/register/size.rb
@@ -121,6 +137,8 @@ files:
 - lib/rggen/built_in/register/type/indirect_sv_ral.erb
 - lib/rggen/built_in/register/type/indirect_sv_rtl.erb
 - lib/rggen/built_in/register_block/byte_size.rb
+- lib/rggen/built_in/register_block/markdown.erb
+- lib/rggen/built_in/register_block/markdown.rb
 - lib/rggen/built_in/register_block/name.rb
 - lib/rggen/built_in/register_block/protocol.rb
 - lib/rggen/built_in/register_block/protocol/apb.erb
@@ -135,11 +153,13 @@ files:
 - lib/rggen/default_setup_file.rb
 - lib/rggen/setup/default.rb
 - lib/rggen/version.rb
+- sample/block_0.md
 - sample/block_0.rb
 - sample/block_0.sv
 - sample/block_0.xlsx
 - sample/block_0.yml
 - sample/block_0_ral_pkg.sv
+- sample/block_1.md
 - sample/block_1.rb
 - sample/block_1.sv
 - sample/block_1.xlsx