rggen-vhdl 0.12.2 → 0.13.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 9cbf295168e68bf08a95ae234b15414b88ab0a68eba9d8be6bfee4a494d19a11
-  data.tar.gz: 23bd05f96bfe6f930389c11d776280f319bcc70521f659ef793b0843de051618
+  metadata.gz: aab2a582042ff67cb8a436badd9c9e45db892433943289caa549e72137afeb7d
+  data.tar.gz: 6d1a70927e02f01554d047824fcbf49111900371f438be44ae3b0e618f2bfd20
 SHA512:
-  metadata.gz: 04d94c6cc7a8e951efeda5bb16a2a75373fddd440bc3fe072b5f14096a903992d986eaf951859ffa1ebd079e3f034db186840daaa1940b649ddc5cdd4efae028
-  data.tar.gz: cb6a3e9eb6b96f5867fd4b9ea37ce2ac0740be9b0dc6c0117a42a61eae4e6b2e27f686264f44847782791016151d2bd13ca9809bf1ba191862834bfdf96f3230
+  metadata.gz: 43e9a26277a6a23701e5d7aeeccaa8842f331feb2bbe56fc70023b9139416bda3d26ed6a1310c8b24e00a75089c1df5eef139073ca0c4dd9c5174f4deed4bb1e
+  data.tar.gz: 0041704e5f8fb7c8124006ec529db4f63b93ff534f06e47f3662b3ed92d674feb04ca25d541b5f651f0dc12f3ebe17dca2d296178d9ea8d7416136fcfbef2d1b

data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2021-2025 Taichi Ishitani
+Copyright (c) 2021-2026 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -2,7 +2,7 @@
 [![CI](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml/badge.svg)](https://github.com/rggen/rggen-vhdl/actions/workflows/ci.yml)
 [![Maintainability](https://qlty.sh/badges/d3e167e0-16f0-4170-ae4a-10ccc3dcdcb5/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-vhdl)
 [![codecov](https://codecov.io/gh/rggen/rggen-vhdl/branch/master/graph/badge.svg?token=cyo9R4xCje)](https://codecov.io/gh/rggen/rggen-vhdl)
-[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
+[![Discord](https://img.shields.io/discord/1406572699467124806?style=flat&logo=discord)](https://discord.com/invite/KWya83ZZxr)
 
 # RgGen::VHDL
 
@@ -62,13 +62,13 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
 * [GitHub Discussions](https://github.com/rggen/rggen/discussions)
-* [Chat Room](https://gitter.im/rggen/rggen)
+* [Discord](https://discord.com/invite/KWya83ZZxr)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
 
 ## Copyright & License
 
-Copyright © 2021-2025 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2021-2026 Taichi Ishitani. RgGen::VHDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/vhdl/bit_field/type/counter.erb

@@ -0,0 +1,23 @@
+u_bit_field: entity <%= library_name %>.rggen_bit_field_counter
+  generic map (
+    WIDTH         => <%= width %>,
+    INITIAL_VALUE => <%= initial_value %>,
+    UP_WIDTH      => <%= up_width %>,
+    DOWN_WIDTH    => <%= down_width %>,
+    WRAP_AROUND   => <%= wrap_around %>,
+    USE_CLEAR     => <%= use_clear_value %>
+  )
+  port map (
+    i_clk             => <%= clock %>,
+    i_rst_n           => <%= reset %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
+    i_sw_mask         => <%= bit_field_mask %>,
+    i_sw_write_data   => <%= bit_field_write_data %>,
+    o_sw_read_data    => <%= bit_field_read_data %>,
+    o_sw_value        => <%= bit_field_value %>,
+    i_clear           => <%= clear_signal %>,
+    i_up              => <%= up[loop_variables] %>,
+    i_down            => <%= down[loop_variables] %>,
+    o_count           => <%= count[loop_variables] %>
+  );

data/lib/rggen/vhdl/bit_field/type/counter.rb

@@ -0,0 +1,55 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :counter) do
+  vhdl do
+    build do
+      generic :up_width, {
+        name: "#{full_name}_up_width".upcase, type: :natural, default: 1
+      }
+      generic :down_width, {
+        name: "#{full_name}_down_width".upcase, type: :natural, default: 1
+      }
+      generic :wrap_around, {
+        name: "#{full_name}_wrap_around".upcase, type: :boolean, default: false
+      }
+      if external_clear?
+        generic :use_clear, {
+          name: "#{full_name}_use_clear".upcase, type: :boolean, default: true
+        }
+      end
+
+      input :up, {
+        name: "i_#{full_name}_up",
+        width: "clip_width(#{up_width})", array_size:
+      }
+      input :down, {
+        name: "i_#{full_name}_down",
+        width: "clip_width(#{down_width})", array_size:
+      }
+      if external_clear?
+        input :clear, {
+          name: "i_#{full_name}_clear", width: 1, array_size:
+        }
+      end
+      output :count, {
+        name: "o_#{full_name}", width:, array_size:
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_clear?
+      !bit_field.reference?
+    end
+
+    def use_clear_value
+      !external_clear? || use_clear
+    end
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/vhdl/register/type/maskable.erb

@@ -0,0 +1,29 @@
+u_register: entity <%= library_name %>.rggen_maskable_register
+  generic map (
+    READABLE        => <%= readable? %>,
+    WRITABLE        => <%= writable? %>,
+    ADDRESS_WIDTH   => <%= address_width %>,
+    OFFSET_ADDRESS  => <%= offset_address %>,
+    BUS_WIDTH       => <%= bus_width %>,
+    DATA_WIDTH      => <%= width %>
+  )
+  port map (
+    i_clk                   => <%= clock %>,
+    i_rst_n                 => <%= reset %>,
+    i_register_valid        => <%= register_valid %>,
+    i_register_access       => <%= register_access %>,
+    i_register_address      => <%= register_address %>,
+    i_register_write_data   => <%= register_write_data %>,
+    i_register_strobe       => <%= register_strobe %>,
+    o_register_active       => <%= register_active %>,
+    o_register_ready        => <%= register_ready %>,
+    o_register_status       => <%= register_status %>,
+    o_register_read_data    => <%= register_read_data %>,
+    o_register_value        => <%= register_value %>,
+    o_bit_field_read_valid  => <%= bit_field_read_valid %>,
+    o_bit_field_write_valid => <%= bit_field_write_valid %>,
+    o_bit_field_mask        => <%= bit_field_mask %>,
+    o_bit_field_write_data  => <%= bit_field_write_data %>,
+    i_bit_field_read_data   => <%= bit_field_read_data %>,
+    i_bit_field_value       => <%= bit_field_value %>
+  );

data/lib/rggen/vhdl/register/type/maskable.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :maskable) do
+  vhdl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/vhdl/register_block/protocol/axi4lite.rb

@@ -36,7 +36,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
     private
 
     def id_width_value
-      "clip_id_width(#{id_width})"
+      "clip_width(#{id_width})"
     end
   end
 end

data/lib/rggen/vhdl/utility/identifier.rb

@@ -24,13 +24,11 @@ module RgGen
         end
 
         def __array_slice__(lsb, width)
-          msb =
-            if integer?(width)
-              __reduce_array__([lsb, width - 1], :+, 0)
-            else
-              __reduce_array__([lsb, width, -1], :+, 0)
-            end
-          "(#{msb} downto #{lsb})"
+          if integer?(width)
+            "(#{__reduce_array__([lsb, width - 1], :+, 0)} downto #{lsb})"
+          else
+            "(#{__reduce_array__([lsb, width], :+, 0)}-1 downto #{lsb})"
+          end
         end
       end
     end

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.12.2'
+    VERSION = '0.13.0'
   end
 end

data/lib/rggen/vhdl.rb

@@ -35,9 +35,11 @@ RgGen.setup_plugin :'rggen-vhdl' do |plugin|
     'vhdl/register/type',
     'vhdl/register/type/external',
     'vhdl/register/type/indirect',
+    'vhdl/register/type/maskable',
     'vhdl/register/type/rw',
     'vhdl/bit_field/vhdl_top',
     'vhdl/bit_field/type',
+    'vhdl/bit_field/type/counter',
     'vhdl/bit_field/type/custom',
     'vhdl/bit_field/type/rc_w0c_w1c_wc_woc',
     'vhdl/bit_field/type/ro_rotrg',

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.12.2
+  version: 0.13.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-07-21 00:00:00.000000000 Z
+date: 1980-01-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.1
+        version: 0.36.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.1
+        version: 0.36.0
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -35,6 +35,8 @@ files:
 - README.md
 - lib/rggen/vhdl.rb
 - lib/rggen/vhdl/bit_field/type.rb
+- lib/rggen/vhdl/bit_field/type/counter.erb
+- lib/rggen/vhdl/bit_field/type/counter.rb
 - lib/rggen/vhdl/bit_field/type/custom.erb
 - lib/rggen/vhdl/bit_field/type/custom.rb
 - lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb
@@ -83,6 +85,8 @@ files:
 - lib/rggen/vhdl/register/type/external.rb
 - lib/rggen/vhdl/register/type/indirect.erb
 - lib/rggen/vhdl/register/type/indirect.rb
+- lib/rggen/vhdl/register/type/maskable.erb
+- lib/rggen/vhdl/register/type/maskable.rb
 - lib/rggen/vhdl/register/type/rw.erb
 - lib/rggen/vhdl/register/type/rw.rb
 - lib/rggen/vhdl/register/vhdl_top.rb
@@ -123,14 +127,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.1'
+      version: '3.2'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.6.2
+rubygems_version: 4.0.3
 specification_version: 4
-summary: rggen-vhdl-0.12.2
+summary: rggen-vhdl-0.13.0
 test_files: []