rggen-vhdl 0.12.1 → 0.12.2

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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+  metadata.gz: 9cbf295168e68bf08a95ae234b15414b88ab0a68eba9d8be6bfee4a494d19a11
+  data.tar.gz: 23bd05f96bfe6f930389c11d776280f319bcc70521f659ef793b0843de051618
 SHA512:
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+  data.tar.gz: cb6a3e9eb6b96f5867fd4b9ea37ce2ac0740be9b0dc6c0117a42a61eae4e6b2e27f686264f44847782791016151d2bd13ca9809bf1ba191862834bfdf96f3230

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -6,7 +6,7 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
     SW_WRITE_ACTION => <%= write_action %>,
     HW_SET          => true,
     HW_SET_WIDTH    => <%= width %>,
-    EXTERNAL_MASK   => <%= external_mask %>
+    EXTERNAL_MASK   => <%= external_mask? %>
   )
   port map (
     i_clk             => <%= clock %>,

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -40,7 +40,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
       }[bit_field.type]
     end
 
-    def external_mask
+    def external_mask?
       bit_field.reference?
     end
 

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.erb

@@ -2,7 +2,7 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,
-    SW_WRITE_ONCE   => <%= write_once %>,
+    SW_WRITE_ONCE   => <%= write_once? %>,
     TRIGGER         => <%= rwtrg? %>
   )
   port map (

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.rb

@@ -24,7 +24,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
       bit_field.type == :rwtrg
     end
 
-    def write_once
+    def write_once?
       bit_field.type == :w1
     end
 

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb

@@ -3,7 +3,7 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,
     SW_READ_ACTION  => RGGEN_READ_NONE,
-    SW_WRITE_ONCE   => <%= write_once %>,
+    SW_WRITE_ONCE   => <%= write_once? %>,
     TRIGGER         => <%= wotrg? %>
   )
   port map (

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.rb

@@ -21,7 +21,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
       bit_field.type == :wotrg
     end
 
-    def write_once
+    def write_once?
       bit_field.type == :wo1
     end
 

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.12.1'
+    VERSION = '0.12.2'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.12.1
+  version: 0.12.2
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-06-01 00:00:00.000000000 Z
+date: 2025-07-21 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -132,5 +132,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-vhdl-0.12.1
+summary: rggen-vhdl-0.12.2
 test_files: []