rggen-vhdl 0.12.0 → 0.12.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 25e25403b17fc5e0b6e5e496d2b0f8ddd2f98bac26a309b9c1e92b5c13a3e24c
+  metadata.gz: b431faf18b53b2ae46ff78f94358b09c1b6c9544092f2d7d22efbec5ea2625b2
+  data.tar.gz: 33c3011c7ca2f86456410d138a661a6ff4c680fda67aafd23a119e1613b6b792
 SHA512:
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+  data.tar.gz: 25b2b95de7d3dd5aa05baa34b04dce80668f9cc8c442caeb59693144f8833b992acd61f704a4cb98693c9ffe50c4174a076c21e3674ff10abffb671bc6e534df

data/lib/rggen/vhdl/bit_field/type/custom.erb

@@ -5,7 +5,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
     SW_READ_ACTION      => <%= sw_read_action %>,
     SW_WRITE_ACTION     => <%= sw_write_action %>,
     SW_WRITE_ONCE       => <%= bit_field.sw_write_once? %>,
+    HW_WRITE            => <%= bit_field.hw_write? %>,
+    HW_SET              => <%= bit_field.hw_set? %>,
     HW_SET_WIDTH        => <%= width %>,
+    HW_CLEAR            => <%= bit_field.hw_clear? %>,
     HW_CLEAR_WIDTH      => <%= width %>,
     STORAGE             => <%= storage? %>,
     EXTERNAL_READ_DATA  => <%= external_read_data? %>,
@@ -14,10 +17,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -4,15 +4,17 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
     INITIAL_VALUE   => <%= initial_value %>,
     SW_READ_ACTION  => <%= read_action %>,
     SW_WRITE_ACTION => <%= write_action %>,
-    HW_SET_WIDTH    => <%= width %>
+    HW_SET          => true,
+    HW_SET_WIDTH    => <%= width %>,
+    EXTERNAL_MASK   => <%= external_mask %>
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
-    i_sw_write_enable => <%= write_enable %>,
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
+    i_sw_write_enable => "1",
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -40,8 +40,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
       }[bit_field.type]
     end
 
-    def write_enable
-      bit_field.writable? && bin(1, 1) || bin(0, 1)
+    def external_mask
+      bit_field.reference?
     end
 
     def value_out_unmasked

data/lib/rggen/vhdl/bit_field/type/ro_rotrg.erb

@@ -8,10 +8,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "0",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rof.erb

@@ -7,10 +7,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => '0',
     i_rst_n           => '0',
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "0",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rohw.erb

@@ -2,15 +2,16 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,
-    SW_WRITE_ACTION => RGGEN_WRITE_NONE
+    SW_WRITE_ACTION => RGGEN_WRITE_NONE,
+    HW_WRITE        => true
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/row0trg_row1trg.erb

@@ -6,10 +6,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field_w01trg
   port map (
     i_clk             => i_clk,
     i_rst_n           => i_rst_n,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rowo_rowotrg.erb

@@ -8,10 +8,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -4,15 +4,16 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
     INITIAL_VALUE   => <%= initial_value %>,
     SW_READ_ACTION  => <%= read_action %>,
     SW_WRITE_ACTION => <%= write_action %>,
+    HW_CLEAR        => true,
     HW_CLEAR_WIDTH  => <%= width %>
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
-    i_sw_write_enable => <%= write_enable %>,
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
+    i_sw_write_enable => "1",
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -34,9 +34,5 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
         wos: 'RGGEN_WRITE_SET'
       }[bit_field.type]
     end
-
-    def write_enable
-      bit_field.writable? && bin(1, 1) || bin(0, 1)
-    end
   end
 end

data/lib/rggen/vhdl/bit_field/type/rw_rwtrg_w1.erb

@@ -8,10 +8,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rwc.erb

@@ -2,15 +2,16 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH           => <%= width %>,
     INITIAL_VALUE   => <%= initial_value %>,
+    HW_CLEAR        => true,
     HW_CLEAR_WIDTH  => 1
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rwe_rwl.erb

@@ -2,15 +2,16 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH                     => <%= width %>,
     INITIAL_VALUE             => <%= initial_value %>,
+    SW_WRITE_CONTROL          => true,
     SW_WRITE_ENABLE_POLARITY  => <%= control_signal_polarity %>
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => <%= control_signal %>,
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rwhw.erb

@@ -1,15 +1,16 @@
 u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH         => <%= width %>,
-    INITIAL_VALUE => <%= initial_value %>
+    INITIAL_VALUE => <%= initial_value %>,
+    HW_WRITE      => true
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/rws.erb

@@ -2,15 +2,16 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   generic map (
     WIDTH         => <%= width %>,
     INITIAL_VALUE => <%= initial_value %>,
+    HW_SET        => true,
     HW_SET_WIDTH  => 1
   )
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -8,10 +8,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/w0t_w1t.erb

@@ -7,10 +7,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/w0trg_w1trg.erb

@@ -6,10 +6,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field_w01trg
   port map (
     i_clk             => i_clk,
     i_rst_n           => i_rst_n,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/wo_wo1_wotrg.erb

@@ -9,10 +9,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type/wrc_wrs.erb

@@ -7,10 +7,10 @@ u_bit_field: entity <%= library_name %>.rggen_bit_field
   port map (
     i_clk             => <%= clock %>,
     i_rst_n           => <%= reset %>,
-    i_sw_valid        => <%= bit_field_valid %>,
-    i_sw_read_mask    => <%= bit_field_read_mask %>,
+    i_sw_read_valid   => <%= bit_field_read_valid %>,
+    i_sw_write_valid  => <%= bit_field_write_valid %>,
     i_sw_write_enable => "1",
-    i_sw_write_mask   => <%= bit_field_write_mask %>,
+    i_sw_mask         => <%= bit_field_mask %>,
     i_sw_write_data   => <%= bit_field_write_data %>,
     o_sw_read_data    => <%= bit_field_read_data %>,
     o_sw_value        => <%= bit_field_value %>,

data/lib/rggen/vhdl/bit_field/type.rb

@@ -38,16 +38,16 @@ RgGen.define_list_feature(:bit_field, :type) do
         register_block.reset
       end
 
-      def bit_field_valid
-        register.bit_field_valid
+      def bit_field_read_valid
+        register.bit_field_read_valid
       end
 
-      def bit_field_read_mask
-        register.bit_field_read_mask[lsb, width]
+      def bit_field_write_valid
+        register.bit_field_write_valid
       end
 
-      def bit_field_write_mask
-        register.bit_field_write_mask[lsb, width]
+      def bit_field_mask
+        register.bit_field_mask[lsb, width]
       end
 
       def bit_field_write_data

data/lib/rggen/vhdl/register/type/default.erb

@@ -20,9 +20,9 @@ u_register: entity <%= library_name %>.rggen_default_register
     o_register_status       => <%= register_status %>,
     o_register_read_data    => <%= register_read_data %>,
     o_register_value        => <%= register_value %>,
-    o_bit_field_valid       => <%= bit_field_valid %>,
-    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
-    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_read_valid  => <%= bit_field_read_valid %>,
+    o_bit_field_write_valid => <%= bit_field_write_valid %>,
+    o_bit_field_mask        => <%= bit_field_mask %>,
     o_bit_field_write_data  => <%= bit_field_write_data %>,
     i_bit_field_read_data   => <%= bit_field_read_data %>,
     i_bit_field_value       => <%= bit_field_value %>

data/lib/rggen/vhdl/register/type/indirect.erb

@@ -22,9 +22,9 @@ u_register: entity <%= library_name %>.rggen_indirect_register
     o_register_read_data    => <%= register_read_data %>,
     o_register_value        => <%= register_value %>,
     i_indirect_match        => <%= indirect_match %>,
-    o_bit_field_valid       => <%= bit_field_valid %>,
-    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
-    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_read_valid  => <%= bit_field_read_valid %>,
+    o_bit_field_write_valid => <%= bit_field_write_valid %>,
+    o_bit_field_mask        => <%= bit_field_mask %>,
     o_bit_field_write_data  => <%= bit_field_write_data %>,
     i_bit_field_read_data   => <%= bit_field_read_data %>,
     i_bit_field_value       => <%= bit_field_value %>

data/lib/rggen/vhdl/register/type/rw.erb

@@ -20,9 +20,9 @@ u_register: entity <%= library_name %>.rggen_default_register
     o_register_status       => <%= register_status %>,
     o_register_read_data    => <%= register_read_data %>,
     o_register_value        => <%= register_value %>,
-    o_bit_field_valid       => <%= bit_field_valid %>,
-    o_bit_field_read_mask   => <%= bit_field_read_mask %>,
-    o_bit_field_write_mask  => <%= bit_field_write_mask %>,
+    o_bit_field_read_valid  => <%= bit_field_read_valid %>,
+    o_bit_field_write_valid => <%= bit_field_write_valid %>,
+    o_bit_field_mask        => <%= bit_field_mask %>,
     o_bit_field_write_data  => <%= bit_field_write_data %>,
     i_bit_field_read_data   => <%= bit_field_read_data %>,
     i_bit_field_value       => <%= bit_field_value %>

data/lib/rggen/vhdl/register/type.rb

@@ -72,16 +72,16 @@ RgGen.define_list_feature(:register, :type) do
         register_block.register_value[[register.index], 0, width]
       end
 
-      def bit_field_valid
-        register.bit_field_valid
+      def bit_field_read_valid
+        register.bit_field_read_valid
       end
 
-      def bit_field_read_mask
-        register.bit_field_read_mask
+      def bit_field_write_valid
+        register.bit_field_write_valid
       end
 
-      def bit_field_write_mask
-        register.bit_field_write_mask
+      def bit_field_mask
+        register.bit_field_mask
       end
 
       def bit_field_write_data

data/lib/rggen/vhdl/register/vhdl_top.rb

@@ -6,9 +6,9 @@ RgGen.define_simple_feature(:register, :vhdl_top) do
 
     build do
       unless register.bit_fields.empty?
-        signal :bit_field_valid
-        signal :bit_field_read_mask, width: register.width
-        signal :bit_field_write_mask, width: register.width
+        signal :bit_field_read_valid
+        signal :bit_field_write_valid
+        signal :bit_field_mask, width: register.width
         signal :bit_field_write_data, width: register.width
         signal :bit_field_read_data, width: register.width
         signal :bit_field_value, width: register.width

data/lib/rggen/vhdl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module VHDL
-    VERSION = '0.12.0'
+    VERSION = '0.12.1'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-vhdl
 version: !ruby/object:Gem::Version
-  version: 0.12.0
+  version: 0.12.1
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-02-19 00:00:00.000000000 Z
+date: 2025-06-01 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.35.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.0
+        version: 0.35.1
 description: VHDL writer plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -132,5 +132,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-vhdl-0.12.0
+summary: rggen-vhdl-0.12.1
 test_files: []