rggen-vhdl 0.10.0 → 0.10.1

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@@ -1,6 +1,3 @@
1
- <% index_fields_and_values.each_with_index do |(field, value), i| %>
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- <%= indirect_match[i] %> <= '1' when unsigned(<%= field %>) = <%= value %> else '0';
3
- <% end %>
4
1
  u_register: entity <%= library_name %>.rggen_indirect_register
5
2
  generic map (
6
3
  READABLE => <%= readable? %>,
@@ -9,7 +6,7 @@ u_register: entity <%= library_name %>.rggen_indirect_register
9
6
  OFFSET_ADDRESS => <%= offset_address %>,
10
7
  BUS_WIDTH => <%= bus_width %>,
11
8
  DATA_WIDTH => <%= width %>,
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- INDIRECT_MATCH_WIDTH => <%= match_width %>
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+ INDIRECT_MATCH_WIDTH => <%= index_match_width %>
13
10
  )
14
11
  port map (
15
12
  i_clk => <%= clock %>,
@@ -2,33 +2,33 @@
2
2
 
3
3
  RgGen.define_list_item_feature(:register, :type, :indirect) do
4
4
  vhdl do
5
+ include RgGen::SystemVerilog::RTL::IndirectIndex
6
+
5
7
  build do
6
- signal :indirect_match, { width: match_width }
8
+ signal :indirect_match, { width: index_match_width }
7
9
  end
8
10
 
9
- main_code :register, from_template: true
11
+ main_code :register do |code|
12
+ indirect_index_matches(code)
13
+ code << process_template
14
+ end
10
15
 
11
16
  private
12
17
 
13
- def match_width
14
- register.index_entries.size
18
+ def array_index_value(value, _width)
19
+ value
15
20
  end
16
21
 
17
- def index_fields
18
- register
19
- .collect_index_fields(register_block.bit_fields)
20
- .map(&:value)
22
+ def fixed_index_value(value, _width)
23
+ value
21
24
  end
22
25
 
23
- def index_values
24
- loop_variables = register.local_loop_variables
25
- register.index_entries.map do |entry|
26
- entry.array_index? && loop_variables.shift || entry.value
27
- end
26
+ def index_match_rhs(index)
27
+ indirect_match[index]
28
28
  end
29
29
 
30
- def index_fields_and_values
31
- index_fields.zip(index_values)
30
+ def index_match_lhs(field, value)
31
+ "'1' when unsigned(#{field}) = #{value} else '0'"
32
32
  end
33
33
  end
34
34
  end
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module VHDL
5
- VERSION = '0.10.0'
5
+ VERSION = '0.10.1'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-vhdl
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.10.0
4
+ version: 0.10.1
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2024-02-28 00:00:00.000000000 Z
11
+ date: 2024-11-28 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
16
16
  requirements:
17
17
  - - ">="
18
18
  - !ruby/object:Gem::Version
19
- version: 0.33.0
19
+ version: 0.33.1
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - ">="
25
25
  - !ruby/object:Gem::Version
26
- version: 0.33.0
26
+ version: 0.33.1
27
27
  description: VHDL writer plugin for RgGen
28
28
  email:
29
29
  - rggen@googlegroups.com
@@ -126,8 +126,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
126
126
  - !ruby/object:Gem::Version
127
127
  version: '0'
128
128
  requirements: []
129
- rubygems_version: 3.5.5
129
+ rubygems_version: 3.5.16
130
130
  signing_key:
131
131
  specification_version: 4
132
- summary: rggen-vhdl-0.10.0
132
+ summary: rggen-vhdl-0.10.1
133
133
  test_files: []