rggen-vhdl 0.10.0 → 0.10.1
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- checksums.yaml +4 -4
- data/lib/rggen/vhdl/register/type/indirect.erb +1 -4
- data/lib/rggen/vhdl/register/type/indirect.rb +15 -15
- data/lib/rggen/vhdl/version.rb +1 -1
- metadata +6 -6
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
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1
1
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---
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2
2
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SHA256:
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3
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-
metadata.gz:
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4
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-
data.tar.gz:
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3
|
+
metadata.gz: a40b2314cf782eff83c05a24378bdcdcb3022dc19df32e1eb3cf3c9bc8270f0b
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4
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+
data.tar.gz: d3b5529f4247a8b1118859542328402bfc025290c1139b40c7d93ab62d6d4c2c
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5
5
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SHA512:
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6
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-
metadata.gz:
|
7
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-
data.tar.gz:
|
6
|
+
metadata.gz: 7b81bc63e6ab3ed5a4b0d4d948162ce575f604fb2de3f25d8941fe196ec6c8f399e8c3a909ecc239cb37e1e03ea314f220b88e83a8b80d33cc21519a900020eb
|
7
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+
data.tar.gz: 76f2b1ac8d10a91750b1ea5c24ab5b75ba78d5ef54e8d9ad178b32dfbe7b73fab0551733281d3ebf808ccb3640fff5bc8cf17695bc1a38cf4ea89e06f2835821
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@@ -1,6 +1,3 @@
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1
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-
<% index_fields_and_values.each_with_index do |(field, value), i| %>
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2
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-
<%= indirect_match[i] %> <= '1' when unsigned(<%= field %>) = <%= value %> else '0';
|
3
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-
<% end %>
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4
1
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u_register: entity <%= library_name %>.rggen_indirect_register
|
5
2
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generic map (
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6
3
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READABLE => <%= readable? %>,
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@@ -9,7 +6,7 @@ u_register: entity <%= library_name %>.rggen_indirect_register
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9
6
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OFFSET_ADDRESS => <%= offset_address %>,
|
10
7
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BUS_WIDTH => <%= bus_width %>,
|
11
8
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DATA_WIDTH => <%= width %>,
|
12
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-
INDIRECT_MATCH_WIDTH => <%=
|
9
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+
INDIRECT_MATCH_WIDTH => <%= index_match_width %>
|
13
10
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)
|
14
11
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port map (
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15
12
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i_clk => <%= clock %>,
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@@ -2,33 +2,33 @@
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2
2
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3
3
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RgGen.define_list_item_feature(:register, :type, :indirect) do
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4
4
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vhdl do
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5
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+
include RgGen::SystemVerilog::RTL::IndirectIndex
|
6
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+
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5
7
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build do
|
6
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-
signal :indirect_match, { width:
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8
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+
signal :indirect_match, { width: index_match_width }
|
7
9
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end
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8
10
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|
9
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-
main_code :register
|
11
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+
main_code :register do |code|
|
12
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+
indirect_index_matches(code)
|
13
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+
code << process_template
|
14
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+
end
|
10
15
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|
11
16
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private
|
12
17
|
|
13
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-
def
|
14
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-
|
18
|
+
def array_index_value(value, _width)
|
19
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+
value
|
15
20
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end
|
16
21
|
|
17
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-
def
|
18
|
-
|
19
|
-
.collect_index_fields(register_block.bit_fields)
|
20
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-
.map(&:value)
|
22
|
+
def fixed_index_value(value, _width)
|
23
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+
value
|
21
24
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end
|
22
25
|
|
23
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-
def
|
24
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-
|
25
|
-
register.index_entries.map do |entry|
|
26
|
-
entry.array_index? && loop_variables.shift || entry.value
|
27
|
-
end
|
26
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+
def index_match_rhs(index)
|
27
|
+
indirect_match[index]
|
28
28
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end
|
29
29
|
|
30
|
-
def
|
31
|
-
|
30
|
+
def index_match_lhs(field, value)
|
31
|
+
"'1' when unsigned(#{field}) = #{value} else '0'"
|
32
32
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end
|
33
33
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end
|
34
34
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end
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data/lib/rggen/vhdl/version.rb
CHANGED
metadata
CHANGED
@@ -1,14 +1,14 @@
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1
1
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--- !ruby/object:Gem::Specification
|
2
2
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name: rggen-vhdl
|
3
3
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version: !ruby/object:Gem::Version
|
4
|
-
version: 0.10.
|
4
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+
version: 0.10.1
|
5
5
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platform: ruby
|
6
6
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authors:
|
7
7
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- Taichi Ishitani
|
8
8
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autorequire:
|
9
9
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bindir: bin
|
10
10
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cert_chain: []
|
11
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-
date: 2024-
|
11
|
+
date: 2024-11-28 00:00:00.000000000 Z
|
12
12
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dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
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name: rggen-systemverilog
|
@@ -16,14 +16,14 @@ dependencies:
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|
16
16
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requirements:
|
17
17
|
- - ">="
|
18
18
|
- !ruby/object:Gem::Version
|
19
|
-
version: 0.33.
|
19
|
+
version: 0.33.1
|
20
20
|
type: :runtime
|
21
21
|
prerelease: false
|
22
22
|
version_requirements: !ruby/object:Gem::Requirement
|
23
23
|
requirements:
|
24
24
|
- - ">="
|
25
25
|
- !ruby/object:Gem::Version
|
26
|
-
version: 0.33.
|
26
|
+
version: 0.33.1
|
27
27
|
description: VHDL writer plugin for RgGen
|
28
28
|
email:
|
29
29
|
- rggen@googlegroups.com
|
@@ -126,8 +126,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
|
|
126
126
|
- !ruby/object:Gem::Version
|
127
127
|
version: '0'
|
128
128
|
requirements: []
|
129
|
-
rubygems_version: 3.5.
|
129
|
+
rubygems_version: 3.5.16
|
130
130
|
signing_key:
|
131
131
|
specification_version: 4
|
132
|
-
summary: rggen-vhdl-0.10.
|
132
|
+
summary: rggen-vhdl-0.10.1
|
133
133
|
test_files: []
|