rggen-veryl 0.3.0 → 0.4.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: '06838b3a4664045b2a8a9e2cd03f18aac6abfa587f383b02eb99c77566ec2bd5'
+  metadata.gz: d92c6db46e4bebb4c853f1a4a4599eed524a1d77a8cc6f7b62b65f282e032497
+  data.tar.gz: ae35fde024ba27dd80292c61504c39b4535bbea71d406f2bd357df1f4d6a9f51
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-  data.tar.gz: 2787dba578e8fbefd0f92f9c340720a5b138b4164dee4d544deca4ef14415ff40e503e65829a794c73b1b12322468541341afe292d8f38f1c266273fb92de1ca
+  metadata.gz: d5b4c108e8df2ee9773b98c27afd706f6b52a34b519179fbd37e83736bb631915e2145cbb137dd920680fdbb8fa3b866cb5cc3dcaff5215488ab9c6aa869520b
+  data.tar.gz: 2749d7b449e9c7488786c9fda5a45724dd2eedb20255435466934deeb7f3ef0e097020b941f34a7c481736fb4a53a0c12e52e601e006f34c4b220804d003d308

data/README.md

@@ -43,7 +43,7 @@ You need to add this repository to the `[dependencies]` section in your `Veryl.t
 
 ```toml
 [dependencies]
-"https://github.com/rggen/rggen-veryl-rtl" = "0.3.0"
+"rggen" = { github = "rggen/rggen-veryl-rtl", version = "0.4.0" }
 ```
 
 ## Contact

data/lib/rggen/veryl/bit_field/type/custom.erb

@@ -3,10 +3,10 @@ inst u_bit_field: rggen::rggen_bit_field #(
   INITIAL_VALUE:      <%= initial_value %>,
   SW_READ_ACTION:     rggen_sw_action::<%= sw_read_action %>,
   SW_WRITE_ACTION:    rggen_sw_action::<%= sw_write_action %>,
-  SW_WRITE_ONCE:      <%= write_once %>,
-  STORAGE:            <%= storage %>,
-  EXTERNAL_READ_DATA: <%= external_read_data %>,
-  TRIGGER:            <%= trigger %>
+  SW_WRITE_ONCE:      <%= write_once? %>,
+  STORAGE:            <%= storage? %>,
+  EXTERNAL_READ_DATA: <%= external_read_data? %>,
+  TRIGGER:            <%= trigger? %>
 )(
   i_clk:              i_clk,
   i_rst:              i_rst,

data/lib/rggen/veryl/bit_field/type/custom.rb

@@ -78,26 +78,18 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
       }[bit_field.sw_write]
     end
 
-    def write_once
-      bit_field.sw_write_once? && 1 || 0
+    def write_once?
+      bit_field.sw_write_once?
     end
 
-    def storage
-      external_read_data? && 0 || 1
-    end
-
-    def external_read_data
-      external_read_data? && 1 || 0
+    def storage?
+      !external_read_data?
     end
 
     def trigger?
       bit_field.write_trigger? || bit_field.read_trigger?
     end
 
-    def trigger
-      trigger? && 1 || 0
-    end
-
     def input_port(name)
       find_port(name, all_bits_0)
     end

data/lib/rggen/veryl/bit_field/type/ro_rotrg.erb

@@ -1,9 +1,9 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:              <%= width %>,
   SW_WRITE_ACTION:    rggen_sw_action::WRITE_NONE,
-  STORAGE:            0,
-  EXTERNAL_READ_DATA: 1,
-  TRIGGER:            <%= trigger %>
+  STORAGE:            false,
+  EXTERNAL_READ_DATA: true,
+  TRIGGER:            <%= rotrg? %>
 )(
   i_clk:          <%= clock %>,
   i_rst:          <%= reset %>,

data/lib/rggen/veryl/bit_field/type/ro_rotrg.rb

@@ -23,10 +23,6 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
       bit_field.type == :rotrg
     end
 
-    def trigger
-      rotrg? && 1 || 0
-    end
-
     def read_trigger_signal
       rotrg? && read_trigger[loop_variables] || unused
     end

data/lib/rggen/veryl/bit_field/type/rof.erb

@@ -1,11 +1,11 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:              <%= width %>,
   SW_WRITE_ACTION:    rggen_sw_action::WRITE_NONE,
-  STORAGE:            0,
-  EXTERNAL_READ_DATA: 1
+  STORAGE:            false,
+  EXTERNAL_READ_DATA: true
 )(
-  i_clk:        '0,
-  i_rst:        '0,
+  i_clk:        <%= clock %>,
+  i_rst:        <%= reset %>,
   bit_field_if: <%= bit_field_if %>,
   i_value:      <%= initial_value %>
 );

data/lib/rggen/veryl/bit_field/type/rowo_rowotrg.erb

@@ -1,8 +1,8 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:              <%= width %>,
   INITIAL_VALUE:      <%= initial_value %>,
-  EXTERNAL_READ_DATA: 1,
-  TRIGGER:            <%= trigger %>
+  EXTERNAL_READ_DATA: true,
+  TRIGGER:            <%= rowotrg? %>
 )(
   i_clk:            <%= clock %>,
   i_rst:            <%= reset %>,

data/lib/rggen/veryl/bit_field/type/rowo_rowotrg.rb

@@ -29,10 +29,6 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
       bit_field.type == :rowotrg
     end
 
-    def trigger
-      rowotrg? && 1 || 0
-    end
-
     def write_trigger_signal
       rowotrg? && write_trigger[loop_variables] || unused
     end

data/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.erb

@@ -1,8 +1,8 @@
 inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:          <%= width %>,
   INITIAL_VALUE:  <%= initial_value %>,
-  SW_WRITE_ONCE:  <%= write_once %>,
-  TRIGGER:        <%= trigger %>
+  SW_WRITE_ONCE:  <%= write_once? %>,
+  TRIGGER:        <%= rwtrg? %>
 )(
   i_clk:            <%= clock %>,
   i_rst:            <%= reset %>,

data/lib/rggen/veryl/bit_field/type/rw_rwtrg_w1.rb

@@ -24,10 +24,6 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
       bit_field.type == :rwtrg
     end
 
-    def trigger
-      rwtrg? && 1 || 0
-    end
-
     def write_trigger_signal
       rwtrg? && write_trigger[loop_variables] || unused
     end
@@ -36,8 +32,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
       rwtrg? && read_trigger[loop_variables] || unused
     end
 
-    def write_once
-      bit_field.type == :w1 && 1 || 0
+    def write_once?
+      bit_field.type == :w1
     end
   end
 end

data/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.erb

@@ -2,8 +2,8 @@ inst u_bit_field: rggen::rggen_bit_field #(
   WIDTH:          <%= width %>,
   INITIAL_VALUE:  <%= initial_value %>,
   SW_READ_ACTION: rggen_sw_action::READ_NONE,
-  SW_WRITE_ONCE:  <%= write_once %>,
-  TRIGGER:        <%= trigger %>
+  SW_WRITE_ONCE:  <%= write_once? %>,
+  TRIGGER:        <%= wotrg? %>
 )(
   i_clk:            <%= clock %>,
   i_rst:            <%= reset %>,

data/lib/rggen/veryl/bit_field/type/wo_wo1_wotrg.rb

@@ -21,16 +21,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
       bit_field.type == :wotrg
     end
 
-    def trigger
-      wotrg? && 1 || 0
-    end
-
     def write_trigger_signal
       wotrg? && write_trigger[loop_variables] || unused
     end
 
-    def write_once
-      bit_field.type == :wo1 && 1 || 0
+    def write_once?
+      bit_field.type == :wo1
     end
   end
 end

data/lib/rggen/veryl/feature.rb

@@ -22,6 +22,10 @@ module RgGen
         Modport.new(attributes, &)
       end
 
+      def create_generic(_, attributes, &)
+        DataObject.new(:generic, attributes, &)
+      end
+
       def create_param(_, attributes, &)
         DataObject.new(:param, attributes, &)
       end
@@ -38,6 +42,7 @@ module RgGen
       define_entity :output, :create_port, :port, -> { register_block }
       define_entity :modport, :create_modport, :port, -> { register_block }
       define_entity :interface, :create_if_instance, :variable, -> { component }
+      define_entity :generic, :create_generic, :generic, -> { register_block }
       define_entity :param, :create_param, :parameter, -> { register_block }
       define_entity :const, :create_const, :parameter, -> { component }
       define_entity :var, :create_var, :variable, -> { component }

data/lib/rggen/veryl/register/type/default.erb

@@ -1,6 +1,6 @@
 inst u_register: rggen::rggen_default_register #(
-  READABLE:       <%= readable %>,
-  WRITABLE:       <%= writable %>,
+  READABLE:       <%= readable? %>,
+  WRITABLE:       <%= writable? %>,
   ADDRESS_WIDTH:  <%= address_width %>,
   OFFSET_ADDRESS: <%= offset_address %>,
   BUS_WIDTH:      <%= bus_width %>,

data/lib/rggen/veryl/register/type/indirect.erb

@@ -1,6 +1,6 @@
 inst u_register: rggen::rggen_indirect_register #(
-  READABLE:             <%= readable %>,
-  WRITABLE:             <%= writable %>,
+  READABLE:             <%= readable? %>,
+  WRITABLE:             <%= writable? %>,
   ADDRESS_WIDTH:        <%= address_width %>,
   OFFSET_ADDRESS:       <%= offset_address %>,
   BUS_WIDTH:            <%= bus_width %>,

data/lib/rggen/veryl/register/type/rw.erb

@@ -1,6 +1,6 @@
 inst u_register: rggen::rggen_default_register #(
-  READABLE:       1,
-  WRITABLE:       1,
+  READABLE:       true,
+  WRITABLE:       true,
   ADDRESS_WIDTH:  <%= address_width %>,
   OFFSET_ADDRESS: <%= offset_address %>,
   BUS_WIDTH:      <%= bus_width %>,

data/lib/rggen/veryl/register/type.rb

@@ -7,6 +7,14 @@ RgGen.define_list_feature(:register, :type) do
 
       private
 
+      def readable?
+        register.readable?
+      end
+
+      def writable?
+        register.writable?
+      end
+
       def register_if
         register_block.register_if[register.index]
       end

data/lib/rggen/veryl/register_block/protocol/axi4lite.rb

@@ -7,7 +7,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'ID_WIDTH', type: :u32, default: 0
       }
       param :write_first, {
-        name: 'WRITE_FIRST', type: :bit, default: 1
+        name: 'WRITE_FIRST', type: :bool, default: true
       }
       modport :axi4lite_if, {
         name: 'axi4lite_if',

data/lib/rggen/veryl/register_block/protocol/native.rb

@@ -7,7 +7,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
         name: 'STROBE_WIDTH', type: :u32, default: bus_width / 8
       }
       param :use_read_strobe, {
-        name: 'USE_READ_STROBE', type: :bit, default: 0
+        name: 'USE_READ_STROBE', type: :bool, default: false
       }
       modport :csrbus_if, {
         name: 'csrbus_if',

data/lib/rggen/veryl/register_block/protocol.rb

@@ -10,19 +10,19 @@ RgGen.define_list_feature(:register_block, :protocol) do
           name: 'ADDRESS_WIDTH', type: :u32, default: local_address_width
         }
         param :pre_decode, {
-          name: 'PRE_DECODE', type: :bit, default: 0
+          name: 'PRE_DECODE', type: :bool, default: false
         }
         param :base_address, {
           name: 'BASE_ADDRESS', type: :bit, width: address_width, default: all_bits_0
         }
         param :error_status, {
-          name: 'ERROR_STATUS', type: :bit, default: 0
+          name: 'ERROR_STATUS', type: :bool, default: false
         }
         param :default_read_data, {
           name: 'DEFAULT_READ_DATA', type: :bit, width: bus_width, default: all_bits_0
         }
         param :insert_slicer, {
-          name: 'INSERT_SLICER', type: :bit, default: 0
+          name: 'INSERT_SLICER', type: :bool, default: false
         }
       end
 

data/lib/rggen/veryl/register_map/keyword_checker.rb

@@ -5,15 +5,16 @@ module RgGen
     module RegisterMap
       module KeywordChecker
         VERYL_KEYWORDS = [
-          'always_comb', 'always_ff', 'as', 'assign', 'bit', 'break', 'case', 'clock',
-          'clock_negedge', 'clock_posedge', 'const', 'default', 'else', 'embed', 'enum',
-          'export', 'f32', 'f64', 'final', 'for', 'function', 'i32', 'i64', 'if',
-          'if_reset', 'import', 'in', 'include', 'initial', 'inout', 'input', 'inside',
-          'inst', 'interface', 'let', 'local', 'logic', 'modport', 'module', 'output',
-          'outside', 'package', 'param', 'proto', 'pub', 'ref', 'repeat', 'reset',
-          'reset_async_high', 'reset_async_low', 'reset_sync_high', 'reset_sync_low',
-          'return', 'signed', 'step', 'struct', 'switch', 'tri', 'type', 'u32', 'u64',
-          'unsafe', 'var'
+          'alias', 'always_comb', 'always_ff', 'assign', 'as', 'bit', 'bool', 'case',
+          'clock', 'clock_posedge', 'clock_negedge', 'connect', 'const', 'converse',
+          'default', 'else', 'embed', 'enum', 'f32', 'f64', 'false', 'final', 'for',
+          'function', 'i32', 'i64', 'if_reset', 'if', 'import', 'include', 'initial',
+          'inout', 'input', 'inside', 'inst', 'interface', 'in', 'let', 'logic', 'lsb',
+          'modport', 'module', 'msb', 'output', 'outside', 'package', 'param', 'proto',
+          'pub', 'repeat', 'reset', 'reset_async_high', 'reset_async_low',
+          'reset_sync_high', 'reset_sync_low', 'return', 'break', 'same', 'signed',
+          'step', 'string', 'struct', 'switch', 'tri', 'true', 'type', 'u32', 'u64',
+          'union', 'unsafe', 'var'
         ].freeze
 
         def self.included(klass)

data/lib/rggen/veryl/utility/data_object.rb

@@ -61,7 +61,7 @@ module RgGen
         end
 
         def emit_width?
-          width && (!width.is_a?(Integer) || width >= 2)
+          (@object_type != :generic) && width && (!width.is_a?(Integer) || width >= 2)
         end
 
         def array_dimensions
@@ -71,7 +71,12 @@ module RgGen
         end
 
         def default_value
-          "= #{default}" if @object_type in :param | :const
+          "= #{default}" if emit_default_value?
+        end
+
+        def emit_default_value?
+          instance_variable_defined?(:@default) &&
+            (@object_type in :generic | :param | :const)
         end
       end
     end

data/lib/rggen/veryl/utility/module_definition.rb

@@ -6,6 +6,7 @@ module RgGen
       class ModuleDefinition < SystemVerilog::Common::Utility::StructureDefinition
         define_attribute :name
         define_attribute :package_imports
+        define_attribute :generics
         define_attribute :params
         define_attribute :ports
         define_attribute :variables
@@ -15,6 +16,7 @@ module RgGen
         def header_code(code)
           package_import_declaration(code)
           module_header_begin(code)
+          generic_declarations(code)
           param_declarations(code)
           port_declarations(code)
           module_header_end(code)
@@ -27,7 +29,20 @@ module RgGen
         end
 
         def module_header_begin(code)
-          code << "pub module #{name} "
+          code << "pub module #{name}"
+          code << ' ' unless include_generics?
+        end
+
+        def include_generics?
+          (generics&.size || 0).positive?
+        end
+
+        def generic_declarations(code)
+          return unless include_generics?
+
+          wrap(code, '::<', '>') do
+            add_declarations_to_header(code, generics)
+          end
         end
 
         def param_declarations(code)

data/lib/rggen/veryl/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Veryl
-    VERSION = '0.3.0'
+    VERSION = '0.4.0'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-veryl
 version: !ruby/object:Gem::Version
-  version: 0.3.0
+  version: 0.4.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-02-19 00:00:00.000000000 Z
+date: 2025-04-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -132,5 +132,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-veryl-0.3.0
+summary: rggen-veryl-0.4.0
 test_files: []