rggen-verilog 0.8.1 → 0.9.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 501905cb54813b90fc9080c475f4c1b14c341ede3538e10628e9e30d0cb39c24
-  data.tar.gz: bfe15d77b852c68ba19b8a4f17e8f9cf961e218c21c294d752268add08262a95
+  metadata.gz: 9c26c2ca7f16bb814bd71bd09e0139bc79bbc095389653585843024e2944314b
+  data.tar.gz: fa8243ba5f46b51121594dbd982971b3bc253832de69a00229260d23df5dc446
 SHA512:
-  metadata.gz: '024865e81e0e44340b062633e411e4bd1b5db96e67d72e10aeacce980610f0d6a0cdd2db273dcf33e1fd4fca9a96a8a43a23bf7722b4e4b097853a80d403e7c2'
-  data.tar.gz: 2bee917871bf9e33cc311aa84fe7bc39e6a8cfff18ec9ee7e0e970f01a5efbfde923aa2271e257032d5af5a271a9b12507afde8c65ff8cee8a3d39fc917d769f
+  metadata.gz: e1359eeb96ed656ad11c5d8dc3c51e2274d97b629a273a1594268ef2a0ace7c8d4db144a83c14b0229f0c8eb49704e141b89d05764d556a34c4d408a9a13cc6b
+  data.tar.gz: 617201c69145f451c1bb33794af0356082cf6a5009f6834ff548d651a1d436785045455f85d21597f1277ba8a0deba03d1815a04a6d53aed6ff93f6364ad84b7

data/lib/rggen/verilog/rtl/register/type/external.erb

@@ -1,6 +1,7 @@
 rggen_external_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .BUS_WIDTH      (<%= bus_width %>),
+  .STROBE_WIDTH   (<%= strobe_width %>),
   .START_ADDRESS  (<%= start_address %>),
   .BYTE_SIZE      (<%= byte_size %>)
 ) u_register (

data/lib/rggen/verilog/rtl/register/type/external.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   verilog_rtl do
     build do
+      parameter :strobe_width, {
+        name: "#{register.name}_strobe_width".upcase,
+        default: configuration.bus_width / 8
+      }
       output :external_valid, {
         name: "o_#{register.name}_valid", width: 1
       }
@@ -16,7 +20,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
         name: "o_#{register.name}_data", width: bus_width
       }
       output :external_strobe, {
-        name: "o_#{register.name}_strobe", width: bus_width / 8
+        name: "o_#{register.name}_strobe", width: strobe_width
       }
       input :external_ready, {
         name: "i_#{register.name}_ready", width: 1

data/lib/rggen/verilog/rtl/register/type/rw.erb

@@ -0,0 +1,27 @@
+rggen_default_register #(
+  .READABLE       (1),
+  .WRITABLE       (1),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>)
+) u_register (
+  .i_clk                  (<%= clock %>),
+  .i_rst_n                (<%= reset %>),
+  .i_register_valid       (<%= register_valid %>),
+  .i_register_access      (<%= register_access %>),
+  .i_register_address     (<%= register_address %>),
+  .i_register_write_data  (<%= register_write_data %>),
+  .i_register_strobe      (<%= register_strobe %>),
+  .o_register_active      (<%= register_active %>),
+  .o_register_ready       (<%= register_ready %>),
+  .o_register_status      (<%= register_status %>),
+  .o_register_read_data   (<%= register_read_data %>),
+  .o_register_value       (<%= register_value %>),
+  .o_bit_field_valid      (<%= bit_field_valid %>),
+  .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
+  .o_bit_field_write_mask (<%= bit_field_write_mask %>),
+  .o_bit_field_write_data (<%= bit_field_write_data %>),
+  .i_bit_field_read_data  (<%= bit_field_read_data %>),
+  .i_bit_field_value      (<%= bit_field_value %>)
+);

data/lib/rggen/verilog/rtl/register/type/rw.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :rw) do
+  verilog_rtl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/verilog/rtl/register_block/verilog_top.rb

@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
         name: 'w_register_write_data', width: bus_width
       }
       wire :register_strobe, {
-        name: 'w_register_strobe', width: bus_width / 8
+        name: 'w_register_strobe', width: bus_width
       }
       wire :register_active, {
         name: 'w_register_active', width: 1, array_size: [total_registers]

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.8.1'
+    VERSION = '0.9.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl/register/type',
     'verilog/rtl/register/type/external',
     'verilog/rtl/register/type/indirect',
+    'verilog/rtl/register/type/rw',
     'verilog/rtl/bit_field/verilog_top',
     'verilog/rtl/bit_field/type',
     'verilog/rtl/bit_field/type/custom',

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.8.1
+  version: 0.9.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-06-09 00:00:00.000000000 Z
+date: 2023-09-12 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.1
+        version: 0.31.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.1
+        version: 0.31.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -94,6 +94,8 @@ files:
 - lib/rggen/verilog/rtl/register/type/external.rb
 - lib/rggen/verilog/rtl/register/type/indirect.erb
 - lib/rggen/verilog/rtl/register/type/indirect.rb
+- lib/rggen/verilog/rtl/register/type/rw.erb
+- lib/rggen/verilog/rtl/register/type/rw.rb
 - lib/rggen/verilog/rtl/register/verilog_top.rb
 - lib/rggen/verilog/rtl/register_block/protocol.rb
 - lib/rggen/verilog/rtl/register_block/protocol/apb.erb
@@ -137,8 +139,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.10
+rubygems_version: 3.4.17
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.8.1
+summary: rggen-verilog-0.9.0
 test_files: []