rggen-verilog 0.8.0 → 0.8.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 3c4b37181e16fd1f97b0cbfc7fa45f58d7c69677930907dde6e60d2064d9842a
-  data.tar.gz: 4b245b8815da6fca8ea8bc4abf4c67c83f56c1534693c24851a767e22175e471
+  metadata.gz: 501905cb54813b90fc9080c475f4c1b14c341ede3538e10628e9e30d0cb39c24
+  data.tar.gz: bfe15d77b852c68ba19b8a4f17e8f9cf961e218c21c294d752268add08262a95
 SHA512:
-  metadata.gz: 6fc8c0cc66ae71e65543274c7f50f3cd9876355528e6a55c71c83f8d75876f05a26518f357b8c7370710496c568a2b87305b8d3a0b5bc440c451e8a6838e0908
-  data.tar.gz: 8416671228b6589ee79b1db4f505d3c0af7053ca0ce4aedfa1c4e6dacc1b8210aa8e6a8d5dc8e12b6a1ae97a8836af07a61cd77b56ba49da2af014c368cf7dc4
+  metadata.gz: '024865e81e0e44340b062633e411e4bd1b5db96e67d72e10aeacce980610f0d6a0cdd2db273dcf33e1fd4fca9a96a8a43a23bf7722b4e4b097853a80d403e7c2'
+  data.tar.gz: 2bee917871bf9e33cc311aa84fe7bc39e6a8cfff18ec9ee7e0e970f01a5efbfde923aa2271e257032d5af5a271a9b12507afde8c65ff8cee8a3d39fc917d769f

data/lib/rggen/verilog/rtl/bit_field/type.rb

@@ -22,8 +22,17 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || 0
-        macro_call('rggen_slice', [bit_field.initial_value, width, index])
+        if multiple_initial_values?
+          index = bit_field.local_index
+          total_bits = width * bit_field.sequence_size
+          macro_call('rggen_slice', [bit_field.initial_value, total_bits, width, index])
+        else
+          bit_field.initial_value
+        end
+      end
+
+      def multiple_initial_values?
+        bit_field.initial_value_array? && bit_field.sequence_size > 1
       end
 
       def clock

data/lib/rggen/verilog/rtl/register/type/external.erb

@@ -2,7 +2,7 @@ rggen_external_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .START_ADDRESS  (<%= start_address %>),
-  .END_ADDRESS    (<%= end_address %>)
+  .BYTE_SIZE      (<%= byte_size %>)
 ) u_register (
   .i_clk                  (<%= clock %>),
   .i_rst_n                (<%= reset %>),

data/lib/rggen/verilog/rtl/register/type/external.rb

@@ -37,8 +37,8 @@ RgGen.define_list_item_feature(:register, :type, :external) do
       hex(register.address_range.begin, address_width)
     end
 
-    def end_address
-      hex(register.address_range.last, address_width)
+    def byte_size
+      register.total_byte_size
     end
   end
 end

data/lib/rggen/verilog/utility.rb

@@ -16,6 +16,10 @@ module RgGen
       def fill_1(width)
         "{#{width}{1'b1}}"
       end
+
+      def width_cast(expression, _width)
+        expression
+      end
     end
   end
 end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.8.0'
+    VERSION = '0.8.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.8.0
+  version: 0.8.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-04-28 00:00:00.000000000 Z
+date: 2023-06-09 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.0
+        version: 0.30.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.30.0
+        version: 0.30.1
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -140,5 +140,5 @@ requirements: []
 rubygems_version: 3.4.10
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.8.0
+summary: rggen-verilog-0.8.1
 test_files: []