rggen-verilog 0.4.1 → 0.5.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -60,7 +60,8 @@ $ simulator \
 
 Feedbacks, bus reports, questions and etc. are welcome! You can post them bu using following ways:
 
-* [GitHub Issue Tracker](https://github.com/rggen/rggen-verilog/issues)
+* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
+* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
 * [Chat Room](https://gitter.im/rggen/rggen)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)

data/lib/rggen/verilog/bit_field/type/row0trg_row1trg.erb

@@ -0,0 +1,16 @@
+rggen_bit_field_w01trg #(
+  .TRIGGER_VALUE  (<%= trigger_value %>),
+  .WIDTH          (<%= width %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .i_value            (<%= reference_or_value_in %>),
+  .o_trigger          (<%= trigger[loop_variables] %>)
+);

data/lib/rggen/verilog/bit_field/type/row0trg_row1trg.rb

@@ -0,0 +1,28 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :value_in, {
+          name: "i_#{full_name}", width: width, array_size: array_size
+        }
+      end
+      output :trigger, {
+        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def trigger_value
+      bin({ row0trg: 0, row1trg: 1 }[bit_field.type], 1)
+    end
+
+    def reference_or_value_in
+      reference_bit_field || value_in[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb

@@ -2,13 +2,15 @@ rggen_bit_field_w01trg #(
   .TRIGGER_VALUE  (<%= trigger_value %>),
   .WIDTH          (<%= width %>)
 ) u_bit_field (
-  .i_clk                  (<%= clock %>),
-  .i_rst_n                (<%= reset %>),
-  .i_bit_field_valid      (<%= bit_field_valid %>),
-  .i_bit_field_read_mask  (<%= bit_field_read_mask %>),
-  .i_bit_field_write_mask (<%= bit_field_write_mask %>),
-  .i_bit_field_write_data (<%= bit_field_write_data %>),
-  .o_bit_field_read_data  (<%= bit_field_read_data %>),
-  .o_bit_field_value      (<%= bit_field_value %>),
-  .o_trigger              (<%= trigger[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .i_sw_valid         (<%= bit_field_valid %>),
+  .i_sw_read_mask     (<%= bit_field_read_mask %>),
+  .i_sw_write_enable  (1'b1),
+  .i_sw_write_mask    (<%= bit_field_write_mask %>),
+  .i_sw_write_data    (<%= bit_field_write_data %>),
+  .o_sw_read_data     (<%= bit_field_read_data %>),
+  .o_sw_value         (<%= bit_field_value %>),
+  .i_value            (<%= fill_0(width) %>),
+  .o_trigger          (<%= trigger[loop_variables] %>)
 );

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.4.1'
+    VERSION = '0.5.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -8,44 +8,43 @@ require_relative 'verilog/component'
 require_relative 'verilog/feature'
 require_relative 'verilog/factories'
 
-module RgGen
-  module Verilog
-    extend Core::Plugin
+RgGen.setup_plugin :'rggen-verilog' do |plugin|
+  plugin.version RgGen::Verilog::VERSION
 
-    setup_plugin :'rggen-verilog' do |plugin|
-      plugin.register_component :verilog do
-        component Component, ComponentFactory
-        feature Feature, FeatureFactory
-      end
-
-      plugin.files [
-        'verilog/bit_field/type',
-        'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
-        'verilog/bit_field/type/ro_rotrg',
-        'verilog/bit_field/type/rof',
-        'verilog/bit_field/type/rowo_rowotrg',
-        'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
-        'verilog/bit_field/type/rw_rwtrg_w1',
-        'verilog/bit_field/type/rwc',
-        'verilog/bit_field/type/rwe_rwl',
-        'verilog/bit_field/type/rws',
-        'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
-        'verilog/bit_field/type/w0t_w1t',
-        'verilog/bit_field/type/w0trg_w1trg',
-        'verilog/bit_field/type/wo_wo1_wotrg',
-        'verilog/bit_field/type/wrc_wrs',
-        'verilog/bit_field/verilog_top',
-        'verilog/register/type',
-        'verilog/register/type/external',
-        'verilog/register/type/indirect',
-        'verilog/register/verilog_top',
-        'verilog/register_block/protocol',
-        'verilog/register_block/protocol/apb',
-        'verilog/register_block/protocol/axi4lite',
-        'verilog/register_block/protocol/wishbone',
-        'verilog/register_block/verilog_top',
-        'verilog/register_file/verilog_top'
-      ]
-    end
+  plugin.register_component :verilog do
+    component RgGen::Verilog::Component,
+              RgGen::Verilog::ComponentFactory
+    feature RgGen::Verilog::Feature,
+            RgGen::Verilog::FeatureFactory
   end
+
+  plugin.files [
+    'verilog/register_block/verilog_top',
+    'verilog/register_block/protocol',
+    'verilog/register_block/protocol/apb',
+    'verilog/register_block/protocol/axi4lite',
+    'verilog/register_block/protocol/wishbone',
+    'verilog/register_file/verilog_top',
+    'verilog/register/verilog_top',
+    'verilog/register/type',
+    'verilog/register/type/external',
+    'verilog/register/type/indirect',
+    'verilog/bit_field/verilog_top',
+    'verilog/bit_field/type',
+    'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
+    'verilog/bit_field/type/ro_rotrg',
+    'verilog/bit_field/type/rof',
+    'verilog/bit_field/type/row0trg_row1trg',
+    'verilog/bit_field/type/rowo_rowotrg',
+    'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
+    'verilog/bit_field/type/rw_rwtrg_w1',
+    'verilog/bit_field/type/rwc',
+    'verilog/bit_field/type/rwe_rwl',
+    'verilog/bit_field/type/rws',
+    'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+    'verilog/bit_field/type/w0t_w1t',
+    'verilog/bit_field/type/w0trg_w1trg',
+    'verilog/bit_field/type/wo_wo1_wotrg',
+    'verilog/bit_field/type/wrc_wrs'
+  ]
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.4.1
+  version: 0.5.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-06-07 00:00:00.000000000 Z
+date: 2022-07-05 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.26.0
+        version: 0.27.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -56,6 +56,8 @@ files:
 - lib/rggen/verilog/bit_field/type/ro_rotrg.rb
 - lib/rggen/verilog/bit_field/type/rof.erb
 - lib/rggen/verilog/bit_field/type/rof.rb
+- lib/rggen/verilog/bit_field/type/row0trg_row1trg.erb
+- lib/rggen/verilog/bit_field/type/row0trg_row1trg.rb
 - lib/rggen/verilog/bit_field/type/rowo_rowotrg.erb
 - lib/rggen/verilog/bit_field/type/rowo_rowotrg.rb
 - lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb
@@ -99,7 +101,6 @@ files:
 - lib/rggen/verilog/register_block/verilog_macros.erb
 - lib/rggen/verilog/register_block/verilog_top.rb
 - lib/rggen/verilog/register_file/verilog_top.rb
-- lib/rggen/verilog/setup.rb
 - lib/rggen/verilog/utility.rb
 - lib/rggen/verilog/utility/local_scope.rb
 - lib/rggen/verilog/version.rb
@@ -107,7 +108,7 @@ homepage: https://github.com/rggen/rggen-verilog
 licenses:
 - MIT
 metadata:
-  bug_tracker_uri: https://github.com/rggen/rggen-verilog/issues
+  bug_tracker_uri: https://github.com/rggen/rggen/issues
   mailing_list_uri: https://groups.google.com/d/forum/rggen
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-verilog
@@ -130,5 +131,5 @@ requirements: []
 rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.4.1
+summary: rggen-verilog-0.5.0
 test_files: []

data/lib/rggen/verilog/setup.rb

@@ -1,11 +0,0 @@
-# frozen_string_literal: true
-
-require 'rggen/verilog'
-
-RgGen.register_plugin RgGen::Verilog do |builder|
-  builder.load_plugin 'rggen/systemverilog/rtl/setup'
-  builder.enable :register_block, [:verilog_top]
-  builder.enable :register_file, [:verilog_top]
-  builder.enable :register, [:verilog_top]
-  builder.enable :bit_field, [:verilog_top]
-end