rggen-verilog 0.2.0 → 0.3.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: bf021f06b55444d10dd0aac02dc945a23fa8033403719cc4bf979afaf433a120
-  data.tar.gz: 0ac61bb02b3f6cbbbc8b7281f85ac2607ad741a9159721327eef4206c652894d
+  metadata.gz: eea0415f0d8ad111af37525833522c9f542d5815e56d954aa69e22f973096919
+  data.tar.gz: cba5ff6f30efa182b035d62698d8017f3bda815e5eca1b2e5cbe093ba525a4b3
 SHA512:
-  metadata.gz: 3c597337180c58cceb309ee668208e292b07640a371f4fa825895af1112d200ade2d2f80e7a5969c48681a9bd9e10c45f44857498e0d2fbd4ff704773368b2dc
-  data.tar.gz: c8066587197f7180780d705c51afb7dfc2df54e9429d989a2e65818fb3fbf9d771a269f753c77469fbdb88427c70cb51a7eff3fe00b1927f5a0d2d4da2971fd3
+  metadata.gz: 687b5e2c1d2cdcf72bf6808c4ffcbf8fcc730fc6efd3ed47383650564be7809bd049f2c192b3e407f6f9bf020514046acd0a8365a6d6141c2844b24fbd4de0b7
+  data.tar.gz: 6dcf31105b3e66e3d570e040457262e832d50e635f9ab1fdedf967ac03531655537561b4d8554fd7e36fe14c0037586e9068fa93b035fedf94e35d197d436a99

data/lib/rggen/verilog.rb

@@ -21,14 +21,12 @@ module RgGen
       plugin.files [
         'verilog/bit_field/type',
         'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
-        'verilog/bit_field/type/reserved',
         'verilog/bit_field/type/ro',
         'verilog/bit_field/type/rof',
         'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
         'verilog/bit_field/type/rw_w1_wo_wo1',
         'verilog/bit_field/type/rwc',
-        'verilog/bit_field/type/rwe',
-        'verilog/bit_field/type/rwl',
+        'verilog/bit_field/type/rwe_rwl',
         'verilog/bit_field/type/rws',
         'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
         'verilog/bit_field/type/w0t_w1t',

data/lib/rggen/verilog/bit_field/type/{rwl.erb → rwe_rwl.erb}

@@ -1,13 +1,13 @@
 rggen_bit_field #(
   .WIDTH                    (<%= width %>),
   .INITIAL_VALUE            (<%= initial_value %>),
-  .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_LOW)
+  .SW_WRITE_ENABLE_POLARITY (<%= control_signal_polarity %>)
 ) u_bit_field (
   .i_clk              (<%= clock %>),
   .i_rst_n            (<%= reset %>),
   .i_sw_valid         (<%= bit_field_valid %>),
   .i_sw_read_mask     (<%= bit_field_read_mask %>),
-  .i_sw_write_enable  (<%= lock_signal %>),
+  .i_sw_write_enable  (<%= control_signal %>),
   .i_sw_write_mask    (<%= bit_field_write_mask %>),
   .i_sw_write_data    (<%= bit_field_write_data %>),
   .o_sw_read_data     (<%= bit_field_read_data %>),

data/lib/rggen/verilog/bit_field/type/rwe_rwl.rb

@@ -0,0 +1,33 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
+  verilog do
+    build do
+      unless bit_field.reference?
+        input :control, {
+          name: "i_#{full_name}_#{enable_or_lock}",
+          width: 1, array_size: array_size
+        }
+      end
+      output :value_out, {
+        name: "o_#{full_name}", width: width, array_size: array_size
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def enable_or_lock
+      { rwe: 'enable', rwl: 'lock' }[bit_field.type]
+    end
+
+    def control_signal_polarity
+      { rwe: '`RGGEN_ACTIVE_HIGH', rwl: '`RGGEN_ACTIVE_LOW' }[bit_field.type]
+    end
+
+    def control_signal
+      reference_bit_field || control[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/factories.rb

@@ -2,7 +2,7 @@
 
 module RgGen
   module Verilog
-    class ComponentFactory < Core::OutputBase::ComponentFactory
+    class ComponentFactory < Core::OutputBase::SourceFileComponentFactory
     end
 
     class FeatureFactory < Core::OutputBase::FeatureFactory

data/lib/rggen/verilog/feature.rb

@@ -12,12 +12,12 @@ module RgGen
         super
       end
 
-      def create_argument(direction, attributes, &block)
+      def create_port(direction, attributes, &block)
         attributes =
           attributes
-            .reject { |key, _| key == :data_type }
-            .merge(array_format: :serialized)
-        super
+            .except(:data_type)
+            .merge(direction: direction, array_format: :serialized)
+        DataObject.new(:argument, attributes, &block)
       end
 
       def create_parameter(parameter_type, attributes, &block)

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.2.0'
+    VERSION = '0.3.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.2.0
+  version: 0.3.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2021-01-20 00:00:00.000000000 Z
+date: 2021-02-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.24.0
+        version: 0.25.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.24.0
+        version: 0.25.0
 - !ruby/object:Gem::Dependency
   name: bundler
   requirement: !ruby/object:Gem::Requirement
@@ -52,8 +52,6 @@ files:
 - lib/rggen/verilog/bit_field/type.rb
 - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb
 - lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb
-- lib/rggen/verilog/bit_field/type/reserved.erb
-- lib/rggen/verilog/bit_field/type/reserved.rb
 - lib/rggen/verilog/bit_field/type/ro.erb
 - lib/rggen/verilog/bit_field/type/ro.rb
 - lib/rggen/verilog/bit_field/type/rof.erb
@@ -64,10 +62,8 @@ files:
 - lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/verilog/bit_field/type/rwc.erb
 - lib/rggen/verilog/bit_field/type/rwc.rb
-- lib/rggen/verilog/bit_field/type/rwe.erb
-- lib/rggen/verilog/bit_field/type/rwe.rb
-- lib/rggen/verilog/bit_field/type/rwl.erb
-- lib/rggen/verilog/bit_field/type/rwl.rb
+- lib/rggen/verilog/bit_field/type/rwe_rwl.erb
+- lib/rggen/verilog/bit_field/type/rwe_rwl.rb
 - lib/rggen/verilog/bit_field/type/rws.erb
 - lib/rggen/verilog/bit_field/type/rws.rb
 - lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
@@ -117,7 +113,7 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: 2.4.0
+      version: '2.5'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
@@ -127,5 +123,5 @@ requirements: []
 rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.2.0
+summary: rggen-verilog-0.3.0
 test_files: []

data/lib/rggen/verilog/bit_field/type/reserved.erb

@@ -1,23 +0,0 @@
-rggen_bit_field #(
-  .WIDTH          (<%= width %>),
-  .SW_READ_ACTION (`RGGEN_READ_NONE),
-  .STORAGE        (0)
-) u_bit_field (
-  .i_clk              (1'b0),
-  .i_rst_n            (1'b0),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
-  .i_sw_write_enable  (1'b0),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
-  .i_sw_write_data    (<%= bit_field_write_data %>),
-  .o_sw_read_data     (<%= bit_field_read_data %>),
-  .o_sw_value         (<%= bit_field_value %>),
-  .i_hw_write_enable  (1'b0),
-  .i_hw_write_data    (<%= fill_0(width) %>),
-  .i_hw_set           (<%= fill_0(width) %>),
-  .i_hw_clear         (<%= fill_0(width) %>),
-  .i_value            (<%= fill_0(width) %>),
-  .i_mask             (<%= fill_0(width) %>),
-  .o_value            (),
-  .o_value_unmasked   ()
-);

data/lib/rggen/verilog/bit_field/type/reserved.rb

@@ -1,7 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :reserved) do
-  verilog do
-    main_code :bit_field, from_template: true
-  end
-end

data/lib/rggen/verilog/bit_field/type/rwe.erb

@@ -1,23 +0,0 @@
-rggen_bit_field #(
-  .WIDTH                    (<%= width %>),
-  .INITIAL_VALUE            (<%= initial_value %>),
-  .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_HIGH)
-) u_bit_field (
-  .i_clk              (<%= clock %>),
-  .i_rst_n            (<%= reset %>),
-  .i_sw_valid         (<%= bit_field_valid %>),
-  .i_sw_read_mask     (<%= bit_field_read_mask %>),
-  .i_sw_write_enable  (<%= enable_signal %>),
-  .i_sw_write_mask    (<%= bit_field_write_mask %>),
-  .i_sw_write_data    (<%= bit_field_write_data %>),
-  .o_sw_read_data     (<%= bit_field_read_data %>),
-  .o_sw_value         (<%= bit_field_value %>),
-  .i_hw_write_enable  (1'b0),
-  .i_hw_write_data    (<%= fill_0(width) %>),
-  .i_hw_set           (<%= fill_0(width) %>),
-  .i_hw_clear         (<%= fill_0(width) %>),
-  .i_value            (<%= fill_0(width) %>),
-  .i_mask             (<%= fill_1(width) %>),
-  .o_value            (<%= value_out[loop_variables] %>),
-  .o_value_unmasked   ()
-);

data/lib/rggen/verilog/bit_field/type/rwe.rb

@@ -1,24 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwe) do
-  verilog do
-    build do
-      unless bit_field.reference?
-        input :enable, {
-          name: "i_#{full_name}_enable", width: 1, array_size: array_size
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def enable_signal
-      reference_bit_field || enable[loop_variables]
-    end
-  end
-end

data/lib/rggen/verilog/bit_field/type/rwl.rb

@@ -1,24 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, :rwl) do
-  verilog do
-    build do
-      unless bit_field.reference?
-        input :lock, {
-          name: "i_#{full_name}_lock", width: 1, array_size: array_size
-        }
-      end
-      output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def lock_signal
-      reference_bit_field || lock[loop_variables]
-    end
-  end
-end