rggen-verilog 0.1.0 → 0.2.0

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Files changed (33) hide show
  1. checksums.yaml +4 -4
  2. data/LICENSE +1 -1
  3. data/README.md +1 -1
  4. data/lib/rggen/verilog.rb +32 -46
  5. data/lib/rggen/verilog/bit_field/type.rb +1 -1
  6. data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb +22 -19
  7. data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb +18 -7
  8. data/lib/rggen/verilog/bit_field/type/reserved.erb +21 -8
  9. data/lib/rggen/verilog/bit_field/type/ro.erb +20 -9
  10. data/lib/rggen/verilog/bit_field/type/rof.erb +20 -9
  11. data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb +22 -17
  12. data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb +18 -7
  13. data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.erb +20 -12
  14. data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb +2 -2
  15. data/lib/rggen/verilog/bit_field/type/rwc.erb +20 -12
  16. data/lib/rggen/verilog/bit_field/type/rwe.erb +21 -13
  17. data/lib/rggen/verilog/bit_field/type/rwl.erb +21 -13
  18. data/lib/rggen/verilog/bit_field/type/rws.erb +18 -12
  19. data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb +24 -0
  20. data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb +36 -0
  21. data/lib/rggen/verilog/bit_field/type/w0t_w1t.erb +21 -13
  22. data/lib/rggen/verilog/bit_field/type/w0t_w1t.rb +5 -2
  23. data/lib/rggen/verilog/bit_field/type/wrc_wrs.erb +20 -11
  24. data/lib/rggen/verilog/bit_field/type/wrc_wrs.rb +9 -0
  25. data/lib/rggen/verilog/register_block/verilog_macros.erb +1 -4
  26. data/lib/rggen/verilog/setup.rb +1 -1
  27. data/lib/rggen/verilog/utility.rb +8 -0
  28. data/lib/rggen/verilog/version.rb +1 -1
  29. metadata +8 -10
  30. data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.erb +0 -15
  31. data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.rb +0 -20
  32. data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.erb +0 -15
  33. data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.rb +0 -20
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data/LICENSE CHANGED
@@ -1,6 +1,6 @@
1
1
  The MIT License (MIT)
2
2
 
3
- Copyright (c) 2020 Taichi Ishitani
3
+ Copyright (c) 2020-2021 Taichi Ishitani
4
4
 
5
5
  Permission is hereby granted, free of charge, to any person obtaining a copy
6
6
  of this software and associated documentation files (the "Software"), to deal
data/README.md CHANGED
@@ -67,7 +67,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
67
67
 
68
68
  ## Copyright & License
69
69
 
70
- Copyright © 2020 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
70
+ Copyright © 2020-2021 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
71
71
 
72
72
  ## Code of Conduct
73
73
 
data/lib/rggen/verilog.rb CHANGED
@@ -10,55 +10,41 @@ require_relative 'verilog/factories'
10
10
 
11
11
  module RgGen
12
12
  module Verilog
13
- PLUGIN_NAME = :'rggen-verilog'
13
+ extend Core::Plugin
14
14
 
15
- FEATURES = [
16
- 'verilog/bit_field/type',
17
- 'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
18
- 'verilog/bit_field/type/reserved',
19
- 'verilog/bit_field/type/ro',
20
- 'verilog/bit_field/type/rof',
21
- 'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
22
- 'verilog/bit_field/type/rw_w1_wo_wo1',
23
- 'verilog/bit_field/type/rwc',
24
- 'verilog/bit_field/type/rwe',
25
- 'verilog/bit_field/type/rwl',
26
- 'verilog/bit_field/type/rws',
27
- 'verilog/bit_field/type/w0crs_w1crs_wcrs',
28
- 'verilog/bit_field/type/w0src_w1src_wsrc',
29
- 'verilog/bit_field/type/w0t_w1t',
30
- 'verilog/bit_field/type/w0trg_w1trg',
31
- 'verilog/bit_field/type/wrc_wrs',
32
- 'verilog/bit_field/verilog_top',
33
- 'verilog/register/type',
34
- 'verilog/register/type/external',
35
- 'verilog/register/type/indirect',
36
- 'verilog/register/verilog_top',
37
- 'verilog/register_block/protocol',
38
- 'verilog/register_block/protocol/apb',
39
- 'verilog/register_block/protocol/axi4lite',
40
- 'verilog/register_block/verilog_top',
41
- 'verilog/register_file/verilog_top'
42
- ].freeze
43
-
44
- def self.register_component(builder)
45
- builder.output_component_registry(:verilog) do
46
- register_component [
47
- :root, :register_block, :register_file, :register, :bit_field
48
- ] do |layer|
49
- component Component, ComponentFactory
50
- feature Feature, FeatureFactory if layer != :root
51
- end
15
+ setup_plugin :'rggen-verilog' do |plugin|
16
+ plugin.register_component :verilog do
17
+ component Component, ComponentFactory
18
+ feature Feature, FeatureFactory
52
19
  end
53
- end
54
-
55
- def self.load_features
56
- FEATURES.each { |feature| require_relative feature }
57
- end
58
20
 
59
- def self.default_setup(builder)
60
- register_component(builder)
61
- load_features
21
+ plugin.files [
22
+ 'verilog/bit_field/type',
23
+ 'verilog/bit_field/type/rc_w0c_w1c_wc_woc',
24
+ 'verilog/bit_field/type/reserved',
25
+ 'verilog/bit_field/type/ro',
26
+ 'verilog/bit_field/type/rof',
27
+ 'verilog/bit_field/type/rs_w0s_w1s_ws_wos',
28
+ 'verilog/bit_field/type/rw_w1_wo_wo1',
29
+ 'verilog/bit_field/type/rwc',
30
+ 'verilog/bit_field/type/rwe',
31
+ 'verilog/bit_field/type/rwl',
32
+ 'verilog/bit_field/type/rws',
33
+ 'verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
34
+ 'verilog/bit_field/type/w0t_w1t',
35
+ 'verilog/bit_field/type/w0trg_w1trg',
36
+ 'verilog/bit_field/type/wrc_wrs',
37
+ 'verilog/bit_field/verilog_top',
38
+ 'verilog/register/type',
39
+ 'verilog/register/type/external',
40
+ 'verilog/register/type/indirect',
41
+ 'verilog/register/verilog_top',
42
+ 'verilog/register_block/protocol',
43
+ 'verilog/register_block/protocol/apb',
44
+ 'verilog/register_block/protocol/axi4lite',
45
+ 'verilog/register_block/verilog_top',
46
+ 'verilog/register_file/verilog_top'
47
+ ]
62
48
  end
63
49
  end
64
50
  end
data/lib/rggen/verilog/bit_field/type.rb CHANGED
@@ -59,7 +59,7 @@ RgGen.define_list_feature(:bit_field, :type) do
59
59
  end
60
60
 
61
61
  def mask
62
- reference_bit_field || hex(2**width - 1, width)
62
+ reference_bit_field || fill_1(width)
63
63
  end
64
64
 
65
65
  def reference_bit_field
data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.erb CHANGED
@@ -1,21 +1,24 @@
1
- <%= module_name %> #(
2
- <% if bit_field.type != :rc %>
3
- .CLEAR_VALUE (<%= clear_value %>),
4
- .WRITE_ONLY (<%= write_only %>),
5
- <% end %>
6
- .WIDTH (<%= width %>),
7
- .INITIAL_VALUE (<%= initial_value %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_READ_ACTION (<%= read_action %>),
5
+ .SW_WRITE_ACTION (<%= write_action %>)
8
6
  ) u_bit_field (
9
- .i_clk (<%= clock %>),
10
- .i_rst_n (<%= reset%>),
11
- .i_bit_field_valid (<%= bit_field_valid %>),
12
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
13
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
14
- .i_bit_field_write_data (<%= bit_field_write_data %>),
15
- .o_bit_field_read_data (<%= bit_field_read_data %>),
16
- .o_bit_field_value (<%= bit_field_value %>),
17
- .i_set (<%= set[loop_variables] %>),
18
- .i_mask (<%= mask %>),
19
- .o_value (<%= value_out[loop_variables] %>),
20
- .o_value_unmasked (<%= value_out_unmasked %>)
7
+ .i_clk (<%= clock %>),
8
+ .i_rst_n (<%= reset %>),
9
+ .i_sw_valid (<%= bit_field_valid %>),
10
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
11
+ .i_sw_write_enable (<%= write_enable %>),
12
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
13
+ .i_sw_write_data (<%= bit_field_write_data %>),
14
+ .o_sw_read_data (<%= bit_field_read_data %>),
15
+ .o_sw_value (<%= bit_field_value %>),
16
+ .i_hw_write_enable (1'b0),
17
+ .i_hw_write_data (<%= fill_0(width) %>),
18
+ .i_hw_set (<%= set[loop_variables] %>),
19
+ .i_hw_clear (<%= fill_0(width) %>),
20
+ .i_value (<%= fill_0(width) %>),
21
+ .i_mask (<%= mask %>),
22
+ .o_value (<%= value_out[loop_variables] %>),
23
+ .o_value_unmasked (<%= value_out_unmasked %>)
21
24
  );
data/lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb CHANGED
@@ -20,17 +20,28 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
20
20
 
21
21
  private
22
22
 
23
- def module_name
24
- bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
23
+ def read_action
24
+ {
25
+ rc: '`RGGEN_READ_CLEAR',
26
+ w0c: '`RGGEN_READ_DEFAULT',
27
+ w1c: '`RGGEN_READ_DEFAULT',
28
+ wc: '`RGGEN_READ_DEFAULT',
29
+ woc: '`RGGEN_READ_NONE'
30
+ }[bit_field.type]
25
31
  end
26
32
 
27
- def clear_value
28
- value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
29
- bin(value, 2)
33
+ def write_action
34
+ {
35
+ rc: '`RGGEN_WRITE_NONE',
36
+ w0c: '`RGGEN_WRITE_0_CLEAR',
37
+ w1c: '`RGGEN_WRITE_1_CLEAR',
38
+ wc: '`RGGEN_WRITE_CLEAR',
39
+ woc: '`RGGEN_WRITE_CLEAR'
40
+ }[bit_field.type]
30
41
  end
31
42
 
32
- def write_only
33
- bit_field.write_only? && 1 || 0
43
+ def write_enable
44
+ bit_field.writable? && bin(1, 1) || bin(0, 1)
34
45
  end
35
46
 
36
47
  def value_out_unmasked
data/lib/rggen/verilog/bit_field/type/reserved.erb CHANGED
@@ -1,10 +1,23 @@
1
- rggen_bit_field_reserved #(
2
- .WIDTH (<%= width %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .SW_READ_ACTION (`RGGEN_READ_NONE),
4
+ .STORAGE (0)
3
5
  ) u_bit_field (
4
- .i_bit_field_valid (<%= bit_field_valid %>),
5
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
6
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
7
- .i_bit_field_write_data (<%= bit_field_write_data %>),
8
- .o_bit_field_read_data (<%= bit_field_read_data %>),
9
- .o_bit_field_value (<%= bit_field_value %>)
6
+ .i_clk (1'b0),
7
+ .i_rst_n (1'b0),
8
+ .i_sw_valid (<%= bit_field_valid %>),
9
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
10
+ .i_sw_write_enable (1'b0),
11
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
12
+ .i_sw_write_data (<%= bit_field_write_data %>),
13
+ .o_sw_read_data (<%= bit_field_read_data %>),
14
+ .o_sw_value (<%= bit_field_value %>),
15
+ .i_hw_write_enable (1'b0),
16
+ .i_hw_write_data (<%= fill_0(width) %>),
17
+ .i_hw_set (<%= fill_0(width) %>),
18
+ .i_hw_clear (<%= fill_0(width) %>),
19
+ .i_value (<%= fill_0(width) %>),
20
+ .i_mask (<%= fill_0(width) %>),
21
+ .o_value (),
22
+ .o_value_unmasked ()
10
23
  );
data/lib/rggen/verilog/bit_field/type/ro.erb CHANGED
@@ -1,11 +1,22 @@
1
- rggen_bit_field_ro #(
2
- .WIDTH (<%= width %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .STORAGE (0)
3
4
  ) u_bit_field (
4
- .i_bit_field_valid (<%= bit_field_valid %>),
5
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
6
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
7
- .i_bit_field_write_data (<%= bit_field_write_data %>),
8
- .o_bit_field_read_data (<%= bit_field_read_data %>),
9
- .o_bit_field_value (<%= bit_field_value %>),
10
- .i_value (<%= reference_or_value_in %>)
5
+ .i_clk (1'b0),
6
+ .i_rst_n (1'b0),
7
+ .i_sw_valid (<%= bit_field_valid %>),
8
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
9
+ .i_sw_write_enable (1'b0),
10
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
11
+ .i_sw_write_data (<%= bit_field_write_data %>),
12
+ .o_sw_read_data (<%= bit_field_read_data %>),
13
+ .o_sw_value (<%= bit_field_value %>),
14
+ .i_hw_write_enable (1'b0),
15
+ .i_hw_write_data (<%= fill_0(width) %>),
16
+ .i_hw_set (<%= fill_0(width) %>),
17
+ .i_hw_clear (<%= fill_0(width) %>),
18
+ .i_value (<%= reference_or_value_in %>),
19
+ .i_mask (<%= fill_1(width) %>),
20
+ .o_value (),
21
+ .o_value_unmasked ()
11
22
  );
data/lib/rggen/verilog/bit_field/type/rof.erb CHANGED
@@ -1,11 +1,22 @@
1
- rggen_bit_field_ro #(
2
- .WIDTH (<%= width %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .STORAGE (0)
3
4
  ) u_bit_field (
4
- .i_bit_field_valid (<%= bit_field_valid %>),
5
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
6
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
7
- .i_bit_field_write_data (<%= bit_field_write_data %>),
8
- .o_bit_field_read_data (<%= bit_field_read_data %>),
9
- .o_bit_field_value (<%= bit_field_value %>),
10
- .i_value (<%= initial_value %>)
5
+ .i_clk (1'b0),
6
+ .i_rst_n (1'b0),
7
+ .i_sw_valid (<%= bit_field_valid %>),
8
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
9
+ .i_sw_write_enable (1'b0),
10
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
11
+ .i_sw_write_data (<%= bit_field_write_data %>),
12
+ .o_sw_read_data (<%= bit_field_read_data %>),
13
+ .o_sw_value (<%= bit_field_value %>),
14
+ .i_hw_write_enable (1'b0),
15
+ .i_hw_write_data (<%= fill_0(width) %>),
16
+ .i_hw_set (<%= fill_0(width) %>),
17
+ .i_hw_clear (<%= fill_0(width) %>),
18
+ .i_value (<%= initial_value %>),
19
+ .i_mask (<%= fill_1(width) %>),
20
+ .o_value (),
21
+ .o_value_unmasked ()
11
22
  );
data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.erb CHANGED
@@ -1,19 +1,24 @@
1
- <%= module_name %> #(
2
- <% if bit_field.type != :rs %>
3
- .SET_VALUE (<%= set_value %>),
4
- .WRITE_ONLY (<%= write_only %>),
5
- <% end %>
6
- .WIDTH (<%= width %>),
7
- .INITIAL_VALUE (<%= initial_value %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_READ_ACTION (<%= read_action %>),
5
+ .SW_WRITE_ACTION (<%= write_action %>)
8
6
  ) u_bit_field (
9
- .i_clk (<%= clock %>),
10
- .i_rst_n (<%= reset %>),
11
- .i_bit_field_valid (<%= bit_field_valid %>),
12
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
13
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
14
- .i_bit_field_write_data (<%= bit_field_write_data %>),
15
- .o_bit_field_read_data (<%= bit_field_read_data %>),
16
- .o_bit_field_value (<%= bit_field_value %>),
17
- .i_clear (<%= clear[loop_variables] %>),
18
- .o_value (<%= value_out[loop_variables] %>)
7
+ .i_clk (<%= clock %>),
8
+ .i_rst_n (<%= reset %>),
9
+ .i_sw_valid (<%= bit_field_valid %>),
10
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
11
+ .i_sw_write_enable (<%= write_enable %>),
12
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
13
+ .i_sw_write_data (<%= bit_field_write_data %>),
14
+ .o_sw_read_data (<%= bit_field_read_data %>),
15
+ .o_sw_value (<%= bit_field_value %>),
16
+ .i_hw_write_enable (1'b0),
17
+ .i_hw_write_data (<%= fill_0(width) %>),
18
+ .i_hw_set (<%= fill_0(width) %>),
19
+ .i_hw_clear (<%= clear[loop_variables] %>),
20
+ .i_value (<%= fill_0(width) %>),
21
+ .i_mask (<%= mask %>),
22
+ .o_value (<%= value_out[loop_variables] %>),
23
+ .o_value_unmasked ()
19
24
  );
data/lib/rggen/verilog/bit_field/type/rs_w0s_w1s_ws_wos.rb CHANGED
@@ -15,17 +15,28 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
15
15
 
16
16
  private
17
17
 
18
- def module_name
19
- bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
18
+ def read_action
19
+ {
20
+ rs: '`RGGEN_READ_SET',
21
+ w0s: '`RGGEN_READ_DEFAULT',
22
+ w1s: '`RGGEN_READ_DEFAULT',
23
+ ws: '`RGGEN_READ_DEFAULT',
24
+ wos: '`RGGEN_READ_NONE'
25
+ }[bit_field.type]
20
26
  end
21
27
 
22
- def set_value
23
- value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
24
- bin(value, 2)
28
+ def write_action
29
+ {
30
+ rs: '`RGGEN_WRITE_NONE',
31
+ w0s: '`RGGEN_WRITE_0_SET',
32
+ w1s: '`RGGEN_WRITE_1_SET',
33
+ ws: '`RGGEN_WRITE_SET',
34
+ wos: '`RGGEN_WRITE_SET'
35
+ }[bit_field.type]
25
36
  end
26
37
 
27
- def write_only
28
- bit_field.write_only? && 1 || 0
38
+ def write_enable
39
+ bit_field.writable? && bin(1, 1) || bin(0, 1)
29
40
  end
30
41
  end
31
42
  end
data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.erb CHANGED
@@ -1,16 +1,24 @@
1
- rggen_bit_field_rw_wo #(
1
+ rggen_bit_field #(
2
2
  .WIDTH (<%= width %>),
3
3
  .INITIAL_VALUE (<%= initial_value %>),
4
- .WRITE_ONLY (<%= write_only %>),
5
- .WRITE_ONCE (<%= write_once %>)
4
+ .SW_READ_ACTION (<%= read_action %>),
5
+ .SW_WRITE_ONCE (<%= write_once %>)
6
6
  ) u_bit_field (
7
- .i_clk (<%= clock %>),
8
- .i_rst_n (<%= reset %>),
9
- .i_bit_field_valid (<%= bit_field_valid %>),
10
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
11
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
12
- .i_bit_field_write_data (<%= bit_field_write_data %>),
13
- .o_bit_field_read_data (<%= bit_field_read_data %>),
14
- .o_bit_field_value (<%= bit_field_value %>),
15
- .o_value (<%= value_out[loop_variables] %>)
7
+ .i_clk (<%= clock %>),
8
+ .i_rst_n (<%= reset %>),
9
+ .i_sw_valid (<%= bit_field_valid %>),
10
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
11
+ .i_sw_write_enable (1'b1),
12
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
13
+ .i_sw_write_data (<%= bit_field_write_data %>),
14
+ .o_sw_read_data (<%= bit_field_read_data %>),
15
+ .o_sw_value (<%= bit_field_value %>),
16
+ .i_hw_write_enable (1'b0),
17
+ .i_hw_write_data (<%= fill_0(width) %>),
18
+ .i_hw_set (<%= fill_0(width) %>),
19
+ .i_hw_clear (<%= fill_0(width) %>),
20
+ .i_value (<%= fill_0(width) %>),
21
+ .i_mask (<%= fill_1(width) %>),
22
+ .o_value (<%= value_out[loop_variables] %>),
23
+ .o_value_unmasked ()
16
24
  );
data/lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb CHANGED
@@ -12,8 +12,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
12
12
 
13
13
  private
14
14
 
15
- def write_only
16
- bit_field.write_only? && 1 || 0
15
+ def read_action
16
+ bit_field.readable? && '`RGGEN_READ_DEFAULT' || '`RGGEN_READ_NONE'
17
17
  end
18
18
 
19
19
  def write_once
data/lib/rggen/verilog/bit_field/type/rwc.erb CHANGED
@@ -1,15 +1,23 @@
1
- rggen_bit_field_rwc #(
1
+ rggen_bit_field #(
2
2
  .WIDTH (<%= width %>),
3
- .INITIAL_VALUE (<%= initial_value %>)
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .HW_CLEAR_WIDTH (1)
4
5
  ) u_bit_field (
5
- .i_clk (<%= clock %>),
6
- .i_rst_n (<%= reset %>),
7
- .i_bit_field_valid (<%= bit_field_valid %>),
8
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
9
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
10
- .i_bit_field_write_data (<%= bit_field_write_data %>),
11
- .o_bit_field_read_data (<%= bit_field_read_data %>),
12
- .o_bit_field_value (<%= bit_field_value %>),
13
- .i_clear (<%= clear_signal %>),
14
- .o_value (<%= value_out[loop_variables] %>)
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .i_sw_valid (<%= bit_field_valid %>),
9
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
10
+ .i_sw_write_enable (1'b1),
11
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
12
+ .i_sw_write_data (<%= bit_field_write_data %>),
13
+ .o_sw_read_data (<%= bit_field_read_data %>),
14
+ .o_sw_value (<%= bit_field_value %>),
15
+ .i_hw_write_enable (1'b0),
16
+ .i_hw_write_data (<%= fill_0(width) %>),
17
+ .i_hw_set (<%= fill_0(width) %>),
18
+ .i_hw_clear (<%= clear_signal %>),
19
+ .i_value (<%= fill_0(width) %>),
20
+ .i_mask (<%= fill_1(width) %>),
21
+ .o_value (<%= value_out[loop_variables] %>),
22
+ .o_value_unmasked ()
15
23
  );
data/lib/rggen/verilog/bit_field/type/rwe.erb CHANGED
@@ -1,15 +1,23 @@
1
- rggen_bit_field_rwe #(
2
- .WIDTH (<%= width %>),
3
- .INITIAL_VALUE (<%= initial_value %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_HIGH)
4
5
  ) u_bit_field (
5
- .i_clk (<%= clock %>),
6
- .i_rst_n (<%= reset %>),
7
- .i_bit_field_valid (<%= bit_field_valid %>),
8
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
9
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
10
- .i_bit_field_write_data (<%= bit_field_write_data %>),
11
- .o_bit_field_read_data (<%= bit_field_read_data %>),
12
- .o_bit_field_value (<%= bit_field_value %>),
13
- .i_enable (<%= enable_signal %>),
14
- .o_value (<%= value_out[loop_variables] %>)
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .i_sw_valid (<%= bit_field_valid %>),
9
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
10
+ .i_sw_write_enable (<%= enable_signal %>),
11
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
12
+ .i_sw_write_data (<%= bit_field_write_data %>),
13
+ .o_sw_read_data (<%= bit_field_read_data %>),
14
+ .o_sw_value (<%= bit_field_value %>),
15
+ .i_hw_write_enable (1'b0),
16
+ .i_hw_write_data (<%= fill_0(width) %>),
17
+ .i_hw_set (<%= fill_0(width) %>),
18
+ .i_hw_clear (<%= fill_0(width) %>),
19
+ .i_value (<%= fill_0(width) %>),
20
+ .i_mask (<%= fill_1(width) %>),
21
+ .o_value (<%= value_out[loop_variables] %>),
22
+ .o_value_unmasked ()
15
23
  );
data/lib/rggen/verilog/bit_field/type/rwl.erb CHANGED
@@ -1,15 +1,23 @@
1
- rggen_bit_field_rwl #(
2
- .WIDTH (<%= width %>),
3
- .INITIAL_VALUE (<%= initial_value %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_WRITE_ENABLE_POLARITY (`RGGEN_ACTIVE_LOW)
4
5
  ) u_bit_field (
5
- .i_clk (<%= clock %>),
6
- .i_rst_n (<%= reset %>),
7
- .i_bit_field_valid (<%= bit_field_valid %>),
8
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
9
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
10
- .i_bit_field_write_data (<%= bit_field_write_data %>),
11
- .o_bit_field_read_data (<%= bit_field_read_data %>),
12
- .o_bit_field_value (<%= bit_field_value %>),
13
- .i_lock (<%= lock_signal %>),
14
- .o_value (<%= value_out[loop_variables] %>)
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .i_sw_valid (<%= bit_field_valid %>),
9
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
10
+ .i_sw_write_enable (<%= lock_signal %>),
11
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
12
+ .i_sw_write_data (<%= bit_field_write_data %>),
13
+ .o_sw_read_data (<%= bit_field_read_data %>),
14
+ .o_sw_value (<%= bit_field_value %>),
15
+ .i_hw_write_enable (1'b0),
16
+ .i_hw_write_data (<%= fill_0(width) %>),
17
+ .i_hw_set (<%= fill_0(width) %>),
18
+ .i_hw_clear (<%= fill_0(width) %>),
19
+ .i_value (<%= fill_0(width) %>),
20
+ .i_mask (<%= fill_1(width) %>),
21
+ .o_value (<%= value_out[loop_variables] %>),
22
+ .o_value_unmasked ()
15
23
  );
data/lib/rggen/verilog/bit_field/type/rws.erb CHANGED
@@ -1,16 +1,22 @@
1
- rggen_bit_field_rws #(
1
+ rggen_bit_field #(
2
2
  .WIDTH (<%= width %>),
3
3
  .INITIAL_VALUE (<%= initial_value %>)
4
4
  ) u_bit_field (
5
- .i_clk (<%= clock %>),
6
- .i_rst_n (<%= reset %>),
7
- .i_bit_field_valid (<%= bit_field_valid %>),
8
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
9
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
10
- .i_bit_field_write_data (<%= bit_field_write_data %>),
11
- .o_bit_field_read_data (<%= bit_field_read_data %>),
12
- .o_bit_field_value (<%= bit_field_value %>),
13
- .i_set (<%= set_signal %>),
14
- .i_value (<%= value_in[loop_variables] %>),
15
- .o_value (<%= value_out[loop_variables] %>)
5
+ .i_clk (<%= clock %>),
6
+ .i_rst_n (<%= reset %>),
7
+ .i_sw_valid (<%= bit_field_valid %>),
8
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
9
+ .i_sw_write_enable (1'b1),
10
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
11
+ .i_sw_write_data (<%= bit_field_write_data %>),
12
+ .o_sw_read_data (<%= bit_field_read_data %>),
13
+ .o_sw_value (<%= bit_field_value %>),
14
+ .i_hw_write_enable (<%= set_signal %>),
15
+ .i_hw_write_data (<%= value_in[loop_variables] %>),
16
+ .i_hw_set (<%= fill_0(width) %>),
17
+ .i_hw_clear (<%= fill_0(width) %>),
18
+ .i_value (<%= fill_0(width) %>),
19
+ .i_mask (<%= fill_1(width) %>),
20
+ .o_value (<%= value_out[loop_variables] %>),
21
+ .o_value_unmasked ()
16
22
  );
data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb ADDED
@@ -0,0 +1,24 @@
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_READ_ACTION (<%= read_action %>),
5
+ .SW_WRITE_ACTION (<%= write_action %>)
6
+ ) u_bit_field (
7
+ .i_clk (<%= clock %>),
8
+ .i_rst_n (<%= reset %>),
9
+ .i_sw_valid (<%= bit_field_valid %>),
10
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
11
+ .i_sw_write_enable (1'b1),
12
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
13
+ .i_sw_write_data (<%= bit_field_write_data %>),
14
+ .o_sw_read_data (<%= bit_field_read_data %>),
15
+ .o_sw_value (<%= bit_field_value %>),
16
+ .i_hw_write_enable (1'b0),
17
+ .i_hw_write_data (<%= fill_0(width) %>),
18
+ .i_hw_set (<%= fill_0(width) %>),
19
+ .i_hw_clear (<%= fill_0(width) %>),
20
+ .i_value (<%= fill_0(width) %>),
21
+ .i_mask (<%= fill_1(width) %>),
22
+ .o_value (<%= value_out[loop_variables] %>),
23
+ .o_value_unmasked ()
24
+ );
data/lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb ADDED
@@ -0,0 +1,36 @@
1
+ # frozen_string_literal: true
2
+
3
+ RgGen.define_list_item_feature(
4
+ :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
5
+ ) do
6
+ verilog do
7
+ build do
8
+ output :value_out, {
9
+ name: "o_#{full_name}", width: width, array_size: array_size
10
+ }
11
+ end
12
+
13
+ main_code :bit_field, from_template: true
14
+
15
+ private
16
+
17
+ def read_action
18
+ read_set? && '`RGGEN_READ_SET' || '`RGGEN_READ_CLEAR'
19
+ end
20
+
21
+ def read_set?
22
+ [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
23
+ end
24
+
25
+ def write_action
26
+ {
27
+ w0crs: '`RGGEN_WRITE_0_CLEAR',
28
+ w0src: '`RGGEN_WRITE_0_SET',
29
+ w1crs: '`RGGEN_WRITE_1_CLEAR',
30
+ w1src: '`RGGEN_WRITE_1_SET',
31
+ wcrs: '`RGGEN_WRITE_CLEAR',
32
+ wsrc: '`RGGEN_WRITE_SET'
33
+ }[bit_field.type]
34
+ end
35
+ end
36
+ end
data/lib/rggen/verilog/bit_field/type/w0t_w1t.erb CHANGED
@@ -1,15 +1,23 @@
1
- rggen_bit_field_w01t #(
2
- .TOGGLE_VALUE (<%= toggle_value %>),
3
- .WIDTH (<%= width %>),
4
- .INITIAL_VALUE (<%= initial_value %>)
1
+ rggen_bit_field #(
2
+ .WIDTH (<%= width %>),
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_WRITE_ACTION (<%= write_action %>)
5
5
  ) u_bit_field (
6
- .i_clk (<%= clock %>),
7
- .i_rst_n (<%= reset %>),
8
- .i_bit_field_valid (<%= bit_field_valid %>),
9
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
10
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
11
- .i_bit_field_write_data (<%= bit_field_write_data %>),
12
- .o_bit_field_read_data (<%= bit_field_read_data %>),
13
- .o_bit_field_value (<%= bit_field_value %>),
14
- .o_value (<%= value_out[loop_variables] %>)
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .i_sw_valid (<%= bit_field_valid %>),
9
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
10
+ .i_sw_write_enable (1'b1),
11
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
12
+ .i_sw_write_data (<%= bit_field_write_data %>),
13
+ .o_sw_read_data (<%= bit_field_read_data %>),
14
+ .o_sw_value (<%= bit_field_value %>),
15
+ .i_hw_write_enable (1'b0),
16
+ .i_hw_write_data (<%= fill_0(width) %>),
17
+ .i_hw_set (<%= fill_0(width) %>),
18
+ .i_hw_clear (<%= fill_0(width) %>),
19
+ .i_value (<%= fill_0(width) %>),
20
+ .i_mask (<%= fill_1(width) %>),
21
+ .o_value (<%= value_out[loop_variables] %>),
22
+ .o_value_unmasked ()
15
23
  );
data/lib/rggen/verilog/bit_field/type/w0t_w1t.rb CHANGED
@@ -12,8 +12,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
12
12
 
13
13
  private
14
14
 
15
- def toggle_value
16
- bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
15
+ def write_action
16
+ {
17
+ w0t: '`RGGEN_WRITE_0_TOGGLE',
18
+ w1t: '`RGGEN_WRITE_1_TOGGLE'
19
+ }[bit_field.type]
17
20
  end
18
21
  end
19
22
  end
data/lib/rggen/verilog/bit_field/type/wrc_wrs.erb CHANGED
@@ -1,14 +1,23 @@
1
- rggen_bit_field_<%= bit_field.type %> #(
1
+ rggen_bit_field #(
2
2
  .WIDTH (<%= width %>),
3
- .INITIAL_VALUE (<%= initial_value %>)
3
+ .INITIAL_VALUE (<%= initial_value %>),
4
+ .SW_READ_ACTION (<%= read_action %>)
4
5
  ) u_bit_field (
5
- .i_clk (<%= clock %>),
6
- .i_rst_n (<%= reset %>),
7
- .i_bit_field_valid (<%= bit_field_valid %>),
8
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
9
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
10
- .i_bit_field_write_data (<%= bit_field_write_data %>),
11
- .o_bit_field_read_data (<%= bit_field_read_data %>),
12
- .o_bit_field_value (<%= bit_field_value %>),
13
- .o_value (<%= value_out[loop_variables] %>)
6
+ .i_clk (<%= clock %>),
7
+ .i_rst_n (<%= reset %>),
8
+ .i_sw_valid (<%= bit_field_valid %>),
9
+ .i_sw_read_mask (<%= bit_field_read_mask %>),
10
+ .i_sw_write_enable (1'b1),
11
+ .i_sw_write_mask (<%= bit_field_write_mask %>),
12
+ .i_sw_write_data (<%= bit_field_write_data %>),
13
+ .o_sw_read_data (<%= bit_field_read_data %>),
14
+ .o_sw_value (<%= bit_field_value %>),
15
+ .i_hw_write_enable (1'b0),
16
+ .i_hw_write_data (<%= fill_0(width) %>),
17
+ .i_hw_set (<%= fill_0(width) %>),
18
+ .i_hw_clear (<%= fill_0(width) %>),
19
+ .i_value (<%= fill_0(width) %>),
20
+ .i_mask (<%= fill_1(width) %>),
21
+ .o_value (<%= value_out[loop_variables] %>),
22
+ .o_value_unmasked ()
14
23
  );
data/lib/rggen/verilog/bit_field/type/wrc_wrs.rb CHANGED
@@ -9,5 +9,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
9
9
  end
10
10
 
11
11
  main_code :bit_field, from_template: true
12
+
13
+ private
14
+
15
+ def read_action
16
+ {
17
+ wrc: '`RGGEN_READ_CLEAR',
18
+ wrs: '`RGGEN_READ_SET'
19
+ }[bit_field.type]
20
+ end
12
21
  end
13
22
  end
data/lib/rggen/verilog/register_block/verilog_macros.erb CHANGED
@@ -1,4 +1 @@
1
- `ifndef rggen_slice
2
- `define rggen_slice(EXPRESSION, WIDTH, INDEX) \
3
- (((EXPRESSION) >> ((WIDTH) * (INDEX))) & {(WIDTH){1'b1}})
4
- `endif
1
+ `include "rggen_rtl_macros.vh"
data/lib/rggen/verilog/setup.rb CHANGED
@@ -3,7 +3,7 @@
3
3
  require 'rggen/verilog'
4
4
  require 'rggen/systemverilog/rtl/setup'
5
5
 
6
- RgGen.setup RgGen::Verilog do |builder|
6
+ RgGen.register_plugin RgGen::Verilog do |builder|
7
7
  builder.enable :register_block, [:verilog_top]
8
8
  builder.enable :register_file, [:verilog_top]
9
9
  builder.enable :register, [:verilog_top]
data/lib/rggen/verilog/utility.rb CHANGED
@@ -8,6 +8,14 @@ module RgGen
8
8
  def local_scope(name, attributes = {}, &block)
9
9
  LocalScope.new(attributes.merge(name: name), &block).to_code
10
10
  end
11
+
12
+ def fill_0(width)
13
+ "{#{width}{1'b0}}"
14
+ end
15
+
16
+ def fill_1(width)
17
+ "{#{width}{1'b1}}"
18
+ end
11
19
  end
12
20
  end
13
21
  end
data/lib/rggen/verilog/version.rb CHANGED
@@ -2,6 +2,6 @@
2
2
 
3
3
  module RgGen
4
4
  module Verilog
5
- VERSION = '0.1.0'
5
+ VERSION = '0.2.0'
6
6
  end
7
7
  end
metadata CHANGED
@@ -1,14 +1,14 @@
1
1
  --- !ruby/object:Gem::Specification
2
2
  name: rggen-verilog
3
3
  version: !ruby/object:Gem::Version
4
- version: 0.1.0
4
+ version: 0.2.0
5
5
  platform: ruby
6
6
  authors:
7
7
  - Taichi Ishitani
8
8
  autorequire:
9
9
  bindir: bin
10
10
  cert_chain: []
11
- date: 2020-10-24 00:00:00.000000000 Z
11
+ date: 2021-01-20 00:00:00.000000000 Z
12
12
  dependencies:
13
13
  - !ruby/object:Gem::Dependency
14
14
  name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
16
16
  requirements:
17
17
  - - ">="
18
18
  - !ruby/object:Gem::Version
19
- version: 0.23.1
19
+ version: 0.24.0
20
20
  type: :runtime
21
21
  prerelease: false
22
22
  version_requirements: !ruby/object:Gem::Requirement
23
23
  requirements:
24
24
  - - ">="
25
25
  - !ruby/object:Gem::Version
26
- version: 0.23.1
26
+ version: 0.24.0
27
27
  - !ruby/object:Gem::Dependency
28
28
  name: bundler
29
29
  requirement: !ruby/object:Gem::Requirement
@@ -70,10 +70,8 @@ files:
70
70
  - lib/rggen/verilog/bit_field/type/rwl.rb
71
71
  - lib/rggen/verilog/bit_field/type/rws.erb
72
72
  - lib/rggen/verilog/bit_field/type/rws.rb
73
- - lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.erb
74
- - lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.rb
75
- - lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.erb
76
- - lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.rb
73
+ - lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
74
+ - lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
77
75
  - lib/rggen/verilog/bit_field/type/w0t_w1t.erb
78
76
  - lib/rggen/verilog/bit_field/type/w0t_w1t.rb
79
77
  - lib/rggen/verilog/bit_field/type/w0trg_w1trg.erb
@@ -126,8 +124,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
126
124
  - !ruby/object:Gem::Version
127
125
  version: '0'
128
126
  requirements: []
129
- rubygems_version: 3.1.2
127
+ rubygems_version: 3.2.3
130
128
  signing_key:
131
129
  specification_version: 4
132
- summary: rggen-verilog-0.1.0
130
+ summary: rggen-verilog-0.2.0
133
131
  test_files: []
data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.erb DELETED
@@ -1,15 +0,0 @@
1
- rggen_bit_field_w01crs_wcrs #(
2
- .CLEAR_VALUE (<%= clear_value %>),
3
- .WIDTH (<%= width %>),
4
- .INITIAL_VALUE (<%= initial_value %>)
5
- ) u_bit_field (
6
- .i_clk (<%= clock %>),
7
- .i_rst_n (<%= reset %>),
8
- .i_bit_field_valid (<%= bit_field_valid %>),
9
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
10
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
11
- .i_bit_field_write_data (<%= bit_field_write_data %>),
12
- .o_bit_field_read_data (<%= bit_field_read_data %>),
13
- .o_bit_field_value (<%= bit_field_value %>),
14
- .o_value (<%= value_out[loop_variables] %>)
15
- );
data/lib/rggen/verilog/bit_field/type/w0crs_w1crs_wcrs.rb DELETED
@@ -1,20 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
4
- verilog do
5
- build do
6
- output :value_out, {
7
- name: "o_#{full_name}", width: width, array_size: array_size
8
- }
9
- end
10
-
11
- main_code :bit_field, from_template: true
12
-
13
- private
14
-
15
- def clear_value
16
- value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
17
- bin(value, 2)
18
- end
19
- end
20
- end
data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.erb DELETED
@@ -1,15 +0,0 @@
1
- rggen_bit_field_w01src_wsrc #(
2
- .SET_VALUE (<%= set_value %>),
3
- .WIDTH (<%= width %>),
4
- .INITIAL_VALUE (<%= initial_value %>)
5
- ) u_bit_field (
6
- .i_clk (<%= clock %>),
7
- .i_rst_n (<%= reset %>),
8
- .i_bit_field_valid (<%= bit_field_valid %>),
9
- .i_bit_field_read_mask (<%= bit_field_read_mask %>),
10
- .i_bit_field_write_mask (<%= bit_field_write_mask %>),
11
- .i_bit_field_write_data (<%= bit_field_write_data %>),
12
- .o_bit_field_read_data (<%= bit_field_read_data %>),
13
- .o_bit_field_value (<%= bit_field_value %>),
14
- .o_value (<%= value_out[loop_variables] %>)
15
- );
data/lib/rggen/verilog/bit_field/type/w0src_w1src_wsrc.rb DELETED
@@ -1,20 +0,0 @@
1
- # frozen_string_literal: true
2
-
3
- RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
4
- verilog do
5
- build do
6
- output :value_out, {
7
- name: "o_#{full_name}", width: width, array_size: array_size
8
- }
9
- end
10
-
11
- main_code :bit_field, from_template: true
12
-
13
- private
14
-
15
- def set_value
16
- value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
17
- bin(value, 2)
18
- end
19
- end
20
- end