rggen-verilog 0.13.2 → 0.14.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2020-2025 Taichi Ishitani
+Copyright (c) 2020-2026 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -2,7 +2,7 @@
 [![CI](https://github.com/rggen/rggen-verilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-verilog/actions?query=workflow%3ACI)
 [![Maintainability](https://qlty.sh/badges/93f1f04b-d863-4f44-a968-2f2721a8f3de/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-verilog)
 [![codecov](https://codecov.io/gh/rggen/rggen-verilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-verilog)
-[![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
+[![Discord](https://img.shields.io/discord/1406572699467124806?style=flat&logo=discord)](https://discord.com/invite/KWya83ZZxr)
 
 # RgGen::Verilog
 
@@ -62,13 +62,13 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 * [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
 * [GitHub Discussions](https://github.com/rggen/rggen/discussions)
-* [Chat Room](https://gitter.im/rggen/rggen)
+* [Discord](https://discord.com/invite/KWya83ZZxr)
 * [Mailing List](https://groups.google.com/d/forum/rggen)
 * [Mail](mailto:rggen@googlegroups.com)
 
 ## Copyright & License
 
-Copyright © 2020-2025 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2020-2026 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/verilog/rtl/bit_field/type/counter.erb

@@ -0,0 +1,21 @@
+rggen_bit_field_counter #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .UP_WIDTH       (<%= up_width %>),
+  .DOWN_WIDTH     (<%= down_width %>),
+  .WRAP_AROUND    (<%= wrap_around %>),
+  .USE_CLEAR      (<%= use_clear_value %>)
+) u_bit_field (
+  .i_clk            (<%= clock %>),
+  .i_rst_n          (<%= reset %>),
+  .i_sw_read_valid  (<%= bit_field_read_valid %>),
+  .i_sw_write_valid (<%= bit_field_write_valid %>),
+  .i_sw_mask        (<%= bit_field_mask %>),
+  .i_sw_write_data  (<%= bit_field_write_data %>),
+  .o_sw_read_data   (<%= bit_field_read_data %>),
+  .o_sw_value       (<%= bit_field_value %>),
+  .i_clear          (<%= clear_signal %>),
+  .i_up             (<%= up[loop_variables] %>),
+  .i_down           (<%= down[loop_variables] %>),
+  .o_count          (<%= count[loop_variables] %>)
+);

data/lib/rggen/verilog/rtl/bit_field/type/counter.rb

@@ -0,0 +1,63 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, :counter) do
+  verilog_rtl do
+    build do
+      parameter :up_width, {
+        name: "#{full_name}_up_width".upcase, default: 1
+      }
+      parameter :up_port_width, {
+        name: "#{full_name}_up_port_width".upcase,
+        default: macro_call(:rggen_clip_width, up_width)
+      }
+      parameter :down_width, {
+        name: "#{full_name}_down_width".upcase, default: 1
+      }
+      parameter :down_port_width, {
+        name: "#{full_name}_down_port_width".upcase,
+        default: macro_call(:rggen_clip_width, down_width)
+      }
+      parameter :wrap_around, {
+        name: "#{full_name}_wrap_around".upcase, default: 0
+      }
+      if external_clear?
+        parameter :use_clear, {
+          name: "#{full_name}_use_clear".upcase, default: 1
+        }
+      end
+
+      input :up, {
+        name: "i_#{full_name}_up",
+        width: up_port_width, array_size:
+      }
+      input :down, {
+        name: "i_#{full_name}_down",
+        width: down_port_width, array_size:
+      }
+      if external_clear?
+        input :clear, {
+          name: "i_#{full_name}_clear", width: 1, array_size:
+        }
+      end
+      output :count, {
+        name: "o_#{full_name}", width:, array_size:
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def external_clear?
+      !bit_field.reference?
+    end
+
+    def use_clear_value
+      external_clear? && use_clear || 1
+    end
+
+    def clear_signal
+      reference_bit_field || clear[loop_variables]
+    end
+  end
+end

data/lib/rggen/verilog/rtl/register/type/maskable.erb

@@ -0,0 +1,27 @@
+rggen_maskable_register #(
+  .READABLE       (<%= readable %>),
+  .WRITABLE       (<%= writable %>),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>)
+) u_register (
+  .i_clk                    (<%= clock %>),
+  .i_rst_n                  (<%= reset %>),
+  .i_register_valid         (<%= register_valid %>),
+  .i_register_access        (<%= register_access %>),
+  .i_register_address       (<%= register_address %>),
+  .i_register_write_data    (<%= register_write_data %>),
+  .i_register_strobe        (<%= register_strobe %>),
+  .o_register_active        (<%= register_active %>),
+  .o_register_ready         (<%= register_ready %>),
+  .o_register_status        (<%= register_status %>),
+  .o_register_read_data     (<%= register_read_data %>),
+  .o_register_value         (<%= register_value %>),
+  .o_bit_field_read_valid   (<%= bit_field_read_valid %>),
+  .o_bit_field_write_valid  (<%= bit_field_write_valid %>),
+  .o_bit_field_mask         (<%= bit_field_mask %>),
+  .o_bit_field_write_data   (<%= bit_field_write_data %>),
+  .i_bit_field_read_data    (<%= bit_field_read_data %>),
+  .i_bit_field_value        (<%= bit_field_value %>)
+);

data/lib/rggen/verilog/rtl/register/type/maskable.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :maskable) do
+  verilog_rtl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/verilog/rtl/register_block/protocol/axi4lite.rb

@@ -17,7 +17,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'o_awready', width: 1
       }
       input :awid, {
-        name: 'i_awid', width: id_width_value
+        name: 'i_awid', width: macro_call(:rggen_clip_width, id_width)
       }
       input :awaddr, {
         name: 'i_awaddr', width: address_width
@@ -44,7 +44,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'i_bready', width: 1
       }
       output :bid, {
-        name: 'o_bid', width: id_width_value
+        name: 'o_bid', width: macro_call(:rggen_clip_width, id_width)
       }
       output :bresp, {
         name: 'o_bresp', width: 2
@@ -56,7 +56,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'o_arready', width: 1
       }
       input :arid, {
-        name: 'i_arid', width: id_width_value
+        name: 'i_arid', width: macro_call(:rggen_clip_width, id_width)
       }
       input :araddr, {
         name: 'i_araddr', width: address_width
@@ -71,7 +71,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
         name: 'i_rready', width: 1
       }
       output :rid, {
-        name: 'o_rid', width: id_width_value
+        name: 'o_rid', width: macro_call(:rggen_clip_width, id_width)
       }
       output :rdata, {
         name: 'o_rdata', width: bus_width
@@ -82,11 +82,5 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
     end
 
     main_code :register_block, from_template: true
-
-    private
-
-    def id_width_value
-      "((#{id_width} == 0) ? 1 : #{id_width})"
-    end
   end
 end

data/lib/rggen/verilog/utility.rb

@@ -20,6 +20,10 @@ module RgGen
       def width_cast(expression, _width)
         expression
       end
+
+      def macro_call(macro_name, args)
+        function_call("`#{macro_name}", args)
+      end
     end
   end
 end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.13.2'
+    VERSION = '0.14.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -34,9 +34,11 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl/register/type',
     'verilog/rtl/register/type/external',
     'verilog/rtl/register/type/indirect',
+    'verilog/rtl/register/type/maskable',
     'verilog/rtl/register/type/rw',
     'verilog/rtl/bit_field/verilog_top',
     'verilog/rtl/bit_field/type',
+    'verilog/rtl/bit_field/type/counter',
     'verilog/rtl/bit_field/type/custom',
     'verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc',
     'verilog/rtl/bit_field/type/ro_rotrg',

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.13.2
+  version: 0.14.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-07-21 00:00:00.000000000 Z
+date: 1980-01-02 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -15,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.1
+        version: 0.36.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.35.1
+        version: 0.36.0
 description: Verilog write plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -38,6 +38,8 @@ files:
 - lib/rggen/verilog/register_map/keyword_checker.rb
 - lib/rggen/verilog/register_map/name.rb
 - lib/rggen/verilog/rtl/bit_field/type.rb
+- lib/rggen/verilog/rtl/bit_field/type/counter.erb
+- lib/rggen/verilog/rtl/bit_field/type/counter.rb
 - lib/rggen/verilog/rtl/bit_field/type/custom.erb
 - lib/rggen/verilog/rtl/bit_field/type/custom.rb
 - lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
@@ -83,6 +85,8 @@ files:
 - lib/rggen/verilog/rtl/register/type/external.rb
 - lib/rggen/verilog/rtl/register/type/indirect.erb
 - lib/rggen/verilog/rtl/register/type/indirect.rb
+- lib/rggen/verilog/rtl/register/type/maskable.erb
+- lib/rggen/verilog/rtl/register/type/maskable.rb
 - lib/rggen/verilog/rtl/register/type/rw.erb
 - lib/rggen/verilog/rtl/register/type/rw.rb
 - lib/rggen/verilog/rtl/register/verilog_top.rb
@@ -124,14 +128,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.1'
+      version: '3.2'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.6.2
+rubygems_version: 4.0.3
 specification_version: 4
-summary: rggen-verilog-0.13.2
+summary: rggen-verilog-0.14.0
 test_files: []