rggen-verilog 0.11.1 → 0.12.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2020-2024 Taichi Ishitani
+Copyright (c) 2020-2025 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
 
 ## Copyright & License
 
-Copyright © 2020-2024 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2020-2025 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/verilog/register_map/keyword_checker.rb

@@ -0,0 +1,43 @@
+# frozen_string_literal: true
+
+module RgGen
+  module Verilog
+    module RegisterMap
+      module KeywordChecker
+        VERILOG_KEYWORDS = [
+          'always', 'and', 'assign', 'automatic', 'begin', 'buf', 'bufif0', 'bufif1',
+          'case', 'casex', 'casez', 'cell', 'cmos', 'config', 'deassign', 'default',
+          'defparam', 'design', 'disable', 'edge', 'else', 'end', 'endcase', 'endconfig',
+          'endfunction', 'endgenerate', 'endmodule', 'endprimitive', 'endspecify',
+          'endtable', 'endtask', 'event', 'for', 'force', 'forever', 'fork', 'function',
+          'generate', 'genvar', 'highz0', 'highz1', 'if', 'ifnone', 'incdir', 'include',
+          'initial', 'inout', 'input', 'instance', 'integer', 'join', 'large', 'liblist',
+          'library', 'localparam', 'macromodule', 'medium', 'module', 'nand', 'negedge',
+          'nmos', 'nor', 'noshowcancelled', 'not', 'notif0', 'notif1', 'or', 'output',
+          'parameter', 'pmos', 'posedge', 'primitive', 'pull0', 'pull1', 'pulldown',
+          'pullup', 'pulsestyle_onevent', 'pulsestyle_ondetect', 'rcmos', 'real',
+          'realtime', 'reg', 'release', 'repeat', 'rnmos', 'rpmos', 'rtran', 'rtranif0',
+          'rtranif1', 'scalared', 'showcancelled', 'signed', 'small', 'specify',
+          'specparam', 'strong0', 'strong1', 'supply0', 'supply1', 'table', 'task',
+          'time', 'tran', 'tranif0', 'tranif1', 'tri', 'tri0', 'tri1', 'triand', 'trior',
+          'trireg', 'unsigned', 'use', 'uwire', 'vectored', 'wait', 'wand', 'weak0',
+          'weak1', 'while', 'wire', 'wor', 'xnor', 'xor'
+        ].freeze
+
+        def self.included(klass)
+          klass.class_eval do
+            verify(:feature, prepend: true) do
+              error_condition do
+                @name && VERILOG_KEYWORDS.include?(@name)
+              end
+              message do
+                layer_name = component.layer.to_s.sub('_', ' ')
+                "verilog keyword is not allowed for #{layer_name} name: #{@name}"
+              end
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/verilog/register_map/name.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+[:register_block, :register_file, :register, :bit_field].each do |layer|
+  RgGen.modify_simple_feature(layer, :name) do
+    register_map do
+      include RgGen::Verilog::RegisterMap::KeywordChecker
+    end
+  end
+end

data/lib/rggen/verilog/rtl/bit_field/type/custom.rb

@@ -5,39 +5,39 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       else
         output :value_out, {
-          name: "o_#{full_name}", width: width, array_size: array_size
+          name: "o_#{full_name}", width:, array_size:
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
-          name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_write_data", width:, array_size:
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_set", width:, array_size:
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_clear", width:, array_size:
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,14 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   verilog_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", width: width, array_size: array_size
+        name: "i_#{full_name}_set", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", width: width, array_size: array_size
+          name: "o_#{full_name}_unmasked", width:, array_size:
         }
       end
     end

data/lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb

@@ -5,12 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rotrg?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/verilog/rtl/bit_field/type/rohw.rb

@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.rb

@@ -4,19 +4,19 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rowotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,10 +4,10 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   verilog_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", width: width, array_size: array_size
+        name: "i_#{full_name}_clear", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -4,14 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/verilog/rtl/bit_field/type/rwc.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", width: 1, array_size: array_size
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb

@@ -6,11 +6,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
       unless bit_field.reference?
         input :control, {
           name: "i_#{full_name}_#{enable_or_lock}",
-          width: 1, array_size: array_size
+          width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/rwhw.rb

@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/rws.rb

@@ -5,11 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", width: 1, array_size: array_size
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,7 +6,7 @@ RgGen.define_list_item_feature(
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   verilog_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -4,11 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.rb

@@ -4,7 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/verilog/rtl/feature.rb

@@ -8,20 +8,20 @@ module RgGen
 
         private
 
-        def create_variable(data_type, attributes, &block)
+        def create_variable(data_type, attributes, &)
           attributes = attributes.merge(array_format: :serialized)
           super
         end
 
-        def create_port(direction, attributes, &block)
+        def create_port(direction, attributes, &)
           attributes =
             attributes
               .except(:data_type)
-              .merge(direction: direction, array_format: :serialized)
-          DataObject.new(:argument, attributes, &block)
+              .merge(direction:, array_format: :serialized)
+          DataObject.new(:argument, attributes, &)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
+        def create_parameter(parameter_type, attributes, &)
           attributes = attributes.merge(array_format: :serialized)
           super
         end

data/lib/rggen/verilog/rtl/register/type/external.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     build do
       parameter :strobe_width, {
         name: "#{register.name}_strobe_width".upcase,
-        default: configuration.bus_width / 8
+        default: register_block.byte_width
       }
       output :external_valid, {
         name: "o_#{register.name}_valid", width: 1

data/lib/rggen/verilog/rtl/register_block/protocol/native.erb

@@ -0,0 +1,33 @@
+rggen_native_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .STROBE_WIDTH         (<%= strobe_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
+) u_adapter (
+  .i_clk                  (<%= register_block.clock %>),
+  .i_rst_n                (<%= register_block.reset %>),
+  .i_csrbus_valid         (<%= valid %>),
+  .i_csrbus_access        (<%= access %>),
+  .i_csrbus_address       (<%= address %>),
+  .i_csrbus_write_data    (<%= write_data %>),
+  .i_csrbus_strobe        (<%= strobe %>),
+  .o_csrbus_ready         (<%= ready %>),
+  .o_csrbus_status        (<%= status %>),
+  .o_csrbus_read_data     (<%= read_data %>),
+  .o_register_valid       (<%= register_block.register_valid %>),
+  .o_register_access      (<%= register_block.register_access %>),
+  .o_register_address     (<%= register_block.register_address %>),
+  .o_register_write_data  (<%= register_block.register_write_data %>),
+  .o_register_strobe      (<%= register_block.register_strobe %>),
+  .i_register_active      (<%= register_block.register_active %>),
+  .i_register_ready       (<%= register_block.register_ready %>),
+  .i_register_status      (<%= register_block.register_status %>),
+  .i_register_read_data   (<%= register_block.register_read_data %>)
+);

data/lib/rggen/verilog/rtl/register_block/protocol/native.rb

@@ -0,0 +1,38 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :native) do
+  verilog_rtl do
+    build do
+      parameter :strobe_width, {
+        name: 'STROBE_WIDTH', default: bus_width / 8
+      }
+
+      input :valid, {
+        name: 'i_csrbus_valid', width: 1
+      }
+      input :access, {
+        name: 'i_csrbus_access', width: 2
+      }
+      input :address, {
+        name: 'i_csrbus_address', width: address_width
+      }
+      input :write_data, {
+        name: 'i_csrbus_write_data', width: bus_width
+      }
+      input :strobe, {
+        name: 'i_csrbus_strobe', width: strobe_width
+      }
+      output :ready, {
+        name: 'o_csrbus_ready', width: 1
+      }
+      output :status, {
+        name: 'o_csrbus_status', width: 2
+      }
+      output :read_data, {
+        name: 'o_csrbus_read_data', width: bus_width
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/verilog/rtl/register_block/protocol.rb

@@ -29,7 +29,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
       private
 
       def bus_width
-        configuration.bus_width
+        register_block.bus_width
       end
 
       def local_address_width
@@ -46,8 +46,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
     end
 
     factory do
-      def target_feature_key(configuration, _register_block)
-        configuration.protocol
+      def target_feature_key(_configuration, register_block)
+        register_block.protocol
       end
     end
   end

data/lib/rggen/verilog/rtl/register_block/verilog_top.rb

@@ -57,7 +57,7 @@ RgGen.define_simple_feature(:register_block, :verilog_top) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def value_width

data/lib/rggen/verilog/utility.rb

@@ -5,8 +5,8 @@ module RgGen
     module Utility
       private
 
-      def local_scope(name, attributes = {}, &block)
-        LocalScope.new(attributes.merge(name: name), &block).to_code
+      def local_scope(name, attributes = {}, &)
+        LocalScope.new(attributes.merge(name:), &).to_code
       end
 
       def fill_0(width)

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.11.1'
+    VERSION = '0.12.0'
   end
 end

data/lib/rggen/verilog.rb

@@ -8,6 +8,7 @@ require_relative 'verilog/rtl/component'
 require_relative 'verilog/rtl/feature'
 require_relative 'verilog/rtl_header/component'
 require_relative 'verilog/rtl_header/feature'
+require_relative 'verilog/register_map/keyword_checker'
 require_relative 'verilog/factories'
 
 RgGen.setup_plugin :'rggen-verilog' do |plugin|
@@ -26,6 +27,7 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl/register_block/protocol/apb',
     'verilog/rtl/register_block/protocol/axi4lite',
     'verilog/rtl/register_block/protocol/wishbone',
+    'verilog/rtl/register_block/protocol/native',
     'verilog/rtl/register_file/verilog_top',
     'verilog/rtl/register/verilog_top',
     'verilog/rtl/register/type',
@@ -66,4 +68,8 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
     'verilog/rtl_header/register/verilog_rtl_header',
     'verilog/rtl_header/register_block/verilog_rtl_header'
   ]
+
+  plugin.files [
+    'verilog/register_map/name'
+  ]
 end

metadata

@@ -1,14 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.11.1
+  version: 0.12.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-11-28 00:00:00.000000000 Z
+date: 2025-01-23 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +15,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.1
+        version: 0.34.0
 description: Verilog write plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -36,6 +35,8 @@ files:
 - README.md
 - lib/rggen/verilog.rb
 - lib/rggen/verilog/factories.rb
+- lib/rggen/verilog/register_map/keyword_checker.rb
+- lib/rggen/verilog/register_map/name.rb
 - lib/rggen/verilog/rtl/bit_field/type.rb
 - lib/rggen/verilog/rtl/bit_field/type/custom.erb
 - lib/rggen/verilog/rtl/bit_field/type/custom.rb
@@ -90,6 +91,8 @@ files:
 - lib/rggen/verilog/rtl/register_block/protocol/apb.rb
 - lib/rggen/verilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/verilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/verilog/rtl/register_block/protocol/native.erb
+- lib/rggen/verilog/rtl/register_block/protocol/native.rb
 - lib/rggen/verilog/rtl/register_block/protocol/wishbone.erb
 - lib/rggen/verilog/rtl/register_block/protocol/wishbone.rb
 - lib/rggen/verilog/rtl/register_block/verilog_macros.erb
@@ -112,7 +115,6 @@ metadata:
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-verilog
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -120,15 +122,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.0'
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.16
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-verilog-0.11.1
+summary: rggen-verilog-0.12.0
 test_files: []