rggen-verilog 0.11.0 → 0.11.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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+  data.tar.gz: 7efc7297a728743b96fb447f11e63ee59eb69840790970683a31506f8d4f8547
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+  data.tar.gz: c1112eb1588ea48f963177b235a55e1251b7b9c4fa3802e6907ba752a6de695077207fa0472b76c1e44bd34b990b71a46318a178224459de85f8549e7b6988be

data/lib/rggen/verilog/rtl/register/type/indirect.erb

@@ -5,8 +5,7 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .INDIRECT_INDEX_WIDTH (<%= index_width %>),
-  .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
+  .INDIRECT_MATCH_WIDTH (<%= index_match_width %>)
 ) u_register (
   .i_clk                  (<%= clock %>),
   .i_rst_n                (<%= reset %>),
@@ -20,7 +19,7 @@ rggen_indirect_register #(
   .o_register_status      (<%= register_status %>),
   .o_register_read_data   (<%= register_read_data %>),
   .o_register_value       (<%= register_value %>),
-  .i_indirect_index       (<%= indirect_index %>),
+  .i_indirect_match       (<%= indirect_match %>),
   .o_bit_field_valid      (<%= bit_field_valid %>),
   .o_bit_field_read_mask  (<%= bit_field_read_mask %>),
   .o_bit_field_write_mask (<%= bit_field_write_mask %>),

data/lib/rggen/verilog/rtl/register/type/indirect.rb

@@ -5,14 +5,20 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     include RgGen::SystemVerilog::RTL::IndirectIndex
 
     build do
-      wire :indirect_index, {
-        name: 'w_indirect_index', width: index_width
+      wire :indirect_match, {
+        name: 'w_indirect_match', width: index_match_width
       }
     end
 
     main_code :register do |code|
-      code << indirect_index_assignment << nl
+      indirect_index_matches(code)
       code << process_template
     end
+
+    private
+
+    def array_index_value(value, width)
+      value[0, width]
+    end
   end
 end

data/lib/rggen/verilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module Verilog
-    VERSION = '0.11.0'
+    VERSION = '0.11.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-verilog
 version: !ruby/object:Gem::Version
-  version: 0.11.0
+  version: 0.11.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-01-22 00:00:00.000000000 Z
+date: 2024-11-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: rggen-systemverilog
@@ -16,14 +16,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.33.0
+        version: 0.33.1
 description: Verilog write plugin for RgGen
 email:
 - rggen@googlegroups.com
@@ -127,8 +127,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.3
+rubygems_version: 3.5.16
 signing_key: 
 specification_version: 4
-summary: rggen-verilog-0.11.0
+summary: rggen-verilog-0.11.1
 test_files: []