rggen-verilog 0.10.0 → 0.11.0
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- checksums.yaml +4 -4
- data/LICENSE +1 -1
- data/README.md +1 -1
- data/lib/rggen/verilog/rtl/bit_field/type/{rol.erb → rohw.erb} +1 -1
- data/lib/rggen/verilog/rtl/bit_field/type/{rol.rb → rohw.rb} +5 -5
- data/lib/rggen/verilog/rtl/bit_field/type/rwhw.erb +24 -0
- data/lib/rggen/verilog/rtl/bit_field/type/rwhw.rb +27 -0
- data/lib/rggen/verilog/rtl/bit_field/type/rws.erb +5 -4
- data/lib/rggen/verilog/rtl/bit_field/type/rws.rb +0 -3
- data/lib/rggen/verilog/version.rb +1 -1
- data/lib/rggen/verilog.rb +2 -1
- metadata +9 -7
checksums.yaml
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@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: c51f12437d8fa2b759cdac993be71633df8d140687b0d12a566ca8d56ed14ecc
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data.tar.gz: 6e50f1af0dd65e009d53a9cf38778c99e3392fa4b0fc8ddf20ede72643e17664
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 87cb9445bc512d778e6992eaee5a86d67edcb5740c4cd5cc1a6c3bc4bbb35db743f74246b20b4397a436c17bdb2e85fcc3e310c87a47f473904fe21b7b2fab26
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7
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data.tar.gz: 03c553d8ce11624b400f3ebae46f18ea311bdfc71b4734ce1254d412b08815bdad4a21a33f87407b8da7aae15ffaa4e49fe8fb4d3a5ced553e87c1faa3617650
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data/LICENSE
CHANGED
@@ -1,6 +1,6 @@
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The MIT License (MIT)
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-
Copyright (c) 2020-
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Copyright (c) 2020-2024 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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data/README.md
CHANGED
@@ -68,7 +68,7 @@ Feedbacks, bus reports, questions and etc. are welcome! You can post them bu usi
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## Copyright & License
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-
Copyright © 2020-
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Copyright © 2020-2024 Taichi Ishitani. RgGen::Verilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
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## Code of Conduct
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@@ -14,7 +14,7 @@ rggen_bit_field #(
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.o_sw_value (<%= bit_field_value %>),
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.o_write_trigger (),
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.o_read_trigger (),
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-
.i_hw_write_enable (<%=
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.i_hw_write_enable (<%= valid_signal %>),
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.i_hw_write_data (<%= value_in[loop_variables] %>),
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.i_hw_set (<%= fill_0(width) %>),
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.i_hw_clear (<%= fill_0(width) %>),
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@@ -1,11 +1,11 @@
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# frozen_string_literal: true
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-
RgGen.define_list_item_feature(:bit_field, :type, :
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RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
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verilog_rtl do
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build do
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unless bit_field.reference?
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input :
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name: "i_#{full_name}
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input :valid, {
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name: "i_#{full_name}_valid", width: 1, array_size: array_size
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}
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end
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input :value_in, {
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@@ -18,8 +18,8 @@ RgGen.define_list_item_feature(:bit_field, :type, :rol) do
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main_code :bit_field, from_template: true
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-
def
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reference_bit_field ||
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def valid_signal
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reference_bit_field || valid[loop_variables]
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end
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end
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end
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@@ -0,0 +1,24 @@
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1
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rggen_bit_field #(
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.WIDTH (<%= width %>),
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.INITIAL_VALUE (<%= initial_value %>)
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) u_bit_field (
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.i_clk (<%= clock %>),
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.i_rst_n (<%= reset %>),
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.i_sw_valid (<%= bit_field_valid %>),
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.i_sw_read_mask (<%= bit_field_read_mask %>),
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.i_sw_write_enable (1'b1),
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.i_sw_write_mask (<%= bit_field_write_mask %>),
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.i_sw_write_data (<%= bit_field_write_data %>),
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.o_sw_read_data (<%= bit_field_read_data %>),
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.o_sw_value (<%= bit_field_value %>),
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.o_write_trigger (),
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.o_read_trigger (),
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.i_hw_write_enable (<%= valid_signal %>),
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.i_hw_write_data (<%= value_in[loop_variables] %>),
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.i_hw_set (<%= fill_0(width) %>),
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.i_hw_clear (<%= fill_0(width) %>),
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.i_value (<%= fill_0(width) %>),
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.i_mask (<%= fill_1(width) %>),
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.o_value (<%= value_out[loop_variables] %>),
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.o_value_unmasked ()
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);
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# frozen_string_literal: true
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RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
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verilog_rtl do
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build do
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unless bit_field.reference?
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input :valid, {
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name: "i_#{full_name}_valid", width: 1, array_size: array_size
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}
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end
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input :value_in, {
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name: "i_#{full_name}", width: width, array_size: array_size
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}
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output :value_out, {
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name: "o_#{full_name}", width: width, array_size: array_size
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}
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end
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main_code :bit_field, from_template: true
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private
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def valid_signal
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reference_bit_field || valid[loop_variables]
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end
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end
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end
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@@ -1,6 +1,7 @@
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rggen_bit_field #(
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.WIDTH (<%= width %>),
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.INITIAL_VALUE (<%= initial_value %>)
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.INITIAL_VALUE (<%= initial_value %>),
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.HW_SET_WIDTH (1)
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) u_bit_field (
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.i_clk (<%= clock %>),
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.i_rst_n (<%= reset %>),
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@@ -13,9 +14,9 @@ rggen_bit_field #(
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.o_sw_value (<%= bit_field_value %>),
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.o_write_trigger (),
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.o_read_trigger (),
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-
.i_hw_write_enable (
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.i_hw_write_data (<%=
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.i_hw_set (<%=
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.i_hw_write_enable (1'b0),
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.i_hw_write_data (<%= fill_0(width) %>),
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.i_hw_set (<%= set_signal %>),
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.i_hw_clear (<%= fill_0(width) %>),
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.i_value (<%= fill_0(width) %>),
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.i_mask (<%= fill_1(width) %>),
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@@ -8,9 +8,6 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
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name: "i_#{full_name}_set", width: 1, array_size: array_size
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}
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end
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input :value_in, {
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name: "i_#{full_name}", width: width, array_size: array_size
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}
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output :value_out, {
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name: "o_#{full_name}", width: width, array_size: array_size
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}
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data/lib/rggen/verilog.rb
CHANGED
@@ -38,13 +38,14 @@ RgGen.setup_plugin :'rggen-verilog' do |plugin|
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'verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc',
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'verilog/rtl/bit_field/type/ro_rotrg',
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'verilog/rtl/bit_field/type/rof',
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-
'verilog/rtl/bit_field/type/
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'verilog/rtl/bit_field/type/rohw',
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'verilog/rtl/bit_field/type/row0trg_row1trg',
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'verilog/rtl/bit_field/type/rowo_rowotrg',
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'verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos',
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'verilog/rtl/bit_field/type/rw_rwtrg_w1',
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'verilog/rtl/bit_field/type/rwc',
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'verilog/rtl/bit_field/type/rwe_rwl',
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'verilog/rtl/bit_field/type/rwhw',
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'verilog/rtl/bit_field/type/rws',
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'verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
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'verilog/rtl/bit_field/type/w0t_w1t',
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
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--- !ruby/object:Gem::Specification
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name: rggen-verilog
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.11.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date:
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date: 2024-01-22 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: rggen-systemverilog
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@@ -16,14 +16,14 @@ dependencies:
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.33.0
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type: :runtime
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prerelease: false
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version_requirements: !ruby/object:Gem::Requirement
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requirements:
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- - ">="
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- !ruby/object:Gem::Version
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version: 0.
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version: 0.33.0
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description: Verilog write plugin for RgGen
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email:
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- rggen@googlegroups.com
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@@ -45,8 +45,8 @@ files:
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- lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb
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- lib/rggen/verilog/rtl/bit_field/type/rof.erb
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- lib/rggen/verilog/rtl/bit_field/type/rof.rb
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-
- lib/rggen/verilog/rtl/bit_field/type/
|
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-
- lib/rggen/verilog/rtl/bit_field/type/
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- lib/rggen/verilog/rtl/bit_field/type/rohw.erb
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- lib/rggen/verilog/rtl/bit_field/type/rohw.rb
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- lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.erb
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- lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb
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- lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.erb
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@@ -59,6 +59,8 @@ files:
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- lib/rggen/verilog/rtl/bit_field/type/rwc.rb
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- lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.erb
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- lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb
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- lib/rggen/verilog/rtl/bit_field/type/rwhw.erb
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- lib/rggen/verilog/rtl/bit_field/type/rwhw.rb
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- lib/rggen/verilog/rtl/bit_field/type/rws.erb
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- lib/rggen/verilog/rtl/bit_field/type/rws.rb
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- lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
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@@ -128,5 +130,5 @@ requirements: []
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rubygems_version: 3.5.3
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signing_key:
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specification_version: 4
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-
summary: rggen-verilog-0.
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summary: rggen-verilog-0.11.0
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test_files: []
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