rggen-systemverilog 0.34.0 → 0.35.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/README.md

@@ -1,6 +1,6 @@
 [![Gem Version](https://badge.fury.io/rb/rggen-systemverilog.svg)](https://badge.fury.io/rb/rggen-systemverilog)
 [![CI](https://github.com/rggen/rggen-systemverilog/workflows/CI/badge.svg)](https://github.com/rggen/rggen-systemverilog/actions?query=workflow%3ACI)
-[![Maintainability](https://api.codeclimate.com/v1/badges/88086c5be538a1564a35/maintainability)](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
+[![Maintainability](https://qlty.sh/badges/1b06df23-43bd-413d-90f9-b98c565be895/maintainability.svg)](https://qlty.sh/gh/rggen/projects/rggen-systemverilog)
 [![codecov](https://codecov.io/gh/rggen/rggen-systemverilog/branch/master/graph/badge.svg)](https://codecov.io/gh/rggen/rggen-systemverilog)
 [![Gitter](https://badges.gitter.im/rggen/rggen.svg)](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
 

data/lib/rggen/systemverilog/common/feature.rb

@@ -16,14 +16,10 @@ module RgGen
           def define_entity(entity_type, method, declaration_type, default_layer)
             context =
               EntityContext.new(entity_type, method, declaration_type, default_layer)
-            define_method(entity_type) do |name, *args, &block|
-              if args.size >= 3
-                message = 'wrong number of arguments ' \
-                          "(given #{args.size + 1}, expected 1..3)"
-                raise ArgumentError.new(message)
-              end
-              define_entity(context, name, args, &block)
-            end
+            feature_hash_variable_store(:@entity_contexts, entity_type, context)
+
+            return if method_defined?(entity_type)
+            public alias_method(entity_type, :entity_method)
           end
         end
 
@@ -38,6 +34,17 @@ module RgGen
           @package_imports = Hash.new { |h, k| h[k] = [] }
         end
 
+        def entity_method(name, *args, &)
+          if args.size >= 3
+            message = 'wrong number of arguments ' \
+                      "(given #{args.size + 1}, expected 1..3)"
+            raise ArgumentError.new(message)
+          end
+
+          context = feature_hash_variable_fetch(:@entity_contexts, __callee__)
+          define_entity(context, name, args, &)
+        end
+
         def define_entity(context, name, args, &)
           layer, attributes = parse_entity_arguments(args)
           entity = create_entity(context, name, attributes, &)

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -49,13 +49,14 @@ RgGen.define_list_feature(:bit_field, :type) do
       private
 
       def array_size
-        Array(bit_field.sequence_size)
+        bit_field.sequence_size&.then { [_1] }
       end
 
       def arguments(index)
         [
           ral_model[index], bit_field.lsb(index), bit_field.width, string(access),
-          volatile, reset_value(index), valid_reset, index || -1, string(reference)
+          volatile, reset_value, reset_values, valid_reset,
+          index || 0, bit_field.sequence_size || 0, string(reference)
         ]
       end
 
@@ -63,12 +64,19 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.volatile? && 1 || 0
       end
 
-      def reset_value(index)
-        value =
-          bit_field.initial_values&.at(index) || bit_field.initial_value || 0
+      def reset_value
+        value = bit_field.initial_value || 0
         hex(value, bit_field.width)
       end
 
+      def reset_values
+        values =
+          bit_field
+            .initial_values(flatten: true)
+            &.map { |value| hex(value, bit_field.width) }
+        array(values)
+      end
+
       def valid_reset
         bit_field.initial_value? && 1 || 0
       end

data/lib/rggen/systemverilog/ral/register/type.rb

@@ -32,7 +32,7 @@ RgGen.define_list_feature(:register, :type) do
       end
 
       def constructors
-        array_indices.map.with_index(&method(:constructor_code))
+        array_indexes.map.with_index(&method(:constructor_code))
       end
 
       private
@@ -55,8 +55,8 @@ RgGen.define_list_feature(:register, :type) do
 
       def arguments(array_index, index)
         [
-          ral_model[array_index], array(array_index), offset_address(index),
-          string(access_rights), string(hdl_path(array_index))
+          ral_model[array_index], array(array_index), array(register.array_size),
+          offset_address(index), string(access_rights), string(hdl_path(array_index))
         ]
       end
 

data/lib/rggen/systemverilog/ral/register_common.rb

@@ -6,7 +6,7 @@ module RgGen
       module RegisterCommon
         private
 
-        def array_indices
+        def array_indexes
           if component.array?
             index_table = component.array_size.map { |size| (0...size).to_a }
             index_table[0].product(*index_table[1..])

data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb

@@ -14,7 +14,7 @@ RgGen.define_simple_feature(:register_file, :sv_ral_model) do
     end
 
     def constructors
-      array_indices.map.with_index(&method(:constructor_code))
+      array_indexes.map.with_index(&method(:constructor_code))
     end
 
     main_code :ral_package do
@@ -37,8 +37,8 @@ RgGen.define_simple_feature(:register_file, :sv_ral_model) do
 
     def arguments(array_index, index)
       [
-        ral_model[array_index], array(array_index), offset_address(index),
-        string(hdl_path(array_index))
+        ral_model[array_index], array(array_index), array(register_file.array_size),
+        offset_address(index), string(hdl_path(array_index))
       ]
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -10,20 +10,17 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       if fixed_initial_value?
         localparam :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
-          array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_rhs
+          array_size: initial_value_size, default: initial_value_rhs
         }
       elsif initial_value?
         parameter :initial_value, {
           name: initial_value_name, data_type: :bit, width: bit_field.width,
-          array_size: initial_value_size, array_format: initial_value_format,
-          default: initial_value_rhs
+          array_size: initial_value_size, default: initial_value_rhs
         }
       end
       interface :bit_field_sub_if, {
         name: 'bit_field_sub_if',
-        interface_type: 'rggen_bit_field_if',
-        parameter_values: [bit_field.width]
+        interface_type: 'rggen_bit_field_if', parameter_values: [bit_field.width]
       }
     end
 
@@ -49,7 +46,7 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     end
 
     def register_if(offsets)
-      index = register.index(offsets || register.local_indices)
+      index = register.index(offsets || register.local_indexes)
       register_block.register_if[index]
     end
 
@@ -61,25 +58,17 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     end
 
     def initial_value_size
-      initial_value_array? && [bit_field.sequence_size] || nil
-    end
-
-    def initial_value_format
-      fixed_initial_value? && :unpacked ||
-        configuration.array_port_format
+      initial_value_array? && array_size || nil
     end
 
     def initial_value_rhs
-      initial_value_array? && initial_value_array_rhs || sized_initial_value
-    end
-
-    def initial_value_array_rhs
-      if fixed_initial_value?
-        array(sized_initial_values)
-      elsif initial_value_format == :unpacked
-        array(default: sized_initial_value)
+      if !initial_value_array?
+        sized_initial_value
+      elsif fixed_initial_value?
+        concat(sized_initial_values)
       else
-        repeat(bit_field.sequence_size, sized_initial_value)
+        size = array_size.inject(:*)
+        repeat(size, sized_initial_value)
       end
     end
 
@@ -89,7 +78,10 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     end
 
     def sized_initial_values
-      bit_field.initial_values&.map { |v| hex(v, bit_field.width) }
+      bit_field
+        .initial_values(flatten: true)
+        .map { |v| hex(v, bit_field.width) }
+        .reverse
     end
 
     def loop_size

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb

@@ -5,47 +5,39 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}", width:, array_size:
         }
       else
         output :value_out, {
-          name: "o_#{full_name}", width:,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}", width:, array_size:
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
-          name: "i_#{full_name}_hw_write_enable", width: 1,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_hw_write_data", width:, array_size:
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_hw_set", width:, array_size:
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_hw_clear", width:, array_size:
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,17 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   sv_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", width:,
-        array_size:, array_format: array_port_format
+        name: "i_#{full_name}_set", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", width:,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_unmasked", width:, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb

@@ -5,14 +5,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rotrg?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb

@@ -5,17 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb

@@ -4,23 +4,19 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width:,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rowotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,12 +4,10 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   sv_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", width:,
-        array_size:, array_format: array_port_format
+        name: "i_#{full_name}_clear", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -4,17 +4,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", width: 1,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
     build do
       unless bit_field.reference?
         input :control, {
-          name: "i_#{full_name}_#{enable_or_lock}", width: 1,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_#{enable_or_lock}", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb

@@ -5,17 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -5,13 +5,11 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", width: 1,
-          array_size:, array_format: array_port_format
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,8 +6,7 @@ RgGen.define_list_item_feature(
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -4,13 +4,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1,
-          array_size:, array_format: array_port_format
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -4,8 +4,7 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width:,
-        array_size:, array_format: array_port_format
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -9,10 +9,6 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       private
 
-      def array_port_format
-        configuration.array_port_format
-      end
-
       def full_name
         bit_field.full_name('_')
       end
@@ -38,7 +34,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def initial_value
-        index = bit_field.initial_value_array? && bit_field.local_index || nil
+        index = bit_field.initial_value_array? && loop_variables || nil
         bit_field.initial_value[index]
       end
 
@@ -50,7 +46,7 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.reference? &&
           bit_field
             .find_reference(register_block.bit_fields)
-            .value(bit_field.local_indices, bit_field.reference_width)
+            .value(bit_field.local_indexes, bit_field.reference_width)
       end
 
       def bit_field_if

data/lib/rggen/systemverilog/rtl/bit_field_index.rb

@@ -5,7 +5,7 @@ module RgGen
     module RTL
       module BitFieldIndex
         EXPORTED_METHODS = [
-          :local_index, :local_indices, :loop_variables, :array_size
+          :local_index, :local_indexes, :loop_variables, :flat_loop_index, :array_size
         ].freeze
 
         def self.included(feature)
@@ -18,8 +18,8 @@ module RgGen
           create_identifier(local_index_name)
         end
 
-        def local_indices
-          [*register.local_indices, local_index_name]
+        def local_indexes
+          [*register.local_indexes, local_index_name]
         end
 
         def loop_variables
@@ -27,13 +27,22 @@ module RgGen
             [*register.loop_variables, local_index].compact
         end
 
+        def flat_loop_index
+          return unless inside_loop?
+
+          size = array_size
+          factors =
+            Array.new(size.size) { |i| size[(i + 1)..].inject(1, :*) }
+          factors
+            .zip(loop_variables)
+            .map { |f, v| f == 1 && v || "#{f}*#{v}" }
+            .join('+')
+        end
+
         def array_size
-          (inside_loop? || nil) &&
-            [
-              *register_files.flat_map(&:array_size),
-              *register.array_size,
-              *bit_field.sequence_size
-            ].compact
+          return unless inside_loop?
+
+          [*register.array_size(hierarchical: true), *bit_field.sequence_size]
         end
 
         private

data/lib/rggen/systemverilog/rtl/register_block/protocol/avalon.erb

@@ -0,0 +1,17 @@
+rggen_avalon_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .avalon_if    (<%= avalon_if %>),
+  .register_if  (<%= register_if %>)
+);

data/lib/rggen/systemverilog/rtl/register_block/protocol/avalon.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :avalon) do
+  register_map do
+    verify(:component) do
+      error_condition { configuration.address_width > 64 }
+      message do
+        'address width over 64 bits is not supported: ' \
+        "#{configuration.address_width}"
+      end
+      position do
+        configuration.feature(:address_width).position
+      end
+    end
+
+    verify(:component) do
+      error_condition { register_block.bus_width > 1024 }
+      message do
+        'bus width over 1024 bits is not supported: ' \
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
+      end
+    end
+  end
+
+  sv_rtl do
+    build do
+      interface_port :avalon_if, {
+        name: 'avalon_if', interface_type: 'rggen_avalon_if', modport: 'agent'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/protocol/native.erb

@@ -7,6 +7,7 @@ rggen_native_adapter #(
   .PRE_DECODE           (<%= pre_decode %>),
   .BASE_ADDRESS         (<%= base_address %>),
   .BYTE_SIZE            (<%= byte_size %>),
+  .USE_READ_STROBE      (<%= use_read_strobe %>),
   .ERROR_STATUS         (<%= error_status %>),
   .DEFAULT_READ_DATA    (<%= default_read_data %>),
   .INSERT_SLICER        (<%= insert_slicer %>)

data/lib/rggen/systemverilog/rtl/register_block/protocol/native.rb

@@ -6,6 +6,9 @@ RgGen.define_list_item_feature(:register_block, :protocol, :native) do
       parameter :strobe_width, {
         name: 'STROBE_WIDTH', data_type: :int, default: bus_width / 8
       }
+      parameter :use_read_strobe, {
+        name: 'USE_READ_STROBE', data_type: :bit, default: 0
+      }
       interface_port :csrbus_if, {
         name: 'csrbus_if', interface_type: 'rggen_bus_if', modport: 'slave'
       }

data/lib/rggen/systemverilog/rtl/register_index.rb

@@ -8,7 +8,7 @@ module RgGen
 
         EXPORTED_METHODS = [
           :loop_variables, :local_loop_variables,
-          :local_index, :local_indices,
+          :local_index, :local_indexes,
           :index, :inside_loop?
         ].freeze
 
@@ -45,15 +45,15 @@ module RgGen
               .join('+')
         end
 
-        def local_indices
-          [*upper_register_file&.local_indices, local_index]
+        def local_indexes
+          [*upper_register_file&.local_indexes, local_index]
         end
 
         def index(offset_or_offsets = nil)
           offset_or_offsets
             .then(&method(:index_operands))
             .then(&method(:partial_sums))
-            .then(&method(:reduce_indices))
+            .then(&method(:reduce_indexes))
         end
 
         def inside_loop?
@@ -84,11 +84,11 @@ module RgGen
           ]
         end
 
-        def reduce_indices(indices)
-          if indices.empty? || indices.all?(&method(:integer?))
-            indices.sum
+        def reduce_indexes(indexes)
+          if indexes.empty? || indexes.all?(&method(:integer?))
+            indexes.sum
           else
-            indices.join('+')
+            indexes.join('+')
           end
         end
 

data/lib/rggen/systemverilog/rtl.rb

@@ -21,11 +21,11 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
   end
 
   plugin.files [
-    'rtl/global/array_port_format',
     'rtl/register_block/sv_rtl_top',
     'rtl/register_block/protocol',
     'rtl/register_block/protocol/apb',
     'rtl/register_block/protocol/axi4lite',
+    'rtl/register_block/protocol/avalon',
     'rtl/register_block/protocol/wishbone',
     'rtl/register_block/protocol/native',
     'rtl/register_file/sv_rtl_top',

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.34.0'
+    VERSION = '0.35.0'
   end
 end

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.34.0
+  version: 0.35.0
 platform: ruby
 authors:
 - Taichi Ishitani
 bindir: bin
 cert_chain: []
-date: 2025-01-23 00:00:00.000000000 Z
+date: 2025-02-19 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -102,7 +102,6 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/bit_field_index.rb
 - lib/rggen/systemverilog/rtl/feature.rb
-- lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/indirect_index.rb
 - lib/rggen/systemverilog/rtl/partial_sum.rb
 - lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb
@@ -117,6 +116,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/avalon.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/avalon.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/native.erb
@@ -158,5 +159,5 @@ required_rubygems_version: !ruby/object:Gem::Requirement
 requirements: []
 rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-systemverilog-0.34.0
+summary: rggen-systemverilog-0.35.0
 test_files: []

data/lib/rggen/systemverilog/rtl/global/array_port_format.rb

@@ -1,21 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_simple_feature(:global, :array_port_format) do
-  configuration do
-    property :array_port_format, default: :packed
-
-    input_pattern /(packed|unpacked|serialized)/i
-    ignore_empty_value false
-
-    build do |value|
-      @array_port_format =
-        if pattern_matched?
-          match_data[1].downcase.to_sym
-        else
-          error "illegal input value for array port format: #{value.inspect}"
-        end
-    end
-
-    printable :array_port_format
-  end
-end