rggen-systemverilog 0.33.1 → 0.34.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2024 Taichi Ishitani
+Copyright (c) 2019-2025 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2024 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2025 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common/feature.rb

@@ -38,9 +38,9 @@ module RgGen
           @package_imports = Hash.new { |h, k| h[k] = [] }
         end
 
-        def define_entity(context, name, args, &block)
+        def define_entity(context, name, args, &)
           layer, attributes = parse_entity_arguments(args)
-          entity = create_entity(context, name, attributes, &block)
+          entity = create_entity(context, name, attributes, &)
           add_entity(context, entity, name, layer)
         end
 
@@ -56,9 +56,9 @@ module RgGen
           end
         end
 
-        def create_entity(context, name, attributes, &block)
-          merged_attributes = { name: name }.merge(Hash(attributes))
-          __send__(context.method_name, context.entity_type, merged_attributes, &block)
+        def create_entity(context, name, attributes, &)
+          merged_attributes = { name: }.merge(Hash(attributes))
+          __send__(context.method_name, context.entity_type, merged_attributes, &)
         end
 
         def add_entity(context, entity, name, layer)

data/lib/rggen/systemverilog/common/utility/data_object.rb

@@ -86,7 +86,7 @@ module RgGen
           end
 
           def serialized_array_size
-            size = [(width || 1), *array_size]
+            size = [width || 1, *array_size]
             if size.all? { |s| s.is_a?(Integer) }
               [size.inject(&:*)]
             else

data/lib/rggen/systemverilog/common/utility/structure_definition.rb

@@ -7,9 +7,9 @@ module RgGen
         class StructureDefinition < Core::Utility::CodeUtility::StructureDefinition
           include Core::Utility::AttributeSetter
 
-          def initialize(default_attributes = {}, &block)
+          def initialize(default_attributes = {}, &)
             apply_attributes(**default_attributes)
-            super(&block)
+            super(&)
           end
 
           private

data/lib/rggen/systemverilog/common/utility.rb

@@ -92,7 +92,7 @@ module RgGen
         end
 
         def argument(name, attribute = {})
-          DataObject.new(:argument, attribute.merge(name: name)).declaration
+          DataObject.new(:argument, attribute.merge(name:)).declaration
         end
 
         {
@@ -103,7 +103,7 @@ module RgGen
           package_definition: PackageDefinition
         }.each do |method_name, definition|
           define_method(method_name) do |name, attributes = {}, &block|
-            definition.new(attributes.merge(name: name), &block).to_code
+            definition.new(attributes.merge(name:), &block).to_code
           end
         end
       end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -4,12 +4,12 @@ RgGen.define_list_feature(:bit_field, :type) do
   sv_ral do
     base_feature do
       define_helpers do
-        def access(access_type = nil, &block)
-          attribute_accessor('@access', access_type, &block)
+        def access(access_type = nil, &)
+          attribute_accessor('@access', access_type, &)
         end
 
-        def model_name(name = nil, &block)
-          attribute_accessor('@model_name', name, &block)
+        def model_name(name = nil, &)
+          attribute_accessor('@model_name', name, &)
         end
 
         private
@@ -28,7 +28,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       build do
         variable :ral_model, {
           name: bit_field.name, data_type: model_name,
-          array_size: array_size, random: true
+          array_size:, random: true
         }
       end
 

data/lib/rggen/systemverilog/ral/feature.rb

@@ -6,14 +6,12 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(_, attributes, &block)
-          DataObject.new(
-            :variable, attributes.merge(array_format: :unpacked), &block
-          )
+        def create_variable(_, attributes, &)
+          DataObject.new(:variable, attributes.merge(array_format: :unpacked), &)
         end
 
-        def create_parameter(_, attributes, &block)
-          DataObject.new(:parameter, attributes, &block)
+        def create_parameter(_, attributes, &)
+          DataObject.new(:parameter, attributes, &)
         end
 
         define_entity :variable, :create_variable, :variable, -> { component.parent }

data/lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb

@@ -26,7 +26,7 @@ RgGen.define_simple_feature(:register_block, :sv_ral_model) do
     end
 
     def byte_width
-      configuration.byte_width
+      register_block.byte_width
     end
 
     def child_model_constructors

data/lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb

@@ -47,7 +47,7 @@ RgGen.define_simple_feature(:register_file, :sv_ral_model) do
     end
 
     def byte_width
-      configuration.byte_width
+      register_block.byte_width
     end
 
     def child_model_constructors

data/lib/rggen/systemverilog/ral.rb

@@ -1,6 +1,7 @@
 # frozen_string_literal: true
 
 require_relative 'common'
+require_relative 'register_map/keyword_checker'
 require_relative 'ral/feature'
 require_relative 'ral/register_common'
 
@@ -30,4 +31,8 @@ RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
     'ral/bit_field/type/rwc_rwhw_rws',
     'ral/bit_field/type/rwe_rwl'
   ]
+
+  plugin.files [
+    'register_map/name'
+  ]
 end

data/lib/rggen/systemverilog/register_map/keyword_checker.rb

@@ -0,0 +1,62 @@
+# frozen_string_literal: true
+
+module RgGen
+  module SystemVerilog
+    module RegisterMap
+      module KeywordChecker
+        SYSTEMVERILOG_KEYWORDS = [
+          'accept_on', 'alias', 'always', 'always_comb', 'always_ff', 'always_latch',
+          'and', 'assert', 'assign', 'assume', 'automatic', 'before', 'begin', 'bind',
+          'bins', 'binsof', 'bit', 'break', 'buf', 'bufif0', 'bufif1', 'byte', 'case',
+          'casex', 'casez', 'cell', 'chandle', 'checker', 'class', 'clocking', 'cmos',
+          'config', 'const', 'constraint', 'context', 'continue', 'cover', 'covergroup',
+          'coverpoint', 'cross', 'deassign', 'default', 'defparam', 'design', 'disable',
+          'dist', 'do', 'edge', 'else', 'end', 'endcase', 'endchecker', 'endclass',
+          'endclocking', 'endconfig', 'endfunction', 'endgenerate', 'endgroup',
+          'endinterface', 'endmodule', 'endpackage', 'endprimitive', 'endprogram',
+          'endproperty', 'endspecify', 'endsequence', 'endtable', 'endtask', 'enum',
+          'event', 'eventually', 'expect', 'export', 'extends', 'extern', 'final',
+          'first_match', 'for', 'force', 'foreach', 'forever', 'fork', 'forkjoin',
+          'function', 'generate', 'genvar', 'global', 'highz0', 'highz1', 'if', 'iff',
+          'ifnone', 'ignore_bins', 'illegal_bins', 'implements', 'implies', 'import',
+          'incdir', 'include', 'initial', 'inout', 'input', 'inside', 'instance', 'int',
+          'integer', 'interconnect', 'interface', 'intersect', 'join', 'join_any',
+          'join_none', 'large', 'let', 'liblist', 'library', 'local', 'localparam',
+          'logic', 'longint', 'macromodule', 'matches', 'medium', 'modport', 'module',
+          'nand', 'negedge', 'nettype', 'new', 'nexttime', 'nmos', 'nor',
+          'noshowcancelled', 'not', 'notif0', 'notif1', 'null', 'or', 'output', 'package',
+          'packed', 'parameter', 'pmos', 'posedge', 'primitive', 'priority', 'program',
+          'property', 'protected', 'pull0', 'pull1', 'pulldown', 'pullup',
+          'pulsestyle_ondetect', 'pulsestyle_onevent', 'pure', 'rand', 'randc',
+          'randcase', 'randsequence', 'rcmos', 'real', 'realtime', 'ref', 'reg',
+          'reject_on', 'release', 'repeat', 'restrict', 'return', 'rnmos', 'rpmos',
+          'rtran', 'rtranif0', 'rtranif1', 's_always', 's_eventually', 's_nexttime',
+          's_until', 's_until_with', 'scalared', 'sequence', 'shortint', 'shortreal',
+          'showcancelled', 'signed', 'small', 'soft', 'solve', 'specify', 'specparam',
+          'static', 'string', 'strong', 'strong0', 'strong1', 'struct', 'super',
+          'supply0', 'supply1', 'sync_accept_on', 'sync_reject_on', 'table', 'tagged',
+          'task', 'this', 'throughout', 'time', 'timeprecision', 'timeunit', 'tran',
+          'tranif0', 'tranif1', 'tri', 'tri0', 'tri1', 'triand', 'trior', 'trireg',
+          'type', 'typedef', 'union', 'unique', 'unique0', 'unsigned', 'until',
+          'until_with', 'untyped', 'use', 'uwire', 'var', 'vectored', 'virtual',
+          'void', 'wait', 'wait_order', 'wand', 'weak', 'weak0', 'weak1', 'while',
+          'wildcard', 'wire', 'with', 'within', 'wor', 'xnor', 'xor'
+        ].freeze
+
+        def self.included(klass)
+          klass.class_eval do
+            verify(:feature, prepend: true) do
+              error_condition do
+                @name && SYSTEMVERILOG_KEYWORDS.include?(@name)
+              end
+              message do
+                layer_name = component.layer.to_s.sub('_', ' ')
+                "systemverilog keyword is not allowed for #{layer_name} name: #{@name}"
+              end
+            end
+          end
+        end
+      end
+    end
+  end
+end

data/lib/rggen/systemverilog/register_map/name.rb

@@ -0,0 +1,9 @@
+# frozen_string_literal: true
+
+[:register_block, :register_file, :register, :bit_field].each do |layer|
+  RgGen.modify_simple_feature(layer, :name) do
+    register_map do
+      include RgGen::SystemVerilog::RegisterMap::KeywordChecker
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/custom.rb

@@ -5,47 +5,47 @@ RgGen.define_list_item_feature(:bit_field, :type, :custom) do
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       else
         output :value_out, {
-          name: "o_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
           name: "i_#{full_name}_hw_write_enable", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_hw_write_data", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_hw_set", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}_hw_clear", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -4,17 +4,17 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
   sv_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}_set", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "o_#{full_name}_unmasked", width:,
+          array_size:, array_format: array_port_format
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb

@@ -5,14 +5,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:ro, :rotrg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if rotrg?
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rohw.rb

@@ -6,16 +6,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rohw) do
       unless bit_field.reference?
         input :valid, {
           name: "i_#{full_name}_valid", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb

@@ -5,13 +5,13 @@ RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb

@@ -4,23 +4,23 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rowo, :rowotrg]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width,
-          array_size: array_size, array_format: array_port_format
+          name: "i_#{full_name}", width:,
+          array_size:, array_format: array_port_format
         }
       end
       if rowotrg?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -4,12 +4,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
   sv_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}_clear", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_rwtrg_w1.rb

@@ -4,17 +4,17 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :rwtrg, :w1]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       if rwtrg?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
         output :read_trigger, {
           name: "o_#{full_name}_read_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb

@@ -6,12 +6,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwc) do
       unless bit_field.reference?
         input :clear, {
           name: "i_#{full_name}_clear", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb

@@ -6,12 +6,12 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rwe, :rwl]) do
       unless bit_field.reference?
         input :control, {
           name: "i_#{full_name}_#{enable_or_lock}", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rwhw.rb

@@ -6,16 +6,16 @@ RgGen.define_list_item_feature(:bit_field, :type, :rwhw) do
       unless bit_field.reference?
         input :valid, {
           name: "i_#{full_name}_valid", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "i_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.rb

@@ -6,12 +6,12 @@ RgGen.define_list_item_feature(:bit_field, :type, :rws) do
       unless bit_field.reference?
         input :set, {
           name: "i_#{full_name}_set", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -6,8 +6,8 @@ RgGen.define_list_item_feature(
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -4,8 +4,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb

@@ -4,8 +4,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0trg, :w1trg]) do
   sv_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}_trigger", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/bit_field/type/wo_wo1_wotrg.rb

@@ -4,13 +4,13 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1, :wotrg]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
       if wotrg?
         output :write_trigger, {
           name: "o_#{full_name}_write_trigger", width: 1,
-          array_size: array_size, array_format: array_port_format
+          array_size:, array_format: array_port_format
         }
       end
     end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -4,8 +4,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
   sv_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width,
-        array_size: array_size, array_format: array_port_format
+        name: "o_#{full_name}", width:,
+        array_size:, array_format: array_port_format
       }
     end
 

data/lib/rggen/systemverilog/rtl/feature.rb

@@ -6,32 +6,28 @@ module RgGen
       class Feature < Common::Feature
         private
 
-        def create_variable(data_type, attributes, &block)
-          DataObject.new(
-            :variable, attributes.merge(data_type: data_type), &block
-          )
+        def create_variable(data_type, attributes, &)
+          DataObject.new(:variable, attributes.merge(data_type:), &)
         end
 
-        def create_if_instance(_, attributes, &block)
-          InterfaceInstance.new(attributes, &block)
+        def create_if_instance(_, attributes, &)
+          InterfaceInstance.new(attributes, &)
         end
 
-        def create_port(direction, attributes, &block)
+        def create_port(direction, attributes, &)
           attributes =
             { data_type: 'logic' }
               .merge(attributes)
-              .merge(direction: direction)
-          DataObject.new(:argument, attributes, &block)
+              .merge(direction:)
+          DataObject.new(:argument, attributes, &)
         end
 
-        def create_if_port(_, attributes, &block)
-          InterfacePort.new(attributes, &block)
+        def create_if_port(_, attributes, &)
+          InterfacePort.new(attributes, &)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
-          DataObject.new(
-            :parameter, attributes.merge(parameter_type: parameter_type), &block
-          )
+        def create_parameter(parameter_type, attributes, &)
+          DataObject.new(:parameter, attributes.merge(parameter_type:), &)
         end
 
         define_entity :logic, :create_variable, :variable, -> { component }

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register, :type, :external) do
     build do
       parameter :strobe_width, {
         name: "#{register.name}_strobe_width".upcase,
-        data_type: :int, default: configuration.bus_width / 8
+        data_type: :int, default: bus_width / 8
       }
       interface_port :bus_if, {
         name: "#{register.name}_bus_if",

data/lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb

@@ -1,21 +1,27 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :apb) do
-  configuration do
+  register_map do
     verify(:component) do
-      error_condition { configuration.bus_width > 32 }
+      error_condition { register_block.bus_width > 32 }
       message do
-        'bus width over 32 bit is not supported: ' \
-        "#{configuration.bus_width}"
+        'bus width over 32 bits is not supported: ' \
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
       end
     end
 
     verify(:component) do
       error_condition { configuration.address_width > 32 }
       message do
-        'address width over 32 bit is not supported: ' \
+        'address width over 32 bits is not supported: ' \
         "#{configuration.address_width}"
       end
+      position do
+        configuration.feature(:address_width).position
+      end
     end
   end
 

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -1,12 +1,15 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
-  configuration do
+  register_map do
     verify(:component) do
-      error_condition { ![32, 64].include?(configuration.bus_width) }
+      error_condition { ![32, 64].include?(register_block.bus_width) }
       message do
         'bus width either 32 bit or 64 bit is only supported: ' \
-        "#{configuration.bus_width}"
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol/native.erb

@@ -0,0 +1,18 @@
+rggen_native_adapter #(
+  .ADDRESS_WIDTH        (<%= address_width %>),
+  .LOCAL_ADDRESS_WIDTH  (<%= local_address_width %>),
+  .BUS_WIDTH            (<%= bus_width %>),
+  .STROBE_WIDTH         (<%= strobe_width %>),
+  .REGISTERS            (<%= total_registers %>),
+  .PRE_DECODE           (<%= pre_decode %>),
+  .BASE_ADDRESS         (<%= base_address %>),
+  .BYTE_SIZE            (<%= byte_size %>),
+  .ERROR_STATUS         (<%= error_status %>),
+  .DEFAULT_READ_DATA    (<%= default_read_data %>),
+  .INSERT_SLICER        (<%= insert_slicer %>)
+) u_adapter (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .csrbus_if    (<%= csrbus_if %>),
+  .register_if  (<%= register_if %>)
+);

data/lib/rggen/systemverilog/rtl/register_block/protocol/native.rb

@@ -0,0 +1,16 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register_block, :protocol, :native) do
+  sv_rtl do
+    build do
+      parameter :strobe_width, {
+        name: 'STROBE_WIDTH', data_type: :int, default: bus_width / 8
+      }
+      interface_port :csrbus_if, {
+        name: 'csrbus_if', interface_type: 'rggen_bus_if', modport: 'slave'
+      }
+    end
+
+    main_code :register_block, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb

@@ -1,12 +1,15 @@
 # frozen_string_literal: true
 
 RgGen.define_list_item_feature(:register_block, :protocol, :wishbone) do
-  configuration do
+  register_map do
     verify(:component) do
-      error_condition { configuration.bus_width > 64 }
+      error_condition { register_block.bus_width > 64 }
       message do
-        'bus width over 64 bit is not supported: ' \
-        "#{configuration.bus_width}"
+        'bus width over 64 bits is not supported: ' \
+        "#{register_block.bus_width}"
+      end
+      position do
+        register_block.feature(:bus_width).position
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -6,57 +6,76 @@ RgGen.define_list_feature(:register_block, :protocol) do
       feature_registries << registry
     end
 
+    def default_protocol
+      available_protocols.first
+    end
+
+    def find_protocol(value)
+      available_protocols
+        .find { value.to_sym.casecmp?(_1) }
+    end
+
+    private
+
+    def feature_registries
+      @feature_registries ||= []
+    end
+
     def available_protocols
       feature_registries
         .map { |registry| registry.enabled_features(:protocol) }
         .inject(:&)
     end
+  end
 
-    private
+  [:configuration, :register_map].each do |component_type|
+    component(component_type) do
+      base_feature do
+        build { |protocol| @protocol = protocol }
+      end
 
-    def feature_registries
-      @feature_registries ||= []
+      default_feature do
+      end
+
+      factory do
+        convert_value do |value, position|
+          shared_context.find_protocol(value) ||
+            (error "unknown protocol: #{value.inspect}", position)
+        end
+      end
     end
   end
 
   configuration do
     base_feature do
       property :protocol
-      build { |protocol| @protocol = protocol }
       printable :protocol
     end
 
-    default_feature do
-    end
-
     factory do
-      convert_value do |value, position|
-        protocol = find_protocol(value)
-        protocol ||
-          (error "unknown protocol: #{value.inspect}", position)
-      end
-
       default_value do |position|
-        default_protocol ||
+        shared_context.default_protocol ||
           (error 'no protocols are available', position)
       end
 
       def target_feature_key(data)
         data.value
       end
+    end
+  end
 
-      private
-
-      def find_protocol(value)
-        available_protocols.find(&value.to_sym.method(:casecmp?))
-      end
+  register_map do
+    base_feature do
+      property :protocol, default: -> { configuration.protocol }
 
-      def default_protocol
-        available_protocols.first
+      def position
+        super || configuration.feature(:protocol).position
       end
+    end
 
-      def available_protocols
-        @available_protocols ||= shared_context.available_protocols
+    factory do
+      def target_feature_key(configuration, data)
+        data&.value || configuration.protocol
       end
     end
   end
@@ -91,7 +110,7 @@ RgGen.define_list_feature(:register_block, :protocol) do
       private
 
       def bus_width
-        configuration.bus_width
+        register_block.bus_width
       end
 
       def local_address_width
@@ -120,8 +139,8 @@ RgGen.define_list_feature(:register_block, :protocol) do
     end
 
     factory do
-      def target_feature_key(configuration, _register_block)
-        configuration.protocol
+      def target_feature_key(_configuration, register_block)
+        register_block.protocol
       end
     end
   end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -34,7 +34,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def bus_width
-      configuration.bus_width
+      register_block.bus_width
     end
 
     def body_code(code)

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -21,7 +21,7 @@ module RgGen
         end
 
         def bus_width
-          configuration.bus_width
+          register_block.bus_width
         end
 
         def value_width

data/lib/rggen/systemverilog/rtl.rb

@@ -1,6 +1,7 @@
 # frozen_string_literal: true
 
 require_relative 'common'
+require_relative 'register_map/keyword_checker'
 require_relative 'rtl/feature'
 require_relative 'rtl/partial_sum'
 require_relative 'rtl/register_index'
@@ -26,6 +27,7 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/register_block/protocol/apb',
     'rtl/register_block/protocol/axi4lite',
     'rtl/register_block/protocol/wishbone',
+    'rtl/register_block/protocol/native',
     'rtl/register_file/sv_rtl_top',
     'rtl/register/sv_rtl_top',
     'rtl/register/type',
@@ -66,4 +68,8 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl_package/register/sv_rtl_package',
     'rtl_package/register_block/sv_rtl_package'
   ]
+
+  plugin.files [
+    'register_map/name'
+  ]
 end

data/lib/rggen/systemverilog/rtl_package/feature.rb

@@ -10,14 +10,14 @@ module RgGen
           component.full_name(separator)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
+        def create_parameter(parameter_type, attributes, &)
           attributes =
             attributes.merge(
-              parameter_type: parameter_type, array_format: :unpacked,
+              parameter_type:, array_format: :unpacked,
               name: attributes[:name].upcase
             )
           DataObject.new(
-            :parameter, attributes, &block
+            :parameter, attributes, &
           )
         end
 

data/lib/rggen/systemverilog/rtl_package/register/sv_rtl_package.rb

@@ -41,7 +41,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_package) do
       value_list = group_address_list(address_list, size_list).first
       localparam :__offset, {
         name: "#{full_name}_byte_offset",
-        data_type: :bit, width: width, array_size: size_list, default: value_list
+        data_type: :bit, width:, array_size: size_list, default: value_list
       }
     end
 
@@ -68,7 +68,7 @@ RgGen.define_simple_feature(:register, :sv_rtl_package) do
       value = address_list.first
       localparam :__offset, {
         name: "#{full_name}_byte_offset",
-        data_type: :bit, width: width, default: value
+        data_type: :bit, width:, default: value
       }
     end
 

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.33.1'
+    VERSION = '0.34.0'
   end
 end

metadata

@@ -1,14 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.33.1
+  version: 0.34.0
 platform: ruby
 authors:
 - Taichi Ishitani
-autorequire: 
 bindir: bin
 cert_chain: []
-date: 2024-11-28 00:00:00.000000000 Z
+date: 2025-01-23 00:00:00.000000000 Z
 dependencies: []
 description: 'SystemVerilog RTL and UVM RAL model generators for RgGen.
 
@@ -60,6 +59,8 @@ files:
 - lib/rggen/systemverilog/ral/register_common.rb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
 - lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
+- lib/rggen/systemverilog/register_map/keyword_checker.rb
+- lib/rggen/systemverilog/register_map/name.rb
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
@@ -118,6 +119,8 @@ files:
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb
+- lib/rggen/systemverilog/rtl/register_block/protocol/native.erb
+- lib/rggen/systemverilog/rtl/register_block/protocol/native.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/wishbone.rb
 - lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb
@@ -139,7 +142,6 @@ metadata:
   rubygems_mfa_required: 'true'
   source_code_uri: https://github.com/rggen/rggen-systemverilog
   wiki_uri: https://github.com/rggen/rggen/wiki
-post_install_message: 
 rdoc_options: []
 require_paths:
 - lib
@@ -147,15 +149,14 @@ required_ruby_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
-      version: '3.0'
+      version: '3.1'
 required_rubygems_version: !ruby/object:Gem::Requirement
   requirements:
   - - ">="
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.5.16
-signing_key: 
+rubygems_version: 3.6.2
 specification_version: 4
-summary: rggen-systemverilog-0.33.1
+summary: rggen-systemverilog-0.34.0
 test_files: []