rggen-systemverilog 0.30.2 → 0.31.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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data/lib/rggen/systemverilog/rtl/register/type/external.erb

@@ -2,6 +2,7 @@ rggen_external_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .VALUE_WIDTH    (<%= value_width %>),
+  .STROBE_WIDTH   (<%= strobe_width %>),
   .START_ADDRESS  (<%= start_address %>),
   .BYTE_SIZE      (<%= byte_size %>)
 ) u_register (

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -3,10 +3,13 @@
 RgGen.define_list_item_feature(:register, :type, :external) do
   sv_rtl do
     build do
+      parameter :strobe_width, {
+        name: "#{register.name}_strobe_width".upcase,
+        data_type: :int, default: configuration.bus_width / 8
+      }
       interface_port :bus_if, {
         name: "#{register.name}_bus_if",
-        interface_type: 'rggen_bus_if',
-        modport: 'master'
+        interface_type: 'rggen_bus_if', modport: 'master'
       }
     end
 

data/lib/rggen/systemverilog/rtl/register/type/rw.erb

@@ -0,0 +1,14 @@
+rggen_default_register #(
+  .READABLE       (1),
+  .WRITABLE       (1),
+  .ADDRESS_WIDTH  (<%= address_width %>),
+  .OFFSET_ADDRESS (<%= offset_address %>),
+  .BUS_WIDTH      (<%= bus_width %>),
+  .DATA_WIDTH     (<%= width %>),
+  .VALUE_WIDTH    (<%= value_width %>)
+) u_register (
+  .i_clk        (<%= register_block.clock %>),
+  .i_rst_n      (<%= register_block.reset %>),
+  .register_if  (<%= register_if %>),
+  .bit_field_if (<%= bit_field_if %>)
+);

data/lib/rggen/systemverilog/rtl/register/type/rw.rb

@@ -0,0 +1,7 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:register, :type, :rw) do
+  sv_rtl do
+    main_code :register, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl.rb

@@ -31,6 +31,7 @@ RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
     'rtl/register/type',
     'rtl/register/type/external',
     'rtl/register/type/indirect',
+    'rtl/register/type/rw',
     'rtl/bit_field/sv_rtl_top',
     'rtl/bit_field/type',
     'rtl/bit_field/type/custom',

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.30.2'
+    VERSION = '0.31.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.30.2
+  version: 0.31.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-08-08 00:00:00.000000000 Z
+date: 2023-09-12 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -123,6 +123,8 @@ files:
 - lib/rggen/systemverilog/rtl/register/type/external.rb
 - lib/rggen/systemverilog/rtl/register/type/indirect.erb
 - lib/rggen/systemverilog/rtl/register/type/indirect.rb
+- lib/rggen/systemverilog/rtl/register/type/rw.erb
+- lib/rggen/systemverilog/rtl/register/type/rw.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol.rb
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.erb
 - lib/rggen/systemverilog/rtl/register_block/protocol/apb.rb
@@ -167,5 +169,5 @@ requirements: []
 rubygems_version: 3.4.17
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.30.2
+summary: rggen-systemverilog-0.31.0
 test_files: []