rggen-systemverilog 0.30.1 → 0.30.2

checksums.yaml

@@ -1,7 +1,7 @@
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data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -5,7 +5,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
     verify(:component) do
       error_condition { ![32, 64].include?(configuration.bus_width) }
       message do
-        'bus width eigher 32 bit or 64 bit is only supported: ' \
+        'bus width either 32 bit or 64 bit is only supported: ' \
         "#{configuration.bus_width}"
       end
     end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.30.1'
+    VERSION = '0.30.2'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.30.1
+  version: 0.30.2
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-06-09 00:00:00.000000000 Z
+date: 2023-08-08 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -164,8 +164,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.4.10
+rubygems_version: 3.4.17
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.30.1
+summary: rggen-systemverilog-0.30.2
 test_files: []