rggen-systemverilog 0.30.0 → 0.30.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: e4b82e5b367666fe0f1d9f62dd4d647348363bcee8f6749032010cc1ee20bd53
+  metadata.gz: eabc1a7fe3c4b18369e5a28a4b7cf3be8f3c39535bc675ccb96852142d23ea9f
+  data.tar.gz: 9cd3d819ee42f7f91a920694f74c1cafcd78b3727c762947adcefa4899100721
 SHA512:
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+  metadata.gz: 1798f396c34dedcba253e799ae1123c0e53c885b1a6378bff22a6cce9655dfd3793e119b532fbc8e97fbbf89405c5c6a5d5abaa2eed7881cb115361eb9424481
+  data.tar.gz: d8dc3fff2fd630f789a616ab3fb9880a8c8863d34ef21a0f6787ae0247db1ae451a161a7557957b33a51e9650ca7e47b2352ac4c3dcae1874b5a8b05dcd6ad7d

data/lib/rggen/systemverilog/common/utility.rb

@@ -87,6 +87,10 @@ module RgGen
           [width, bit_length].max
         end
 
+        def width_cast(expression, width)
+          "#{width}'(#{expression})"
+        end
+
         def argument(name, attribute = {})
           DataObject.new(:argument, attribute.merge(name: name)).declaration
         end

data/lib/rggen/systemverilog/rtl/register/type/default.erb

@@ -4,7 +4,8 @@ rggen_default_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
-  .DATA_WIDTH     (<%= width %>)
+  .DATA_WIDTH     (<%= width %>),
+  .VALUE_WIDTH    (<%= value_width %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),

data/lib/rggen/systemverilog/rtl/register/type/external.erb

@@ -1,8 +1,9 @@
 rggen_external_register #(
   .ADDRESS_WIDTH  (<%= address_width %>),
   .BUS_WIDTH      (<%= bus_width %>),
+  .VALUE_WIDTH    (<%= value_width %>),
   .START_ADDRESS  (<%= start_address %>),
-  .END_ADDRESS    (<%= end_address %>)
+  .BYTE_SIZE      (<%= byte_size %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),
   .i_rst_n      (<%= register_block.reset %>),

data/lib/rggen/systemverilog/rtl/register/type/external.rb

@@ -14,16 +14,12 @@ RgGen.define_list_item_feature(:register, :type, :external) do
 
     private
 
-    def byte_width
-      configuration.byte_width
-    end
-
     def start_address
       hex(register.address_range.begin, address_width)
     end
 
-    def end_address
-      hex(register.address_range.last, address_width)
+    def byte_size
+      register.total_byte_size
     end
   end
 end

data/lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -5,6 +5,7 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
+  .VALUE_WIDTH          (<%= value_width %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
 ) u_register (

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -26,11 +26,5 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
     end
 
     main_code :register_block, from_template: true
-
-    private
-
-    def id_port_width
-      "((#{id_width}>0)?#{id_width}:1)"
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol.rb

@@ -17,12 +17,6 @@ RgGen.define_list_feature(:register_block, :protocol) do
     def feature_registries
       @feature_registries ||= []
     end
-
-    def collect_available_protocols(registry)
-      registry
-        .enabled_features(:protocol)
-        .select { |protocol| registry.feature?(:protocol, protocol) }
-    end
   end
 
   configuration do
@@ -100,10 +94,6 @@ RgGen.define_list_feature(:register_block, :protocol) do
         configuration.bus_width
       end
 
-      def byte_width
-        configuration.byte_width
-      end
-
       def local_address_width
         register_block.local_address_width
       end

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -12,7 +12,7 @@
   if (1) begin : __g_tie_off \
     genvar  __i; \
     for (__i = 0;__i < WIDTH;++__i) begin : g \
-      if (!(((VALID_BITS) >> __i) & 1'b1)) begin : g \
+      if ((((VALID_BITS) >> __i) % 2) == 0) begin : g \
         assign  RIF.read_data[__i]  = 1'b0; \
         assign  RIF.value[__i]      = 1'b0; \
       end \

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -3,6 +3,7 @@
 RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
   sv_rtl do
     export :total_registers
+    export :value_width
 
     build do
       input :clock, { name: 'i_clk', width: 1 }
@@ -19,7 +20,11 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block.files_and_registers.sum(&:count)
+      @total_registers ||= register_block.files_and_registers.sum(&:count)
+    end
+
+    def value_width
+      @value_width ||= register_block.registers.map(&:width).max
     end
 
     private
@@ -32,10 +37,6 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
       configuration.bus_width
     end
 
-    def value_width
-      register_block.registers.map(&:width).max
-    end
-
     def body_code(code)
       macro_definition(code)
       sv_module_definition(code)

data/lib/rggen/systemverilog/rtl/register_type.rb

@@ -16,10 +16,18 @@ module RgGen
           register.writable? && 1 || 0
         end
 
+        def width
+          register.width
+        end
+
         def bus_width
           configuration.bus_width
         end
 
+        def value_width
+          register_block.value_width
+        end
+
         def address_width
           register_block.local_address_width
         end
@@ -62,16 +70,15 @@ module RgGen
         end
 
         def format_offset(offset)
-          offset.is_a?(Integer) ? hex(offset, address_width) : offset
-        end
-
-        def width
-          register.width
+          case offset
+          when Integer then hex(offset, address_width)
+          else width_cast(offset, address_width)
+          end
         end
 
         def valid_bits
           bits = register.bit_fields.map(&:bit_map).inject(:|)
-          hex(bits, register.width)
+          hex(bits, width)
         end
       end
     end

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.30.0'
+    VERSION = '0.30.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.30.0
+  version: 0.30.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2023-04-28 00:00:00.000000000 Z
+date: 2023-06-09 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -167,5 +167,5 @@ requirements: []
 rubygems_version: 3.4.10
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.30.0
+summary: rggen-systemverilog-0.30.1
 test_files: []