rggen-systemverilog 0.26.1 → 0.27.0
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- checksums.yaml +4 -4
- data/README.md +2 -1
- data/lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb +5 -0
- data/lib/rggen/systemverilog/ral.rb +24 -29
- data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb +30 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +38 -43
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +7 -6
- data/lib/rggen/systemverilog/ral/setup.rb +0 -8
- data/lib/rggen/systemverilog/rtl/setup.rb +0 -12
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: e21904c762e6894ce703b9786419aad14e0a8be86ace5d6ee098499ef57eeb06
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data.tar.gz: a8c2b427a10ef057d2220b049f733561f1b0fd16052ef7166309b1bd3e58fd72
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 6b146bfee049359f9e8296684d1beb785dbf1567cc2d3ac75effcb26bce7a9068b0371904af583ab58e19562a332727731d277c51e117c056d68bba87e9b6bc2
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data.tar.gz: 63eaedf2f45061b5af697700a3b577298c470cb078e45ae59e7dd41cf552f1607e9c5a553ecede94f1b3e49b96b386f0af6326fcdd0715b6a187a4c1aad954fa
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data/README.md
CHANGED
@@ -27,7 +27,8 @@ $ gem isntall rggen-systemverilog
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Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
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* [GitHub Issue Tracker](https://github.com/rggen/rggen
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+
* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
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* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
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* [Chat Room](https://gitter.im/rggen/rggen)
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* [Mailing List](https://groups.google.com/d/forum/rggen)
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* [Mail](mailto:rggen@googlegroups.com)
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@@ -4,35 +4,30 @@ require_relative 'common'
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4
4
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require_relative 'ral/feature'
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require_relative 'ral/register_common'
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6
6
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7
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-
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8
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-
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-
module RAL
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10
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-
extend Core::Plugin
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7
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+
RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
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8
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plugin.version RgGen::SystemVerilog::VERSION
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9
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-
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-
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-
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-
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-
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feature Feature, Common::FeatureFactory
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end
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-
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plugin.files [
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'ral/bit_field/type',
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-
'ral/bit_field/type/rof',
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-
'ral/bit_field/type/rotrg_rwtrg_wotrg',
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'ral/bit_field/type/rowo_rowotrg',
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'ral/bit_field/type/rwc_rws',
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'ral/bit_field/type/rwe_rwl',
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'ral/bit_field/type/w0trg_w1trg',
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'ral/register/type',
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'ral/register/type/external',
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'ral/register/type/indirect',
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'ral/register_block/sv_ral_model',
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'ral/register_block/sv_ral_package',
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'ral/register_file/sv_ral_model'
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]
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end
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36
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-
end
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10
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+
plugin.register_component :sv_ral do
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11
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+
component RgGen::SystemVerilog::Common::Component,
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+
RgGen::SystemVerilog::Common::ComponentFactory
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feature RgGen::SystemVerilog::RAL::Feature,
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RgGen::SystemVerilog::Common::FeatureFactory
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15
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end
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plugin.files [
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'ral/register_block/sv_ral_package',
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'ral/register_block/sv_ral_model',
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'ral/register_file/sv_ral_model',
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'ral/register/type',
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'ral/register/type/external',
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'ral/register/type/indirect',
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'ral/bit_field/type',
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'ral/bit_field/type/rof',
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'ral/bit_field/type/rotrg_rwtrg_wotrg',
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'ral/bit_field/type/row0trg_row1trg',
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'ral/bit_field/type/rowo_rowotrg',
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'ral/bit_field/type/rwc_rws',
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'ral/bit_field/type/rwe_rwl',
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'ral/bit_field/type/w0trg_w1trg'
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]
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end
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@@ -0,0 +1,10 @@
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1
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rggen_bit_field_w01trg #(
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2
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.TRIGGER_VALUE (<%= trigger_value %>),
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.WIDTH (<%= width %>)
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) u_bit_field (
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.i_clk (<%= clock %>),
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6
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.i_rst_n (<%= reset %>),
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7
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.bit_field_if (<%= bit_field_if %>),
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8
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.i_value (<%= reference_or_value_in %>),
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9
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.o_trigger (<%= trigger[loop_variables] %>)
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);
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@@ -0,0 +1,30 @@
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1
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# frozen_string_literal: true
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2
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3
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RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
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4
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sv_rtl do
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5
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build do
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6
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unless bit_field.reference?
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7
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input :value_in, {
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8
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name: "i_#{full_name}", width: width,
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9
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array_size: array_size, array_format: array_port_format
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}
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end
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output :trigger, {
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13
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name: "o_#{full_name}_trigger", width: width,
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array_size: array_size, array_format: array_port_format
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}
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end
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+
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main_code :bit_field, from_template: true
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private
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21
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def trigger_value
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23
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bin({ row0trg: 0, row1trg: 1 }[bit_field.type], 1)
|
24
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end
|
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+
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+
def reference_or_value_in
|
27
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reference_bit_field || value_in[loop_variables]
|
28
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+
end
|
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end
|
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end
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@@ -8,49 +8,44 @@ require_relative 'rtl/register_type'
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8
8
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require_relative 'rtl/indirect_index'
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9
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require_relative 'rtl/bit_field_index'
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10
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|
11
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-
|
12
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-
|
13
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-
module RTL
|
14
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-
extend Core::Plugin
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11
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+
RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
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12
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plugin.version RgGen::SystemVerilog::VERSION
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13
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-
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-
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-
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-
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-
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feature Feature, Common::FeatureFactory
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-
end
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-
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plugin.files [
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25
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'rtl/bit_field/sv_rtl_top',
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'rtl/bit_field/type',
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'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
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'rtl/bit_field/type/ro_rotrg',
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'rtl/bit_field/type/rof',
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30
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'rtl/bit_field/type/rowo_rowotrg',
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'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
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'rtl/bit_field/type/rw_rwtrg_w1',
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33
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'rtl/bit_field/type/rwc',
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34
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'rtl/bit_field/type/rwe_rwl',
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35
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-
'rtl/bit_field/type/rws',
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36
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-
'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
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37
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-
'rtl/bit_field/type/w0t_w1t',
|
38
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-
'rtl/bit_field/type/w0trg_w1trg',
|
39
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-
'rtl/bit_field/type/wo_wo1_wotrg',
|
40
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-
'rtl/bit_field/type/wrc_wrs',
|
41
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-
'rtl/global/array_port_format',
|
42
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-
'rtl/register/sv_rtl_top',
|
43
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-
'rtl/register/type',
|
44
|
-
'rtl/register/type/external',
|
45
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-
'rtl/register/type/indirect',
|
46
|
-
'rtl/register_block/protocol',
|
47
|
-
'rtl/register_block/protocol/apb',
|
48
|
-
'rtl/register_block/protocol/axi4lite',
|
49
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-
'rtl/register_block/protocol/wishbone',
|
50
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-
'rtl/register_block/sv_rtl_top',
|
51
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-
'rtl/register_file/sv_rtl_top'
|
52
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-
]
|
53
|
-
end
|
54
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-
end
|
14
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+
plugin.register_component :sv_rtl do
|
15
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+
component RgGen::SystemVerilog::Common::Component,
|
16
|
+
RgGen::SystemVerilog::Common::ComponentFactory
|
17
|
+
feature RgGen::SystemVerilog::RTL::Feature,
|
18
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+
RgGen::SystemVerilog::Common::FeatureFactory
|
55
19
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end
|
20
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+
|
21
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plugin.files [
|
22
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'rtl/global/array_port_format',
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23
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'rtl/register_block/sv_rtl_top',
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24
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'rtl/register_block/protocol',
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25
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'rtl/register_block/protocol/apb',
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26
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'rtl/register_block/protocol/axi4lite',
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27
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+
'rtl/register_block/protocol/wishbone',
|
28
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'rtl/register_file/sv_rtl_top',
|
29
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'rtl/register/sv_rtl_top',
|
30
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'rtl/register/type',
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31
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'rtl/register/type/external',
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32
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+
'rtl/register/type/indirect',
|
33
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'rtl/bit_field/sv_rtl_top',
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34
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'rtl/bit_field/type',
|
35
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'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
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36
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'rtl/bit_field/type/ro_rotrg',
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'rtl/bit_field/type/rof',
|
38
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'rtl/bit_field/type/row0trg_row1trg',
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39
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'rtl/bit_field/type/rowo_rowotrg',
|
40
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'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
|
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'rtl/bit_field/type/rw_rwtrg_w1',
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42
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'rtl/bit_field/type/rwc',
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43
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'rtl/bit_field/type/rwe_rwl',
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44
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'rtl/bit_field/type/rws',
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45
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'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
46
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'rtl/bit_field/type/w0t_w1t',
|
47
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'rtl/bit_field/type/w0trg_w1trg',
|
48
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'rtl/bit_field/type/wo_wo1_wotrg',
|
49
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'rtl/bit_field/type/wrc_wrs'
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50
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]
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51
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end
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metadata
CHANGED
@@ -1,14 +1,14 @@
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1
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--- !ruby/object:Gem::Specification
|
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2
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name: rggen-systemverilog
|
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3
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version: !ruby/object:Gem::Version
|
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-
version: 0.
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+
version: 0.27.0
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5
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platform: ruby
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6
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authors:
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7
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- Taichi Ishitani
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8
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autorequire:
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9
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bindir: bin
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cert_chain: []
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-
date: 2022-
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+
date: 2022-07-05 00:00:00.000000000 Z
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12
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dependencies:
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13
13
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- !ruby/object:Gem::Dependency
|
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14
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name: bundler
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@@ -57,6 +57,7 @@ files:
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57
57
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- lib/rggen/systemverilog/ral/bit_field/type.rb
|
58
58
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- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
|
59
59
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- lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
|
60
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+
- lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb
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61
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- lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
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62
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- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
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63
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- lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
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@@ -73,7 +74,6 @@ files:
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73
74
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- lib/rggen/systemverilog/ral/register_common.rb
|
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75
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- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
|
75
76
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- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
|
76
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-
- lib/rggen/systemverilog/ral/setup.rb
|
77
77
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- lib/rggen/systemverilog/rtl.rb
|
78
78
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- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
|
79
79
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- lib/rggen/systemverilog/rtl/bit_field/type.rb
|
@@ -83,6 +83,8 @@ files:
|
|
83
83
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- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
|
84
84
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- lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
|
85
85
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
|
86
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
|
87
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
|
86
88
|
- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
|
87
89
|
- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
|
88
90
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
|
@@ -129,13 +131,12 @@ files:
|
|
129
131
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- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
130
132
|
- lib/rggen/systemverilog/rtl/register_index.rb
|
131
133
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- lib/rggen/systemverilog/rtl/register_type.rb
|
132
|
-
- lib/rggen/systemverilog/rtl/setup.rb
|
133
134
|
- lib/rggen/systemverilog/version.rb
|
134
135
|
homepage: https://github.com/rggen/rggen-systemverilog
|
135
136
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licenses:
|
136
137
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- MIT
|
137
138
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metadata:
|
138
|
-
bug_tracker_uri: https://github.com/rggen/rggen
|
139
|
+
bug_tracker_uri: https://github.com/rggen/rggen/issues
|
139
140
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mailing_list_uri: https://groups.google.com/d/forum/rggen
|
140
141
|
rubygems_mfa_required: 'true'
|
141
142
|
source_code_uri: https://github.com/rggen/rggen-systemverilog
|
@@ -158,5 +159,5 @@ requirements: []
|
|
158
159
|
rubygems_version: 3.3.3
|
159
160
|
signing_key:
|
160
161
|
specification_version: 4
|
161
|
-
summary: rggen-systemverilog-0.
|
162
|
+
summary: rggen-systemverilog-0.27.0
|
162
163
|
test_files: []
|
@@ -1,12 +0,0 @@
|
|
1
|
-
# frozen_string_literal: true
|
2
|
-
|
3
|
-
require 'rggen/systemverilog/rtl'
|
4
|
-
|
5
|
-
RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
|
6
|
-
builder.enable :global, [:array_port_format]
|
7
|
-
builder.enable :register_block, [:sv_rtl_top, :protocol]
|
8
|
-
builder.enable :register_block, :protocol, [:apb, :axi4lite, :wishbone]
|
9
|
-
builder.enable :register_file, [:sv_rtl_top]
|
10
|
-
builder.enable :register, [:sv_rtl_top]
|
11
|
-
builder.enable :bit_field, [:sv_rtl_top]
|
12
|
-
end
|