rggen-systemverilog 0.26.1 → 0.27.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/README.md +2 -1
- data/lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb +5 -0
- data/lib/rggen/systemverilog/ral.rb +24 -29
- data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb +10 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb +30 -0
- data/lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb +1 -0
- data/lib/rggen/systemverilog/rtl/register_block/protocol.rb +2 -1
- data/lib/rggen/systemverilog/rtl.rb +38 -43
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +7 -6
- data/lib/rggen/systemverilog/ral/setup.rb +0 -8
- data/lib/rggen/systemverilog/rtl/setup.rb +0 -12
checksums.yaml
CHANGED
|
@@ -1,7 +1,7 @@
|
|
|
1
1
|
---
|
|
2
2
|
SHA256:
|
|
3
|
-
metadata.gz:
|
|
4
|
-
data.tar.gz:
|
|
3
|
+
metadata.gz: e21904c762e6894ce703b9786419aad14e0a8be86ace5d6ee098499ef57eeb06
|
|
4
|
+
data.tar.gz: a8c2b427a10ef057d2220b049f733561f1b0fd16052ef7166309b1bd3e58fd72
|
|
5
5
|
SHA512:
|
|
6
|
-
metadata.gz:
|
|
7
|
-
data.tar.gz:
|
|
6
|
+
metadata.gz: 6b146bfee049359f9e8296684d1beb785dbf1567cc2d3ac75effcb26bce7a9068b0371904af583ab58e19562a332727731d277c51e117c056d68bba87e9b6bc2
|
|
7
|
+
data.tar.gz: 63eaedf2f45061b5af697700a3b577298c470cb078e45ae59e7dd41cf552f1607e9c5a553ecede94f1b3e49b96b386f0af6326fcdd0715b6a187a4c1aad954fa
|
data/README.md
CHANGED
|
@@ -27,7 +27,8 @@ $ gem isntall rggen-systemverilog
|
|
|
27
27
|
|
|
28
28
|
Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
|
|
29
29
|
|
|
30
|
-
* [GitHub Issue Tracker](https://github.com/rggen/rggen
|
|
30
|
+
* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
|
|
31
|
+
* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
|
|
31
32
|
* [Chat Room](https://gitter.im/rggen/rggen)
|
|
32
33
|
* [Mailing List](https://groups.google.com/d/forum/rggen)
|
|
33
34
|
* [Mail](mailto:rggen@googlegroups.com)
|
|
@@ -4,35 +4,30 @@ require_relative 'common'
|
|
|
4
4
|
require_relative 'ral/feature'
|
|
5
5
|
require_relative 'ral/register_common'
|
|
6
6
|
|
|
7
|
-
|
|
8
|
-
|
|
9
|
-
module RAL
|
|
10
|
-
extend Core::Plugin
|
|
7
|
+
RgGen.setup_plugin :'rggen-sv-ral' do |plugin|
|
|
8
|
+
plugin.version RgGen::SystemVerilog::VERSION
|
|
11
9
|
|
|
12
|
-
|
|
13
|
-
|
|
14
|
-
|
|
15
|
-
|
|
16
|
-
|
|
17
|
-
feature Feature, Common::FeatureFactory
|
|
18
|
-
end
|
|
19
|
-
|
|
20
|
-
plugin.files [
|
|
21
|
-
'ral/bit_field/type',
|
|
22
|
-
'ral/bit_field/type/rof',
|
|
23
|
-
'ral/bit_field/type/rotrg_rwtrg_wotrg',
|
|
24
|
-
'ral/bit_field/type/rowo_rowotrg',
|
|
25
|
-
'ral/bit_field/type/rwc_rws',
|
|
26
|
-
'ral/bit_field/type/rwe_rwl',
|
|
27
|
-
'ral/bit_field/type/w0trg_w1trg',
|
|
28
|
-
'ral/register/type',
|
|
29
|
-
'ral/register/type/external',
|
|
30
|
-
'ral/register/type/indirect',
|
|
31
|
-
'ral/register_block/sv_ral_model',
|
|
32
|
-
'ral/register_block/sv_ral_package',
|
|
33
|
-
'ral/register_file/sv_ral_model'
|
|
34
|
-
]
|
|
35
|
-
end
|
|
36
|
-
end
|
|
10
|
+
plugin.register_component :sv_ral do
|
|
11
|
+
component RgGen::SystemVerilog::Common::Component,
|
|
12
|
+
RgGen::SystemVerilog::Common::ComponentFactory
|
|
13
|
+
feature RgGen::SystemVerilog::RAL::Feature,
|
|
14
|
+
RgGen::SystemVerilog::Common::FeatureFactory
|
|
37
15
|
end
|
|
16
|
+
|
|
17
|
+
plugin.files [
|
|
18
|
+
'ral/register_block/sv_ral_package',
|
|
19
|
+
'ral/register_block/sv_ral_model',
|
|
20
|
+
'ral/register_file/sv_ral_model',
|
|
21
|
+
'ral/register/type',
|
|
22
|
+
'ral/register/type/external',
|
|
23
|
+
'ral/register/type/indirect',
|
|
24
|
+
'ral/bit_field/type',
|
|
25
|
+
'ral/bit_field/type/rof',
|
|
26
|
+
'ral/bit_field/type/rotrg_rwtrg_wotrg',
|
|
27
|
+
'ral/bit_field/type/row0trg_row1trg',
|
|
28
|
+
'ral/bit_field/type/rowo_rowotrg',
|
|
29
|
+
'ral/bit_field/type/rwc_rws',
|
|
30
|
+
'ral/bit_field/type/rwe_rwl',
|
|
31
|
+
'ral/bit_field/type/w0trg_w1trg'
|
|
32
|
+
]
|
|
38
33
|
end
|
|
@@ -0,0 +1,10 @@
|
|
|
1
|
+
rggen_bit_field_w01trg #(
|
|
2
|
+
.TRIGGER_VALUE (<%= trigger_value %>),
|
|
3
|
+
.WIDTH (<%= width %>)
|
|
4
|
+
) u_bit_field (
|
|
5
|
+
.i_clk (<%= clock %>),
|
|
6
|
+
.i_rst_n (<%= reset %>),
|
|
7
|
+
.bit_field_if (<%= bit_field_if %>),
|
|
8
|
+
.i_value (<%= reference_or_value_in %>),
|
|
9
|
+
.o_trigger (<%= trigger[loop_variables] %>)
|
|
10
|
+
);
|
|
@@ -0,0 +1,30 @@
|
|
|
1
|
+
# frozen_string_literal: true
|
|
2
|
+
|
|
3
|
+
RgGen.define_list_item_feature(:bit_field, :type, [:row0trg, :row1trg]) do
|
|
4
|
+
sv_rtl do
|
|
5
|
+
build do
|
|
6
|
+
unless bit_field.reference?
|
|
7
|
+
input :value_in, {
|
|
8
|
+
name: "i_#{full_name}", width: width,
|
|
9
|
+
array_size: array_size, array_format: array_port_format
|
|
10
|
+
}
|
|
11
|
+
end
|
|
12
|
+
output :trigger, {
|
|
13
|
+
name: "o_#{full_name}_trigger", width: width,
|
|
14
|
+
array_size: array_size, array_format: array_port_format
|
|
15
|
+
}
|
|
16
|
+
end
|
|
17
|
+
|
|
18
|
+
main_code :bit_field, from_template: true
|
|
19
|
+
|
|
20
|
+
private
|
|
21
|
+
|
|
22
|
+
def trigger_value
|
|
23
|
+
bin({ row0trg: 0, row1trg: 1 }[bit_field.type], 1)
|
|
24
|
+
end
|
|
25
|
+
|
|
26
|
+
def reference_or_value_in
|
|
27
|
+
reference_bit_field || value_in[loop_variables]
|
|
28
|
+
end
|
|
29
|
+
end
|
|
30
|
+
end
|
|
@@ -8,49 +8,44 @@ require_relative 'rtl/register_type'
|
|
|
8
8
|
require_relative 'rtl/indirect_index'
|
|
9
9
|
require_relative 'rtl/bit_field_index'
|
|
10
10
|
|
|
11
|
-
|
|
12
|
-
|
|
13
|
-
module RTL
|
|
14
|
-
extend Core::Plugin
|
|
11
|
+
RgGen.setup_plugin :'rggen-sv-rtl' do |plugin|
|
|
12
|
+
plugin.version RgGen::SystemVerilog::VERSION
|
|
15
13
|
|
|
16
|
-
|
|
17
|
-
|
|
18
|
-
|
|
19
|
-
|
|
20
|
-
|
|
21
|
-
feature Feature, Common::FeatureFactory
|
|
22
|
-
end
|
|
23
|
-
|
|
24
|
-
plugin.files [
|
|
25
|
-
'rtl/bit_field/sv_rtl_top',
|
|
26
|
-
'rtl/bit_field/type',
|
|
27
|
-
'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
|
|
28
|
-
'rtl/bit_field/type/ro_rotrg',
|
|
29
|
-
'rtl/bit_field/type/rof',
|
|
30
|
-
'rtl/bit_field/type/rowo_rowotrg',
|
|
31
|
-
'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
|
|
32
|
-
'rtl/bit_field/type/rw_rwtrg_w1',
|
|
33
|
-
'rtl/bit_field/type/rwc',
|
|
34
|
-
'rtl/bit_field/type/rwe_rwl',
|
|
35
|
-
'rtl/bit_field/type/rws',
|
|
36
|
-
'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
|
37
|
-
'rtl/bit_field/type/w0t_w1t',
|
|
38
|
-
'rtl/bit_field/type/w0trg_w1trg',
|
|
39
|
-
'rtl/bit_field/type/wo_wo1_wotrg',
|
|
40
|
-
'rtl/bit_field/type/wrc_wrs',
|
|
41
|
-
'rtl/global/array_port_format',
|
|
42
|
-
'rtl/register/sv_rtl_top',
|
|
43
|
-
'rtl/register/type',
|
|
44
|
-
'rtl/register/type/external',
|
|
45
|
-
'rtl/register/type/indirect',
|
|
46
|
-
'rtl/register_block/protocol',
|
|
47
|
-
'rtl/register_block/protocol/apb',
|
|
48
|
-
'rtl/register_block/protocol/axi4lite',
|
|
49
|
-
'rtl/register_block/protocol/wishbone',
|
|
50
|
-
'rtl/register_block/sv_rtl_top',
|
|
51
|
-
'rtl/register_file/sv_rtl_top'
|
|
52
|
-
]
|
|
53
|
-
end
|
|
54
|
-
end
|
|
14
|
+
plugin.register_component :sv_rtl do
|
|
15
|
+
component RgGen::SystemVerilog::Common::Component,
|
|
16
|
+
RgGen::SystemVerilog::Common::ComponentFactory
|
|
17
|
+
feature RgGen::SystemVerilog::RTL::Feature,
|
|
18
|
+
RgGen::SystemVerilog::Common::FeatureFactory
|
|
55
19
|
end
|
|
20
|
+
|
|
21
|
+
plugin.files [
|
|
22
|
+
'rtl/global/array_port_format',
|
|
23
|
+
'rtl/register_block/sv_rtl_top',
|
|
24
|
+
'rtl/register_block/protocol',
|
|
25
|
+
'rtl/register_block/protocol/apb',
|
|
26
|
+
'rtl/register_block/protocol/axi4lite',
|
|
27
|
+
'rtl/register_block/protocol/wishbone',
|
|
28
|
+
'rtl/register_file/sv_rtl_top',
|
|
29
|
+
'rtl/register/sv_rtl_top',
|
|
30
|
+
'rtl/register/type',
|
|
31
|
+
'rtl/register/type/external',
|
|
32
|
+
'rtl/register/type/indirect',
|
|
33
|
+
'rtl/bit_field/sv_rtl_top',
|
|
34
|
+
'rtl/bit_field/type',
|
|
35
|
+
'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
|
|
36
|
+
'rtl/bit_field/type/ro_rotrg',
|
|
37
|
+
'rtl/bit_field/type/rof',
|
|
38
|
+
'rtl/bit_field/type/row0trg_row1trg',
|
|
39
|
+
'rtl/bit_field/type/rowo_rowotrg',
|
|
40
|
+
'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
|
|
41
|
+
'rtl/bit_field/type/rw_rwtrg_w1',
|
|
42
|
+
'rtl/bit_field/type/rwc',
|
|
43
|
+
'rtl/bit_field/type/rwe_rwl',
|
|
44
|
+
'rtl/bit_field/type/rws',
|
|
45
|
+
'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
|
|
46
|
+
'rtl/bit_field/type/w0t_w1t',
|
|
47
|
+
'rtl/bit_field/type/w0trg_w1trg',
|
|
48
|
+
'rtl/bit_field/type/wo_wo1_wotrg',
|
|
49
|
+
'rtl/bit_field/type/wrc_wrs'
|
|
50
|
+
]
|
|
56
51
|
end
|
metadata
CHANGED
|
@@ -1,14 +1,14 @@
|
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
|
2
2
|
name: rggen-systemverilog
|
|
3
3
|
version: !ruby/object:Gem::Version
|
|
4
|
-
version: 0.
|
|
4
|
+
version: 0.27.0
|
|
5
5
|
platform: ruby
|
|
6
6
|
authors:
|
|
7
7
|
- Taichi Ishitani
|
|
8
8
|
autorequire:
|
|
9
9
|
bindir: bin
|
|
10
10
|
cert_chain: []
|
|
11
|
-
date: 2022-
|
|
11
|
+
date: 2022-07-05 00:00:00.000000000 Z
|
|
12
12
|
dependencies:
|
|
13
13
|
- !ruby/object:Gem::Dependency
|
|
14
14
|
name: bundler
|
|
@@ -57,6 +57,7 @@ files:
|
|
|
57
57
|
- lib/rggen/systemverilog/ral/bit_field/type.rb
|
|
58
58
|
- lib/rggen/systemverilog/ral/bit_field/type/rof.rb
|
|
59
59
|
- lib/rggen/systemverilog/ral/bit_field/type/rotrg_rwtrg_wotrg.rb
|
|
60
|
+
- lib/rggen/systemverilog/ral/bit_field/type/row0trg_row1trg.rb
|
|
60
61
|
- lib/rggen/systemverilog/ral/bit_field/type/rowo_rowotrg.rb
|
|
61
62
|
- lib/rggen/systemverilog/ral/bit_field/type/rwc_rws.rb
|
|
62
63
|
- lib/rggen/systemverilog/ral/bit_field/type/rwe_rwl.rb
|
|
@@ -73,7 +74,6 @@ files:
|
|
|
73
74
|
- lib/rggen/systemverilog/ral/register_common.rb
|
|
74
75
|
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.erb
|
|
75
76
|
- lib/rggen/systemverilog/ral/register_file/sv_ral_model.rb
|
|
76
|
-
- lib/rggen/systemverilog/ral/setup.rb
|
|
77
77
|
- lib/rggen/systemverilog/rtl.rb
|
|
78
78
|
- lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
|
|
79
79
|
- lib/rggen/systemverilog/rtl/bit_field/type.rb
|
|
@@ -83,6 +83,8 @@ files:
|
|
|
83
83
|
- lib/rggen/systemverilog/rtl/bit_field/type/ro_rotrg.rb
|
|
84
84
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
|
|
85
85
|
- lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
|
|
86
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.erb
|
|
87
|
+
- lib/rggen/systemverilog/rtl/bit_field/type/row0trg_row1trg.rb
|
|
86
88
|
- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.erb
|
|
87
89
|
- lib/rggen/systemverilog/rtl/bit_field/type/rowo_rowotrg.rb
|
|
88
90
|
- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
|
|
@@ -129,13 +131,12 @@ files:
|
|
|
129
131
|
- lib/rggen/systemverilog/rtl/register_file/sv_rtl_top.rb
|
|
130
132
|
- lib/rggen/systemverilog/rtl/register_index.rb
|
|
131
133
|
- lib/rggen/systemverilog/rtl/register_type.rb
|
|
132
|
-
- lib/rggen/systemverilog/rtl/setup.rb
|
|
133
134
|
- lib/rggen/systemverilog/version.rb
|
|
134
135
|
homepage: https://github.com/rggen/rggen-systemverilog
|
|
135
136
|
licenses:
|
|
136
137
|
- MIT
|
|
137
138
|
metadata:
|
|
138
|
-
bug_tracker_uri: https://github.com/rggen/rggen
|
|
139
|
+
bug_tracker_uri: https://github.com/rggen/rggen/issues
|
|
139
140
|
mailing_list_uri: https://groups.google.com/d/forum/rggen
|
|
140
141
|
rubygems_mfa_required: 'true'
|
|
141
142
|
source_code_uri: https://github.com/rggen/rggen-systemverilog
|
|
@@ -158,5 +159,5 @@ requirements: []
|
|
|
158
159
|
rubygems_version: 3.3.3
|
|
159
160
|
signing_key:
|
|
160
161
|
specification_version: 4
|
|
161
|
-
summary: rggen-systemverilog-0.
|
|
162
|
+
summary: rggen-systemverilog-0.27.0
|
|
162
163
|
test_files: []
|
|
@@ -1,12 +0,0 @@
|
|
|
1
|
-
# frozen_string_literal: true
|
|
2
|
-
|
|
3
|
-
require 'rggen/systemverilog/rtl'
|
|
4
|
-
|
|
5
|
-
RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
|
|
6
|
-
builder.enable :global, [:array_port_format]
|
|
7
|
-
builder.enable :register_block, [:sv_rtl_top, :protocol]
|
|
8
|
-
builder.enable :register_block, :protocol, [:apb, :axi4lite, :wishbone]
|
|
9
|
-
builder.enable :register_file, [:sv_rtl_top]
|
|
10
|
-
builder.enable :register, [:sv_rtl_top]
|
|
11
|
-
builder.enable :bit_field, [:sv_rtl_top]
|
|
12
|
-
end
|