rggen-systemverilog 0.26.0 → 0.26.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 6093eea4b475c6dddb948d2b0bb5053705cc64f38a5603c925d0ab04029e0978
-  data.tar.gz: e2c07ce7eb68f15c9e4d2dbd0f83d7a74dbcb92ba292ba1fae8830c4ca147cb0
+  metadata.gz: 37662ce6857eb9237c7747e58b21d0dad5230a4879f88800b772cff8c5bb5b17
+  data.tar.gz: f9334ba40018bf2c057f5e9dfb97611958141ca19d776b95495cdf5ea1c18e64
 SHA512:
-  metadata.gz: 2d460b5eecdc50fbae20514b7f814fd98774b6dcb05ab72df2936301a9218870609eb1236b13f9a305d1882f001360eb84537b083c5323d2fde475fe170ffaed
-  data.tar.gz: 4ea6fb47189ec224f30701198d9a51de4ab68cbc2a601b048ad23b1edcda1308214218fd456550c2e8d085c3575ab2aeec7e58c43d6337dba81111c0e8f0b07f
+  metadata.gz: 14a6a6540f7ed433b53e48692942dc01ff684c1ad85497ce245c9d92cb3a75b2905ede3b81987e14596e7e5887b90bb8aed8dd7dd02deefbcce549eb5d5eb605
+  data.tar.gz: c62ebc166dafb2ef593a2b27f5bac1897071078d6ccb68f666a61d8bb793bcd57f10063b894426b987573907a0e85f85825bb1de58fb9566f4a95cd59ca2805f

data/lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb

@@ -36,10 +36,6 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
       end
     end
 
-    pre_code :bit_field do |code|
-      code << bit_field_if_connection << nl
-    end
-
     def value(offsets = nil, width = nil)
       value_lsb = bit_field.lsb(offsets&.last || local_index)
       value_width = width || bit_field.width
@@ -113,17 +109,5 @@ RgGen.define_simple_feature(:bit_field, :sv_rtl_top) do
     def body_code(code)
       bit_field.generate_code(code, :bit_field, :top_down)
     end
-
-    def bit_field_if_connection
-      macro_call(
-        'rggen_connect_bit_field_if',
-        [
-          register.bit_field_if,
-          bit_field.bit_field_sub_if,
-          bit_field.lsb(local_index),
-          bit_field.width
-        ]
-      )
-    end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -3,6 +3,10 @@
 RgGen.define_list_feature(:bit_field, :type) do
   sv_rtl do
     base_feature do
+      pre_code :bit_field do |code|
+        code << bit_field_if_connection << nl
+      end
+
       private
 
       def array_port_format
@@ -17,6 +21,10 @@ RgGen.define_list_feature(:bit_field, :type) do
         bit_field.width
       end
 
+      def lsb
+        bit_field.lsb(bit_field.local_index)
+      end
+
       def clock
         register_block.clock
       end
@@ -52,6 +60,13 @@ RgGen.define_list_feature(:bit_field, :type) do
       def loop_variables
         bit_field.loop_variables
       end
+
+      def bit_field_if_connection
+        macro_call(
+          'rggen_connect_bit_field_if',
+          [register.bit_field_if, bit_field_if, lsb, width]
+        )
+      end
     end
 
     factory do

data/lib/rggen/systemverilog/rtl/register/type/default.erb

@@ -5,7 +5,6 @@ rggen_default_register #(
   .OFFSET_ADDRESS (<%= offset_address %>),
   .BUS_WIDTH      (<%= bus_width %>),
   .DATA_WIDTH     (<%= width %>),
-  .VALID_BITS     (<%= valid_bits %>),
   .REGISTER_INDEX (<%= register_index %>)
 ) u_register (
   .i_clk        (<%= register_block.clock %>),

data/lib/rggen/systemverilog/rtl/register/type/indirect.erb

@@ -5,7 +5,6 @@ rggen_indirect_register #(
   .OFFSET_ADDRESS       (<%= offset_address %>),
   .BUS_WIDTH            (<%= bus_width %>),
   .DATA_WIDTH           (<%= width %>),
-  .VALID_BITS           (<%= valid_bits %>),
   .INDIRECT_INDEX_WIDTH (<%= index_width %>),
   .INDIRECT_INDEX_VALUE (<%= concat(index_values) %>)
 ) u_register (

data/lib/rggen/systemverilog/rtl/register/type.rb

@@ -5,6 +5,11 @@ RgGen.define_list_feature(:register, :type) do
     base_feature do
       include RgGen::SystemVerilog::RTL::RegisterType
 
+      pre_code :register do |code|
+        register.bit_fields.empty? ||
+          (code << tie_off_unused_signals << nl)
+      end
+
       private
 
       def register_if
@@ -14,6 +19,13 @@ RgGen.define_list_feature(:register, :type) do
       def bit_field_if
         register.bit_field_if
       end
+
+      def tie_off_unused_signals
+        macro_call(
+          'rggen_tie_off_unused_signals',
+          [width, valid_bits, bit_field_if]
+        )
+      end
     end
 
     default_feature do

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_macros.erb

@@ -7,3 +7,15 @@
   assign  RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
   assign  RIF.value[LSB+:WIDTH]     = FIF.value;
 `endif
+`ifndef rggen_tie_off_unused_signals
+  `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
+  if (1) begin : __g_tie_off \
+    genvar  __i; \
+    for (__i = 0;__i < WIDTH;++__i) begin : g \
+      if (!(((VALID_BITS) >> __i) & 1'b1)) begin : g \
+        assign  RIF.read_data[__i]  = 1'b0; \
+        assign  RIF.value[__i]      = 1'b0; \
+      end \
+    end \
+  end
+`endif

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.26.0'
+    VERSION = '0.26.1'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.26.0
+  version: 0.26.1
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2022-03-25 00:00:00.000000000 Z
+date: 2022-06-07 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -158,5 +158,5 @@ requirements: []
 rubygems_version: 3.3.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.26.0
+summary: rggen-systemverilog-0.26.1
 test_files: []