rggen-systemverilog 0.23.1 → 0.24.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/LICENSE

@@ -1,6 +1,6 @@
 The MIT License (MIT)
 
-Copyright (c) 2019-2020 Taichi Ishitani
+Copyright (c) 2019-2021 Taichi Ishitani
 
 Permission is hereby granted, free of charge, to any person obtaining a copy
 of this software and associated documentation files (the "Software"), to deal

data/README.md

@@ -34,7 +34,7 @@ Feedbacks, bug reports, questions and etc. are wellcome! You can post them by us
 
 ## Copyright & License
 
-Copyright © 2019-2020 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
+Copyright © 2019-2021 Taichi Ishitani. RgGen::SystemVerilog is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for futher details.
 
 ## Code of Conduct
 

data/lib/rggen/systemverilog/common.rb

@@ -1,6 +1,5 @@
 # frozen_string_literal: true
 
-require 'docile'
 require 'facets/kernel/attr_singleton'
 
 require_relative 'version'
@@ -21,24 +20,3 @@ require_relative 'common/utility'
 require_relative 'common/component'
 require_relative 'common/feature'
 require_relative 'common/factories'
-
-module RgGen
-  module SystemVerilog
-    module Common
-      def self.register_component(builder, name, feature_class)
-        builder.output_component_registry(name) do
-          register_component [
-            :root, :register_block, :register_file, :register, :bit_field
-          ] do |category|
-            component Component, ComponentFactory
-            feature feature_class, FeatureFactory if category != :root
-          end
-        end
-      end
-
-      def self.load_features(features, root)
-        features.each { |feature| require File.join(root, feature) }
-      end
-    end
-  end
-end

data/lib/rggen/systemverilog/common/feature.rb

@@ -8,7 +8,7 @@ module RgGen
         template_engine Core::OutputBase::ERBEngine
 
         EntityContext =
-          Struct.new(:entity_type, :method, :declaration_type, :default_layer)
+          Struct.new(:entity_type, :method_name, :declaration_type, :default_layer)
 
         class << self
           private
@@ -58,7 +58,7 @@ module RgGen
 
         def create_entity(context, name, attributes, &block)
           merged_attributes = { name: name }.merge(Hash(attributes))
-          __send__(context.method, context.entity_type, merged_attributes, &block)
+          __send__(context.method_name, context.entity_type, merged_attributes, &block)
         end
 
         def add_entity(context, entity, name, layer)

data/lib/rggen/systemverilog/common/utility.rb

@@ -45,6 +45,10 @@ module RgGen
           end
         end
 
+        def all_bits_1
+          "'1"
+        end
+
         def all_bits_0
           "'0"
         end

data/lib/rggen/systemverilog/ral.rb

@@ -7,37 +7,29 @@ require_relative 'ral/register_common'
 module RgGen
   module SystemVerilog
     module RAL
-      PLUGIN_NAME = :'rggen-sv-ral'
+      extend Core::Plugin
 
-      FEATURES = [
-        'ral/bit_field/type',
-        'ral/bit_field/type/reserved_rof',
-        'ral/bit_field/type/rwc_rws',
-        'ral/bit_field/type/rwe_rwl',
-        'ral/bit_field/type/w0trg_w1trg',
-        'ral/register/type',
-        'ral/register/type/external',
-        'ral/register/type/indirect',
-        'ral/register_block/sv_ral_model',
-        'ral/register_block/sv_ral_package',
-        'ral/register_file/sv_ral_model'
-      ].freeze
+      setup_plugin :'rggen-sv-ral' do |plugin|
+        plugin.version SystemVerilog::VERSION
 
-      def self.version
-        SystemVerilog::VERSION
-      end
-
-      def self.register_component(builder)
-        Common.register_component(builder, :sv_ral, Feature)
-      end
-
-      def self.load_features
-        Common.load_features(FEATURES, __dir__)
-      end
+        plugin.register_component :sv_ral do
+          component Common::Component, Common::ComponentFactory
+          feature Feature, Common::FeatureFactory
+        end
 
-      def self.default_setup(builder)
-        register_component(builder)
-        load_features
+        plugin.files [
+          'ral/bit_field/type',
+          'ral/bit_field/type/reserved_rof',
+          'ral/bit_field/type/rwc_rws',
+          'ral/bit_field/type/rwe_rwl',
+          'ral/bit_field/type/w0trg_w1trg',
+          'ral/register/type',
+          'ral/register/type/external',
+          'ral/register/type/indirect',
+          'ral/register_block/sv_ral_model',
+          'ral/register_block/sv_ral_package',
+          'ral/register_file/sv_ral_model'
+        ]
       end
     end
   end

data/lib/rggen/systemverilog/ral/bit_field/type.rb

@@ -29,7 +29,7 @@ RgGen.define_list_feature(:bit_field, :type) do
 
       def model_name
         name = helper.model_name
-        name&.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
+        name.is_a?(Proc) && instance_eval(&name) || name || :rggen_ral_field
       end
 
       def constructors

data/lib/rggen/systemverilog/ral/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/ral'
 
-RgGen.setup RgGen::SystemVerilog::RAL do |builder|
+RgGen.register_plugin RgGen::SystemVerilog::RAL do |builder|
   builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
   builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -11,54 +11,45 @@ require_relative 'rtl/bit_field_index'
 module RgGen
   module SystemVerilog
     module RTL
-      PLUGIN_NAME = :'rggen-sv-rtl'
+      extend Core::Plugin
 
-      FEATURES = [
-        'rtl/bit_field/sv_rtl_top',
-        'rtl/bit_field/type',
-        'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
-        'rtl/bit_field/type/reserved',
-        'rtl/bit_field/type/ro',
-        'rtl/bit_field/type/rof',
-        'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
-        'rtl/bit_field/type/rw_w1_wo_wo1',
-        'rtl/bit_field/type/rwc',
-        'rtl/bit_field/type/rwe',
-        'rtl/bit_field/type/rwl',
-        'rtl/bit_field/type/rws',
-        'rtl/bit_field/type/w0crs_w1crs_wcrs',
-        'rtl/bit_field/type/w0src_w1src_wsrc',
-        'rtl/bit_field/type/w0t_w1t',
-        'rtl/bit_field/type/w0trg_w1trg',
-        'rtl/bit_field/type/wrc_wrs',
-        'rtl/global/array_port_format',
-        'rtl/global/fold_sv_interface_port',
-        'rtl/register/sv_rtl_top',
-        'rtl/register/type',
-        'rtl/register/type/external',
-        'rtl/register/type/indirect',
-        'rtl/register_block/protocol',
-        'rtl/register_block/protocol/apb',
-        'rtl/register_block/protocol/axi4lite',
-        'rtl/register_block/sv_rtl_top',
-        'rtl/register_file/sv_rtl_top'
-      ].freeze
+      setup_plugin :'rggen-sv-rtl' do |plugin|
+        plugin.version SystemVerilog::VERSION
 
-      def self.version
-        SystemVerilog::VERSION
-      end
-
-      def self.register_component(builder)
-        Common.register_component(builder, :sv_rtl, Feature)
-      end
-
-      def self.load_features
-        Common.load_features(FEATURES, __dir__)
-      end
+        plugin.register_component :sv_rtl do
+          component Common::Component, Common::ComponentFactory
+          feature Feature, Common::FeatureFactory
+        end
 
-      def self.default_setup(builder)
-        register_component(builder)
-        load_features
+        plugin.files [
+          'rtl/bit_field/sv_rtl_top',
+          'rtl/bit_field/type',
+          'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
+          'rtl/bit_field/type/reserved',
+          'rtl/bit_field/type/ro',
+          'rtl/bit_field/type/rof',
+          'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
+          'rtl/bit_field/type/rw_w1_wo_wo1',
+          'rtl/bit_field/type/rwc',
+          'rtl/bit_field/type/rwe',
+          'rtl/bit_field/type/rwl',
+          'rtl/bit_field/type/rws',
+          'rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc',
+          'rtl/bit_field/type/w0t_w1t',
+          'rtl/bit_field/type/w0trg_w1trg',
+          'rtl/bit_field/type/wrc_wrs',
+          'rtl/global/array_port_format',
+          'rtl/global/fold_sv_interface_port',
+          'rtl/register/sv_rtl_top',
+          'rtl/register/type',
+          'rtl/register/type/external',
+          'rtl/register/type/indirect',
+          'rtl/register_block/protocol',
+          'rtl/register_block/protocol/apb',
+          'rtl/register_block/protocol/axi4lite',
+          'rtl/register_block/sv_rtl_top',
+          'rtl/register_file/sv_rtl_top'
+        ]
       end
     end
   end

data/lib/rggen/systemverilog/rtl/bit_field/type.rb

@@ -35,8 +35,7 @@ RgGen.define_list_feature(:bit_field, :type) do
       end
 
       def mask
-        reference_bit_field ||
-          hex(2**bit_field.width - 1, bit_field.width)
+        reference_bit_field || all_bits_1
       end
 
       def reference_bit_field

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb

@@ -1,16 +1,19 @@
-<%= module_name %> #(
-<% if bit_field.type != :rc %>
-  .CLEAR_VALUE    (<%= clear_value %>),
-  .WRITE_ONLY     (<%= write_only %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
 ) u_bit_field (
-  .i_clk            (<%= clock %>),
-  .i_rst_n          (<%= reset%>),
-  .bit_field_if     (<%= bit_field_if %>),
-  .i_set            (<%= set[loop_variables] %>),
-  .i_mask           (<%= mask %>),
-  .o_value          (<%= value_out[loop_variables] %>),
-  .o_value_unmasked (<%= value_out_unmasked %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= write_enable %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           (<%= set[loop_variables] %>),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             (<%= mask %>),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   (<%= value_out_unmasked %>)
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb

@@ -23,22 +23,32 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc])
 
     private
 
-    def module_name
-      bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
+    def read_action
+      {
+        rc: 'RGGEN_READ_CLEAR',
+        w0c: 'RGGEN_READ_DEFAULT',
+        w1c: 'RGGEN_READ_DEFAULT',
+        wc: 'RGGEN_READ_DEFAULT',
+        woc: 'RGGEN_READ_NONE'
+      }[bit_field.type]
     end
 
-    def clear_value
-      value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
-      bin(value, 2)
+    def write_action
+      {
+        rc: 'RGGEN_WRITE_NONE',
+        w0c: 'RGGEN_WRITE_0_CLEAR',
+        w1c: 'RGGEN_WRITE_1_CLEAR',
+        wc: 'RGGEN_WRITE_CLEAR',
+        woc: 'RGGEN_WRITE_CLEAR'
+      }[bit_field.type]
     end
 
-    def write_only
-      bit_field.write_only? && 1 || 0
+    def write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
     end
 
     def value_out_unmasked
-      (bit_field.reference? || nil) &&
-        value_unmasked[loop_variables]
+      (bit_field.reference? || nil) && value_unmasked[loop_variables]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb

@@ -1,3 +1,18 @@
-rggen_bit_field_reserved u_bit_field (
-  .bit_field_if (<%= bit_field_if %>)
+rggen_bit_field #(
+  .WIDTH          (<%= width %>),
+  .SW_READ_ACTION (RGGEN_READ_NONE),
+  .STORAGE        (0)
+) u_bit_field (
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('0),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/ro.erb

@@ -1,6 +1,17 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
+rggen_bit_field #(
+  .WIDTH    (<%= width %>),
+  .STORAGE  (0)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= reference_or_value_in %>)
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= reference_or_value_in %>),
+  .i_mask             ('1),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rof.erb

@@ -1,6 +1,17 @@
-rggen_bit_field_ro #(
-  .WIDTH  (<%= width %>)
+rggen_bit_field #(
+  .WIDTH    (<%= width %>),
+  .STORAGE  (0)
 ) u_bit_field (
-  .bit_field_if (<%= bit_field_if %>),
-  .i_value      (<%= initial_value %>)
+  .i_clk              ('0),
+  .i_rst_n            ('0),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('0),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            (<%= initial_value %>),
+  .i_mask             ('1),
+  .o_value            (),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb

@@ -1,14 +1,19 @@
-<%= module_name %> #(
-<% if bit_field.type != :rs %>
-  .SET_VALUE      (<%= set_value %>),
-  .WRITE_ONLY     (<%= write_only %>),
-<% end %>
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= write_enable %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         (<%= clear[loop_variables] %>),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb

@@ -17,17 +17,28 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos])
 
     private
 
-    def module_name
-      bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
+    def read_action
+      {
+        rs: 'RGGEN_READ_SET',
+        w0s: 'RGGEN_READ_DEFAULT',
+        w1s: 'RGGEN_READ_DEFAULT',
+        ws: 'RGGEN_READ_DEFAULT',
+        wos: 'RGGEN_READ_NONE'
+      }[bit_field.type]
     end
 
-    def set_value
-      value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
-      bin(value, 2)
+    def write_action
+      {
+        rs: 'RGGEN_WRITE_NONE',
+        w0s: 'RGGEN_WRITE_0_SET',
+        w1s: 'RGGEN_WRITE_1_SET',
+        ws: 'RGGEN_WRITE_SET',
+        wos: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
     end
 
-    def write_only
-      bit_field.write_only? && 1 || 0
+    def write_enable
+      bit_field.writable? && all_bits_1 || all_bits_0
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb

@@ -1,11 +1,19 @@
-rggen_bit_field_rw_wo #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>),
-  .WRITE_ONLY     (<%= write_only %>),
-  .WRITE_ONCE     (<%= write_once %>)
+  .SW_READ_ACTION (<%= read_action %>),
+  .SW_WRITE_ONCE  (<%= write_once %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb

@@ -13,8 +13,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1, :wo, :wo1]) do
 
     private
 
-    def write_only
-      bit_field.write_only? && 1 || 0
+    def read_action
+      bit_field.readable? && 'RGGEN_READ_DEFAULT' || 'RGGEN_READ_NONE'
     end
 
     def write_once

data/lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwc #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .HW_CLEAR_WIDTH (1)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_clear      (<%= clear_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         (<%= clear_signal %>),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rwe.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwe #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH                    (<%= width %>),
+  .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_HIGH)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_enable     (<%= enable_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= enable_signal %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rwl.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_rwl #(
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH                    (<%= width %>),
+  .INITIAL_VALUE            (<%= initial_value %>),
+  .SW_WRITE_ENABLE_POLARITY (RGGEN_ACTIVE_LOW)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_lock       (<%= lock_signal %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  (<%= lock_signal %>),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/rws.erb

@@ -1,11 +1,17 @@
-rggen_bit_field_rws #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .i_set        (<%= set_signal %>),
-  .i_value      (<%= value_in[loop_variables] %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  (<%= set_signal %>),
+  .i_hw_write_data    (<%= value_in[loop_variables] %>),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb

@@ -0,0 +1,19 @@
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_READ_ACTION   (<%= read_action %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
+) u_bit_field (
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb

@@ -0,0 +1,37 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(
+  :bit_field, :type, [:w0crs, :w0src, :w1crs, :w1src, :wcrs, :wsrc]
+) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      read_set? && 'RGGEN_READ_SET' || 'RGGEN_READ_CLEAR'
+    end
+
+    def read_set?
+      [:w0crs, :w1crs, :wcrs].include?(bit_field.type)
+    end
+
+    def write_action
+      {
+        w0crs: 'RGGEN_WRITE_0_CLEAR',
+        w0src: 'RGGEN_WRITE_0_SET',
+        w1crs: 'RGGEN_WRITE_1_CLEAR',
+        w1src: 'RGGEN_WRITE_1_SET',
+        wcrs: 'RGGEN_WRITE_CLEAR',
+        wsrc: 'RGGEN_WRITE_SET'
+      }[bit_field.type]
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -1,10 +1,18 @@
-rggen_bit_field_w01t #(
-  .TOGGLE_VALUE   (<%= toggle_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+rggen_bit_field #(
+  .WIDTH            (<%= width %>),
+  .INITIAL_VALUE    (<%= initial_value %>),
+  .SW_WRITE_ACTION  (<%= write_action %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -13,8 +13,11 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
 
     private
 
-    def toggle_value
-      bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
+    def write_action
+      {
+        w0t: 'RGGEN_WRITE_0_TOGGLE',
+        w1t: 'RGGEN_WRITE_1_TOGGLE'
+      }[bit_field.type]
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -1,9 +1,18 @@
-rggen_bit_field_<%= bit_field.type %> #(
+rggen_bit_field #(
   .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
+  .INITIAL_VALUE  (<%= initial_value %>),
+  .SW_READ_ACTION (<%= read_action %>)
 ) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
+  .i_clk              (<%= clock %>),
+  .i_rst_n            (<%= reset %>),
+  .bit_field_if       (<%= bit_field_if %>),
+  .i_sw_write_enable  ('1),
+  .i_hw_write_enable  ('0),
+  .i_hw_write_data    ('0),
+  .i_hw_set           ('0),
+  .i_hw_clear         ('0),
+  .i_value            ('0),
+  .i_mask             ('1),
+  .o_value            (<%= value_out[loop_variables] %>),
+  .o_value_unmasked   ()
 );

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -10,5 +10,14 @@ RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
     end
 
     main_code :bit_field, from_template: true
+
+    private
+
+    def read_action
+      {
+        wrc: 'RGGEN_READ_CLEAR',
+        wrs: 'RGGEN_READ_SET'
+      }[bit_field.type]
+    end
   end
 end

data/lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb

@@ -110,33 +110,7 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
 
     main_code :register_block, from_template: true
     main_code :register_block do |code|
-      unless configuration.fold_sv_interface_port?
-        [
-          [axi4lite_if.awvalid, awvalid],
-          [awready, axi4lite_if.awready],
-          [axi4lite_if.awid, awid],
-          [axi4lite_if.awaddr, awaddr],
-          [axi4lite_if.awprot, awprot],
-          [axi4lite_if.wvalid, wvalid],
-          [wready, axi4lite_if.wready],
-          [axi4lite_if.wdata, wdata],
-          [axi4lite_if.wstrb, wstrb],
-          [bvalid, axi4lite_if.bvalid],
-          [axi4lite_if.bready, bready],
-          [bid, axi4lite_if.bid],
-          [bresp, axi4lite_if.bresp],
-          [axi4lite_if.arvalid, arvalid],
-          [arready, axi4lite_if.arready],
-          [axi4lite_if.arid, arid],
-          [axi4lite_if.araddr, araddr],
-          [axi4lite_if.arprot, arprot],
-          [rvalid, axi4lite_if.rvalid],
-          [axi4lite_if.rready, rready],
-          [rid, axi4lite_if.rid],
-          [rdata, axi4lite_if.rdata],
-          [rresp, axi4lite_if.rresp]
-        ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
-      end
+      configuration.fold_sv_interface_port? || assign_axi4lite_signals(code)
     end
 
     private
@@ -144,5 +118,33 @@ RgGen.define_list_item_feature(:register_block, :protocol, :axi4lite) do
     def id_port_width
       "((#{id_width}>0)?#{id_width}:1)"
     end
+
+    def assign_axi4lite_signals(code)
+      [
+        [axi4lite_if.awvalid, awvalid],
+        [awready, axi4lite_if.awready],
+        [axi4lite_if.awid, awid],
+        [axi4lite_if.awaddr, awaddr],
+        [axi4lite_if.awprot, awprot],
+        [axi4lite_if.wvalid, wvalid],
+        [wready, axi4lite_if.wready],
+        [axi4lite_if.wdata, wdata],
+        [axi4lite_if.wstrb, wstrb],
+        [bvalid, axi4lite_if.bvalid],
+        [axi4lite_if.bready, bready],
+        [bid, axi4lite_if.bid],
+        [bresp, axi4lite_if.bresp],
+        [axi4lite_if.arvalid, arvalid],
+        [arready, axi4lite_if.arready],
+        [axi4lite_if.arid, arid],
+        [axi4lite_if.araddr, araddr],
+        [axi4lite_if.arprot, arprot],
+        [rvalid, axi4lite_if.rvalid],
+        [axi4lite_if.rready, rready],
+        [rid, axi4lite_if.rid],
+        [rdata, axi4lite_if.rdata],
+        [rresp, axi4lite_if.rresp]
+      ].each { |lhs, rhs| code << assign(lhs, rhs) << nl }
+    end
   end
 end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup RgGen::SystemVerilog::RTL do |builder|
+RgGen.register_plugin RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.23.1'
+    VERSION = '0.24.0'
   end
 end

metadata

@@ -1,29 +1,15 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.23.1
+  version: 0.24.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-10-24 00:00:00.000000000 Z
+date: 2021-01-20 00:00:00.000000000 Z
 dependencies:
-- !ruby/object:Gem::Dependency
-  name: docile
-  requirement: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.1.5
-  type: :runtime
-  prerelease: false
-  version_requirements: !ruby/object:Gem::Requirement
-    requirements:
-    - - ">="
-      - !ruby/object:Gem::Version
-        version: 1.1.5
 - !ruby/object:Gem::Dependency
   name: facets
   requirement: !ruby/object:Gem::Requirement
@@ -123,10 +109,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
@@ -181,8 +165,8 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: '0'
 requirements: []
-rubygems_version: 3.1.2
+rubygems_version: 3.2.3
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.23.1
+summary: rggen-systemverilog-0.24.0
 test_files: []

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_w01crs_wcrs #(
-  .CLEAR_VALUE    (<%= clear_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.rb

@@ -1,21 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
-  sv_rtl do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def clear_value
-      value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
-      bin(value, 2)
-    end
-  end
-end

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.erb

@@ -1,10 +0,0 @@
-rggen_bit_field_w01src_wsrc #(
-  .SET_VALUE      (<%= set_value %>),
-  .WIDTH          (<%= width %>),
-  .INITIAL_VALUE  (<%= initial_value %>)
-) u_bit_field (
-  .i_clk        (<%= clock %>),
-  .i_rst_n      (<%= reset %>),
-  .bit_field_if (<%= bit_field_if %>),
-  .o_value      (<%= value_out[loop_variables] %>)
-);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.rb

@@ -1,21 +0,0 @@
-# frozen_string_literal: true
-
-RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
-  sv_rtl do
-    build do
-      output :value_out, {
-        name: "o_#{full_name}", data_type: :logic, width: width,
-        array_size: array_size, array_format: array_port_format
-      }
-    end
-
-    main_code :bit_field, from_template: true
-
-    private
-
-    def set_value
-      value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
-      bin(value, 2)
-    end
-  end
-end