rggen-systemverilog 0.22.0 → 0.23.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 04ab89d77ae7cb44157307093ab87d047953a8fdb1c39035447b87c56de6179e
-  data.tar.gz: 84abe81c5b8ae34ec9bf28fbf1c35e8b1ad79cebb40a5835a1ceedac1aaaac33
+  metadata.gz: f00d208ebd7482486fc99dd9b7fcf787ca74b668c5a4fbbe60879cc6f497607d
+  data.tar.gz: af34bfc503ddaba18d7e696c14cef77f8979f53aaf05d7b6cd5a2f570dedfa33
 SHA512:
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-  data.tar.gz: a12ca1343735fdf819bdedf9d8a122015793177cd09d8c41764e54797c7972eadcbb4e7cc83a1429b21daddd476cf11b18d140b925338a96e763b33cf5a68117
+  metadata.gz: 65ab0f8c1a60dd50e7d0731491c396b9f4531ec4c1b9d1ed7d8ecebac4d8e57e4e8367763be85660d0ddb373f38371cf4ea373130514763c00e2cf6432928523
+  data.tar.gz: 4aafce8907c363d82c219d1aae0dbb5d43681d1fc05726e9e877a6b1ee894cbe1d63ddf5c295e152d8cdc1cd9cb2b5154fa470dbce81f75b65211dba8b635e86

data/lib/rggen/systemverilog/rtl.rb

@@ -13,20 +13,21 @@ module RgGen
       FEATURES = [
         'rtl/bit_field/sv_rtl_top',
         'rtl/bit_field/type',
-        'rtl/bit_field/type/rc_w0c_w1c',
+        'rtl/bit_field/type/rc_w0c_w1c_wc_woc',
         'rtl/bit_field/type/reserved',
         'rtl/bit_field/type/ro',
         'rtl/bit_field/type/rof',
-        'rtl/bit_field/type/rs_w0s_w1s',
+        'rtl/bit_field/type/rs_w0s_w1s_ws_wos',
         'rtl/bit_field/type/rw_w1_wo_wo1',
         'rtl/bit_field/type/rwc',
         'rtl/bit_field/type/rwe',
         'rtl/bit_field/type/rwl',
         'rtl/bit_field/type/rws',
-        'rtl/bit_field/type/w0crs_w1crs',
-        'rtl/bit_field/type/w0src_w1src',
+        'rtl/bit_field/type/w0crs_w1crs_wcrs',
+        'rtl/bit_field/type/w0src_w1src_wsrc',
         'rtl/bit_field/type/w0t_w1t',
         'rtl/bit_field/type/w0trg_w1trg',
+        'rtl/bit_field/type/wrc_wrs',
         'rtl/global/array_port_format',
         'rtl/global/fold_sv_interface_port',
         'rtl/register/sv_rtl_top',

data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.erb → rc_w0c_w1c_wc_woc.erb}

@@ -1,6 +1,7 @@
 <%= module_name %> #(
-<% if [:w0c, :w1c].include?(bit_field.type) %>
+<% if bit_field.type != :rc %>
   .CLEAR_VALUE    (<%= clear_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
 <% end %>
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{rc_w0c_w1c.rb → rc_w0c_w1c_wc_woc.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c, :wc, :woc]) do
   sv_rtl do
     build do
       input :set, {
@@ -24,15 +24,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rc, :w0c, :w1c]) do
     private
 
     def module_name
-      if bit_field.type == :rc
-        'rggen_bit_field_rc'
-      else
-        'rggen_bit_field_w01c'
-      end
+      bit_field.type == :rc && 'rggen_bit_field_rc' || 'rggen_bit_field_w01c_wc_woc'
     end
 
     def clear_value
-      bin({ w0c: 0, w1c: 1 }[bit_field.type], 1)
+      value = { w0c: 0b00, w1c: 0b01, wc: 0b10, woc: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
     end
 
     def value_out_unmasked

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.erb → rs_w0s_w1s_ws_wos.erb}

@@ -1,6 +1,7 @@
 <%= module_name %> #(
-<% if [:w0s, :w1s].include?(bit_field.type) %>
+<% if bit_field.type != :rs %>
   .SET_VALUE      (<%= set_value %>),
+  .WRITE_ONLY     (<%= write_only %>),
 <% end %>
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{rs_w0s_w1s.rb → rs_w0s_w1s_ws_wos.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s, :ws, :wos]) do
   sv_rtl do
     build do
       input :clear, {
@@ -18,15 +18,16 @@ RgGen.define_list_item_feature(:bit_field, :type, [:rs, :w0s, :w1s]) do
     private
 
     def module_name
-      if bit_field.type == :rs
-        'rggen_bit_field_rs'
-      else
-        'rggen_bit_field_w01s'
-      end
+      bit_field.type == :rs && 'rggen_bit_field_rs' || 'rggen_bit_field_w01s_ws_wos'
     end
 
     def set_value
-      bin({ w0s: 0, w1s: 1 }[bit_field.type], 1)
+      value = { w0s: 0b00, w1s: 0b01, ws: 0b10, wos: 0b10 }[bit_field.type]
+      bin(value, 2)
+    end
+
+    def write_only
+      bit_field.write_only? && 1 || 0
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.erb → w0crs_w1crs_wcrs.erb}

@@ -1,4 +1,4 @@
-rggen_bit_field_w01crs #(
+rggen_bit_field_w01crs_wcrs #(
   .CLEAR_VALUE    (<%= clear_value %>),
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0crs_w1crs.rb → w0crs_w1crs_wcrs.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs, :wcrs]) do
   sv_rtl do
     build do
       output :value_out, {
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0crs, :w1crs]) do
     private
 
     def clear_value
-      value = (bit_field.type == :w0crs && 0) || 1
-      bin(value, 1)
+      value = { w0crs: 0b00, w1crs: 0b01, wcrs: 0b10 }[bit_field.type]
+      bin(value, 2)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.erb → w0src_w1src_wsrc.erb}

@@ -1,4 +1,4 @@
-rggen_bit_field_w01src #(
+rggen_bit_field_w01src_wsrc #(
   .SET_VALUE      (<%= set_value %>),
   .WIDTH          (<%= width %>),
   .INITIAL_VALUE  (<%= initial_value %>)

data/lib/rggen/systemverilog/rtl/bit_field/type/{w0src_w1src.rb → w0src_w1src_wsrc.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
+RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src, :wsrc]) do
   sv_rtl do
     build do
       output :value_out, {
@@ -14,8 +14,8 @@ RgGen.define_list_item_feature(:bit_field, :type, [:w0src, :w1src]) do
     private
 
     def set_value
-      value = (bit_field.type == :w0src && 0) || 1
-      bin(value, 1)
+      value = { w0src: 0b00, w1src: 0b01, wsrc: 0b10 }[bit_field.type]
+      bin(value, 2)
     end
   end
 end

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb

@@ -0,0 +1,9 @@
+rggen_bit_field_<%= bit_field.type %> #(
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb

@@ -0,0 +1,14 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:wrc, :wrs]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+  end
+end

data/lib/rggen/systemverilog/rtl/register/type/indirect.rb

@@ -19,7 +19,7 @@ RgGen.define_list_item_feature(:register, :type, :indirect) do
     end
 
     def index_width
-      @index_width ||= index_fields.map(&:width).sum
+      @index_width ||= index_fields.sum(&:width)
     end
 
     def index_values

data/lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb

@@ -23,7 +23,7 @@ RgGen.define_simple_feature(:register_block, :sv_rtl_top) do
     end
 
     def total_registers
-      register_block.files_and_registers.map(&:count).sum
+      register_block.files_and_registers.sum(&:count)
     end
 
     private

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.22.0'
+    VERSION = '0.23.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.22.0
+  version: 0.23.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-08-17 00:00:00.000000000 Z
+date: 2020-08-25 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -103,16 +103,16 @@ files:
 - lib/rggen/systemverilog/rtl.rb
 - lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb
 - lib/rggen/systemverilog/rtl/bit_field/type.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/reserved.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/ro.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rof.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rwc.erb
@@ -123,14 +123,16 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/rwl.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/rws.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
-- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs_wcrs.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src_wsrc.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/wrc_wrs.rb
 - lib/rggen/systemverilog/rtl/feature.rb
 - lib/rggen/systemverilog/rtl/global/array_port_format.rb
 - lib/rggen/systemverilog/rtl/global/fold_sv_interface_port.rb
@@ -179,5 +181,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.22.0
+summary: rggen-systemverilog-0.23.0
 test_files: []