rggen-systemverilog 0.21.1 → 0.22.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: 63469ade8ab437c95069caec46c58fd2aba98a44f18e09722d63bbf51f11f62c
+  metadata.gz: 04ab89d77ae7cb44157307093ab87d047953a8fdb1c39035447b87c56de6179e
+  data.tar.gz: 84abe81c5b8ae34ec9bf28fbf1c35e8b1ad79cebb40a5835a1ceedac1aaaac33
 SHA512:
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+  metadata.gz: 97a47dd4eedce5d59607f41bfcea72c176cc1c6e2e7a04656ba387baa652ee3413a3b4c669c906c343907f97565cc7e10c194a66cc19dcc40830a00ec184b238
+  data.tar.gz: a12ca1343735fdf819bdedf9d8a122015793177cd09d8c41764e54797c7972eadcbb4e7cc83a1429b21daddd476cf11b18d140b925338a96e763b33cf5a68117

data/lib/rggen/systemverilog/ral.rb

@@ -7,6 +7,8 @@ require_relative 'ral/register_common'
 module RgGen
   module SystemVerilog
     module RAL
+      PLUGIN_NAME = :'rggen-sv-ral'
+
       FEATURES = [
         'ral/bit_field/type',
         'ral/bit_field/type/reserved_rof',

data/lib/rggen/systemverilog/ral/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/ral'
 
-RgGen.setup :'rggen-sv-ral', RgGen::SystemVerilog::RAL do |builder|
+RgGen.setup RgGen::SystemVerilog::RAL do |builder|
   builder.enable :register_block, [:sv_ral_model, :sv_ral_package]
   builder.enable :register_file, [:sv_ral_model]
 end

data/lib/rggen/systemverilog/rtl.rb

@@ -8,6 +8,8 @@ require_relative 'rtl/register_index'
 module RgGen
   module SystemVerilog
     module RTL
+      PLUGIN_NAME = :'rggen-sv-rtl'
+
       FEATURES = [
         'rtl/bit_field/sv_rtl_top',
         'rtl/bit_field/type',
@@ -23,6 +25,7 @@ module RgGen
         'rtl/bit_field/type/rws',
         'rtl/bit_field/type/w0crs_w1crs',
         'rtl/bit_field/type/w0src_w1src',
+        'rtl/bit_field/type/w0t_w1t',
         'rtl/bit_field/type/w0trg_w1trg',
         'rtl/global/array_port_format',
         'rtl/global/fold_sv_interface_port',

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb

@@ -0,0 +1,10 @@
+rggen_bit_field_w01t #(
+  .TOGGLE_VALUE   (<%= toggle_value %>),
+  .WIDTH          (<%= width %>),
+  .INITIAL_VALUE  (<%= initial_value %>)
+) u_bit_field (
+  .i_clk        (<%= clock %>),
+  .i_rst_n      (<%= reset %>),
+  .bit_field_if (<%= bit_field_if %>),
+  .o_value      (<%= value_out[loop_variables] %>)
+);

data/lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb

@@ -0,0 +1,20 @@
+# frozen_string_literal: true
+
+RgGen.define_list_item_feature(:bit_field, :type, [:w0t, :w1t]) do
+  sv_rtl do
+    build do
+      output :value_out, {
+        name: "o_#{full_name}", data_type: :logic, width: width,
+        array_size: array_size, array_format: array_port_format
+      }
+    end
+
+    main_code :bit_field, from_template: true
+
+    private
+
+    def toggle_value
+      bin({ w0t: 0, w1t: 1 }[bit_field.type], 1)
+    end
+  end
+end

data/lib/rggen/systemverilog/rtl/setup.rb

@@ -2,7 +2,7 @@
 
 require 'rggen/systemverilog/rtl'
 
-RgGen.setup :'rggen-sv-rtl', RgGen::SystemVerilog::RTL do |builder|
+RgGen.setup RgGen::SystemVerilog::RTL do |builder|
   builder.enable :global, [
     :array_port_format, :fold_sv_interface_port
   ]

data/lib/rggen/systemverilog/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module SystemVerilog
-    VERSION = '0.21.1'
+    VERSION = '0.22.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-systemverilog
 version: !ruby/object:Gem::Version
-  version: 0.21.1
+  version: 0.22.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-07-24 00:00:00.000000000 Z
+date: 2020-08-17 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: docile
@@ -127,6 +127,8 @@ files:
 - lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w1crs.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0src_w1src.rb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.erb
+- lib/rggen/systemverilog/rtl/bit_field/type/w0t_w1t.rb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.erb
 - lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb
 - lib/rggen/systemverilog/rtl/feature.rb
@@ -177,5 +179,5 @@ requirements: []
 rubygems_version: 3.1.2
 signing_key: 
 specification_version: 4
-summary: rggen-systemverilog-0.21.1
+summary: rggen-systemverilog-0.22.0
 test_files: []