rggen-systemverilog 0.11.0 → 0.11.1
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- checksums.yaml +4 -4
- data/README.md +2 -2
- data/lib/rggen/systemverilog/version.rb +1 -1
- metadata +3 -3
checksums.yaml
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---
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 72d85079f6fe1425ce8227634c0a0d4d2e3b2c24f72b9befc1ab6faddbb498d1
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data.tar.gz: '0483e8644334c77814b245d8644041041089f237f045e5c2eff0f011329fe20f'
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 749d5f74f72fe9d683bc29179d4c0ef2262025d71388e75da9eed675714d0819a092385e46be9c3180103c70bcb0e05fd815ff5b05ab35874cdcb2e57ab9930c
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data.tar.gz: dcbba23df7e2674578f010c0dc6db7ca0f84c9cf1d3c3b54ae4d036bc40660564084265fcae382e5cdca94890fba6ede3fd737828b724f9d89b513d422e08bea
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data/README.md
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# RgGen::SystemVerilog
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RgGen::SystemVerilog provides
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RgGen::SystemVerilog provides features listed below:
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* Structure for defining SystemVerilog RTL and UVM RAL model writers
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*
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* Convenience APIs for SystemVerilog code
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* Declaring signals, ports and variables
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* Generating code to define module, class and package
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* Etc.
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metadata
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--- !ruby/object:Gem::Specification
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name: rggen-systemverilog
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version: !ruby/object:Gem::Version
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version: 0.11.
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version: 0.11.1
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2019-08-
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date: 2019-08-19 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: docile
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@@ -109,5 +109,5 @@ requirements: []
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rubygems_version: 3.0.3
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signing_key:
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specification_version: 4
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-
summary: rggen-systemverilog-0.11.
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summary: rggen-systemverilog-0.11.1
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test_files: []
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