rggen-systemverilog 0.9.0 → 0.10.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
checksums.yaml
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SHA256:
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metadata.gz:
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data.tar.gz:
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metadata.gz: 7b9151400ac8b5e912e6542f249878a597c38f1ff740d47a318afc20872c5ce7
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data.tar.gz: '09b3d758f2b661f6677bdf45b88505b6bd3a3b6f5c6e1a96a14cffadcf8431a3'
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: aba68f32b100a9d1aecd998fe66ab7fc89a840700ec2b6b4c31f97e45a48b87f71c4828380b339f1cc8276655cf7d2e49c5a2e5e50101ebf8db7fc33a8249f5a
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data.tar.gz: 1005421893fd648c4e8bf9c10cf4865194e5327fd1b54b27dbe9ea6a2138f7a7777f6ef030d43dbadc788301fea4d7bbf8c331b4bf3b3c35c4e39cb3c72ba3ad
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data/README.md
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[](https://badge.fury.io/rb/rggen-systemverilog)
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[](https://travis-ci.org/rggen/rggen-systemverilog)
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[](https://codeclimate.com/github/rggen/rggen-systemverilog/maintainability)
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[](https://codecov.io/gh/rggen/rggen-systemverilog)
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[](https://sonarcloud.io/dashboard?id=rggen_rggen-systemverilog)
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[](https://gitter.im/rggen/rggen?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge)
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# RgGen::SystemVerilog
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@@ -32,7 +34,9 @@ $ gem isntall rggen-systemverilog
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Feedbacks, bug reports, questions and etc. are wellcome! You can post them by using following ways:
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* [GitHub Issue Tracker](https://github.com/rggen/rggen-systemverilog/issues)
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* [
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* [Chat Room](https://gitter.im/rggen/rggen)
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* [Mailing List](https://groups.google.com/d/forum/rggen)
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* [Mail](mailto:rggen@googlegroups.com)
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## Copyright & License
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@@ -67,7 +67,7 @@ module RgGen
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end
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def packed_dimensions
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(
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(serialized? ? serialized_array_size : packed_array_size)
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.map { |size| "[#{msb(size)}:0]" }
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.join
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end
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!array_size.empty?
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end
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def
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array? && array_format == :
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def serialized?
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array? && array_format == :serialized
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end
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def
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def serialized_array_size
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size = [(width || 1), *array_size]
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if size.all? { |s| s.is_a?(Integer) }
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[size.inject(&:*)]
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end
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def __array_select__(array_index)
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if @array_format == :
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"[#{
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if @array_format == :serialized
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"[#{__serialized_lsb__(array_index)}+:#{@width}]"
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else
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array_index
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.map { |index| "[#{index}]" }
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end
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end
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def
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__reduce_array__([@width,
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def __serialized_lsb__(array_index)
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__reduce_array__([@width, __serialized_index__(array_index)], :*, 1)
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end
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def
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def __serialized_index__(array_index)
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index_values =
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array_index
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.reverse
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metadata
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--- !ruby/object:Gem::Specification
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name: rggen-systemverilog
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version: !ruby/object:Gem::Version
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version: 0.
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version: 0.10.0
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platform: ruby
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authors:
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- Taichi Ishitani
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autorequire:
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bindir: bin
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cert_chain: []
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date: 2019-07-
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date: 2019-07-31 00:00:00.000000000 Z
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dependencies:
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- !ruby/object:Gem::Dependency
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name: docile
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@@ -56,7 +56,7 @@ description: 'Structure of SystemVerilog RTL and UVM RAL model writers for Rggen
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'
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email:
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- rggen@googlegroups.com
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executables: []
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extensions: []
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extra_rdoc_files: []
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- MIT
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metadata:
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bug_tracker_uri: https://github.com/rggen/rggen-systemverilog/issues
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mailing_list_uri: https://groups.google.com/d/forum/rggen
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source_code_uri: https://github.com/rggen/rggen-systemverilog
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wiki_uri: https://github.com/rggen/rggen/wiki
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post_install_message:
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rubygems_version: 3.0.3
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signing_key:
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specification_version: 4
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summary: rggen-systemverilog-0.
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summary: rggen-systemverilog-0.10.0
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test_files: []
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