rggen-systemrdl 0.1.0
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +7 -0
- data/LICENSE +21 -0
- data/README.md +66 -0
- data/lib/rggen/systemrdl/converter/addrmap.rb +49 -0
- data/lib/rggen/systemrdl/converter/base.rb +165 -0
- data/lib/rggen/systemrdl/converter/field.rb +514 -0
- data/lib/rggen/systemrdl/converter/mem.rb +23 -0
- data/lib/rggen/systemrdl/converter/reg.rb +29 -0
- data/lib/rggen/systemrdl/converter/regfile.rb +29 -0
- data/lib/rggen/systemrdl/global/ignore_precedence.rb +27 -0
- data/lib/rggen/systemrdl/loader.rb +21 -0
- data/lib/rggen/systemrdl/version.rb +7 -0
- data/lib/rggen/systemrdl.rb +20 -0
- data/notes/bit_field_type_mapping.md +105 -0
- data/notes/bit_field_type_matrix.md +80 -0
- data/notes/external_reg_regfile_mapping.md +37 -0
- data/notes/interrupt_aggregation_policy.md +50 -0
- data/notes/precedence_handling_policy.md +38 -0
- data/notes/systemrdl_rggen_gap_analysis.md +132 -0
- data/notes/systemrdl_to_rggen_mapping.md +264 -0
- data/notes/systemrdl_to_rggen_todo.md +34 -0
- data/notes/udp_handling_policy.md +181 -0
- metadata +80 -0
checksums.yaml
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---
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SHA256:
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metadata.gz: 2688c26e49be1e67f4901940a3872d9113ae6e6c33fc2920152a7907058e689d
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data.tar.gz: eff39992ccaa258d5ca4ec00896c986e003ca9478d563aaf4a1f496586f77dad
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SHA512:
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metadata.gz: 502271d1de11850f8355a59a023307531ccb52ef8f0ccf2be917f544fddb865e870929aaebcba2b21b88ad5c3313b2ee5abbb5dbf0cf3b31ed0199d3c5f10110
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data.tar.gz: ba07135e0c0473ec599241d9e1b663bab94850e8c2dab22c9fec3a81c13e5eb9c99caec2e756321d294b3fb47b4386a736a2bdadbf0ba0acca6dea750e33e0c0
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data/LICENSE
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MIT License
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Copyright (c) 2026 Taichi Ishitani
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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data/README.md
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[](https://badge.fury.io/rb/rggen-systemrdl)
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[](https://github.com/rggen/rggen-systemrdl/actions/workflows/ci.yml)
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[](https://discord.com/invite/KWya83ZZxr)
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# RgGen::SystemRDL
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RgGen::SystemRDL is a RgGen plugin to load register map descriptions written in [SystemRDL 2.0](https://www.accellera.org/images/downloads/standards/systemrdl/SystemRDL_2.0_Jan2018.pdf).
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## Installation
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To install RgGen::SystemRDL, use the following command:
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```
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$ gem install rggen-systemrdl
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```
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## Usage
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You need to tell RgGen to load the RgGen::SystemRDL plugin. There are two ways.
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### Using the `--plugin` runtime option
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```
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$ rggen --plugin rggen-systemrdl your_register_map.rdl
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```
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### Using the `RGGEN_PLUGINS` environment variable
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```
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$ export RGGEN_PLUGINS=${RGGEN_PLUGINS}:rggen-systemrdl
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$ rggen your_register_map.rdl
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```
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## Supported features and limitations
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The plugin converts SystemRDL `addrmap`, `regfile`, `reg`, `field`, and `mem` components into the corresponding RgGen register map layers, including a wide range of `field` access types.
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Some SystemRDL constructs have no corresponding concept in RgGen. These are not supported and cause an error.
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For the detailed component-to-layer correspondence, the full SystemRDL-property to RgGen-type mapping, and the complete list of unsupported constructs with the reasons behind each decision, see the design notes:
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* [SystemRDL to RgGen mapping](notes/systemrdl_to_rggen_mapping.md)
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* [Bit field type matrix](notes/bit_field_type_matrix.md)
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### Precedence handling
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RgGen fixes precedence to hardware, whereas SystemRDL's precedence is variable and defaults to software.
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A field is therefore rejected unless its precedence is explicitly set to `hw`.
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To accept a SystemRDL description without changing it, set the `ignore_precedence` configuration option (default `false`) to `true`.
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Then the `precedence` property in the SystemRDL description is ignored and every field is treated as hardware precedence.
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## Contact
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Feedbacks, bug reports, questions and etc. are welcome! You can post them by using the following
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ways:
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* [GitHub Issue Tracker](https://github.com/rggen/rggen/issues)
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* [GitHub Discussions](https://github.com/rggen/rggen/discussions)
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* [Discord](https://discord.com/invite/KWya83ZZxr)
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* [Mailing List](https://groups.google.com/d/forum/rggen)
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* [Mail](mailto:rggen@googlegroups.com)
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## Copyright & License
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Copyright © 2026 Taichi Ishitani.
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RgGen::SystemRDL is licensed under the [MIT License](https://opensource.org/licenses/MIT), see [LICENSE](LICENSE) for further details.
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# frozen_string_literal: true
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module RgGen
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module SystemRDL
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module Converter
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class AddrMap < Base
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private
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def support_external?
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true
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end
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def external?(rdl_model)
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!rdl_model.parent.nil?
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end
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def insert_to_root?
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true
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end
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def layer_name
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:register_block
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end
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def unsupported_properties
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[:sharedextbus, :bigendian, :littleendian, :rsvdset, :rsvdsetX, :msb0]
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end
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def convert_rdl_model(rdl_model, _root_data, input_data)
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convert_addrmap_name(rdl_model, input_data)
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convert_comment(rdl_model, input_data)
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convert_byte_size(rdl_model, input_data)
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end
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def convert_addrmap_name(rdl_model, input_data)
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check_name(rdl_model)
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name = rdl_model.full_name
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escaped_name = escape_name(name.gsub('.', '__'))
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input_data[:name] = to_input_value(escaped_name, rdl_model.token_range)
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end
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def convert_byte_size(rdl_model, input_data)
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input_data[:byte_size] = from_property(rdl_model, :size)
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end
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end
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end
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end
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end
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# frozen_string_literal: true
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module RgGen
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module SystemRDL
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module Converter
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class Base
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def self.convert(rdl_model, root_data, input_data)
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(@converter ||= new).convert(rdl_model, root_data, input_data)
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end
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def convert(rdl_model, root_data, input_data)
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check_external(rdl_model)
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check_unsupported_properties(rdl_model)
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check_property_reference(rdl_model)
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insert_external(rdl_model, input_data) if external?(rdl_model)
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return if region_only?
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input_data = insert_design_boundary(rdl_model, root_data) if design_boundary_required?(rdl_model)
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input_data = (insert_to_root? && root_data || input_data).child(layer_name)
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convert_rdl_model(rdl_model, root_data, input_data)
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rdl_model.instances.each do |sub_model|
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converter = select_converter(sub_model)
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converter.convert(sub_model, root_data, input_data)
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end
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end
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private
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def check_external(rdl_model)
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return unless !support_external? && external?(rdl_model)
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error "external #{rdl_model.layer} is not supported", rdl_model.token_range
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end
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def support_external?
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false
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end
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def external?(_rdl_model)
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false
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end
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def insert_external(rdl_model, input_data)
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input_data = input_data.child(:register)
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convert_name(rdl_model, input_data)
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convert_comment(rdl_model, input_data)
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convert_offset_address(rdl_model, input_data)
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convert_external_type(rdl_model, input_data)
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end
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def convert_external_type(rdl_model, input_data)
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size = rdl_model.size
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bus_width = input_data.configuration.bus_width
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if (size % (bus_width / 8)) != 0
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message =
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"#{rdl_model.layer} size is not a multiple of the bus width: " \
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"size #{size} bus width #{bus_width}"
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error message, rdl_model.token_range
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end
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input_data[:type] = to_input_value(:external, nil)
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input_data[:size] = to_input_value(size / (bus_width / 8), nil)
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end
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def check_unsupported_properties(rdl_model)
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unsupported_properties&.each do |property|
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prop = rdl_model.property(property)
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next unless prop.value
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error "#{property} is not supported", prop.token_range
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end
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end
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def unsupported_properties
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end
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def check_property_reference(rdl_model)
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rdl_model.properties.each_value do |prop|
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next unless prop.property_ref?
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error 'property reference is not supported', prop.token_range
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end
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end
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def region_only?
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false
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end
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def design_boundary_required?(_rdl_model)
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false
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end
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def insert_to_root?
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false
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end
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def select_converter(rdl_model)
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{
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addrmap: AddrMap,
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regfile: RegFile,
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reg: Reg,
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field: Field,
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mem: Mem
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}[rdl_model.layer]
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end
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def error(message, token_range)
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pos = token_range&.head&.position
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raise Core::SourceError.new(message, pos)
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end
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def convert_name(rdl_model, input_data)
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check_name(rdl_model)
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input_data[:name] = to_input_value(escape_name(rdl_model.name), rdl_model.token_range)
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end
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def check_name(rdl_model)
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return unless rdl_model.name.include?('__')
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error "identifier including __ is not allowed: #{rdl_model.name}", rdl_model.token_range
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end
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def escape_name(name)
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name.gsub('[', '__').gsub(']', '')
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end
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def convert_comment(rdl_model, input_data)
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input_data[:comment] = from_property(rdl_model, :desc)
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end
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def convert_offset_address(rdl_model, input_data)
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input_data[:offset_address] = from_property(rdl_model, :address)
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end
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def set_true?(rdl_model, property_name)
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rdl_model.property(property_name).value == true
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end
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def from_property(rdl_model, property_name)
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property = rdl_model.property(property_name)
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return if property.value.nil?
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from_property_value(property)
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end
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def from_property_value(property)
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if property.value?
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to_input_value(property.value, property.token_range)
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else
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|
+
to_input_value(property.value.full_name(exclude_addrmap: true), property.token_range)
|
|
155
|
+
end
|
|
156
|
+
end
|
|
157
|
+
|
|
158
|
+
def to_input_value(value, token_range)
|
|
159
|
+
position = token_range&.head&.position
|
|
160
|
+
Core::InputBase::InputValue.new(value, position)
|
|
161
|
+
end
|
|
162
|
+
end
|
|
163
|
+
end
|
|
164
|
+
end
|
|
165
|
+
end
|