rggen-default-register-map 0.17.0 → 0.18.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: 4ed4f7d03fe2c3b316ce912c5080070214841e66c0b6c6e84d77beb2873c845d
-  data.tar.gz: 52521afda2eaea55d94fa19310b6c02db2fcb0d5f3ca5af7d7a22f62d5144aa8
+  metadata.gz: 5606aceae9565f8ffa80125e9eaa9e5d4eee19296a0438e353d54a6a584600a6
+  data.tar.gz: 2f809d1e88bbd7acc788e2308e9b9cf56a5bd571dba191ca1d08e660f05958b8
 SHA512:
-  metadata.gz: 29148e29d7cdc8ac258f538a2c4c090746a6350d43d4cec5aa201af6b2dd59de421a916c55d727aad48fc7a52051fd7b8670d6cdd4e7908ae859c403ffb28d7a
-  data.tar.gz: dd74e27ee704d145f6009e544308c6884361d27a63c4f6e75e428f25a9656b0e62a8098a8982a2efac548a226564787907b20d72865ac97e4b7f549c05d6cb08
+  metadata.gz: 784ee0f9741d412d636361bd0a007ab130a383063d8eddd5873cf687b675112a19718805f9d5d3e83814e0338dff7d1901429279aa79af10d26db74aa4de9e98
+  data.tar.gz: a44e28a91dbfcc9f9de6334d11589d6452981b4674ad2385d7cb1e3c25311b38894de607b691be9ea49c6f1528d7433c5271a40857a6070e154bfa1b6bb5d4f9

data/lib/rggen/default_register_map.rb

@@ -16,14 +16,14 @@ module RgGen
       'default_register_map/bit_field/type/ro',
       'default_register_map/bit_field/type/rof',
       'default_register_map/bit_field/type/rs',
-      'default_register_map/bit_field/type/rw',
+      'default_register_map/bit_field/type/rw_w1',
       'default_register_map/bit_field/type/rwc_rws',
       'default_register_map/bit_field/type/rwe_rwl',
       'default_register_map/bit_field/type/w0c_w1c',
       'default_register_map/bit_field/type/w0crs_w1crs_w0src_w1src',
       'default_register_map/bit_field/type/w0s_w1s',
       'default_register_map/bit_field/type/w0trg_w1trg',
-      'default_register_map/bit_field/type/wo',
+      'default_register_map/bit_field/type/wo_wo1',
       'default_register_map/global/address_width',
       'default_register_map/global/bus_width',
       'default_register_map/register/name',

data/lib/rggen/default_register_map/bit_field/bit_assignment.rb

@@ -19,13 +19,13 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
     end
 
     verify(:feature) do
-      error_condition { [@lsb, @width, @sequence_size, @step].none? }
+      error_condition { [@lsb_base, @width, @sequence_size, @step].none? }
       message { 'no bit assignment is given' }
     end
 
     verify(:feature) do
-      error_condition { !@lsb }
-      message { 'no lsb is given' }
+      error_condition { [@lsb_base, @width].none? }
+      message { 'neither lsb nor width is given' }
     end
 
     verify(:feature) do
@@ -61,7 +61,11 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
 
     private
 
-    KEYS = [:lsb, :width, :sequence_size, :step].freeze
+    VARIABLE_NAMES = {
+      lsb: :@lsb_base, width: :@width, sequence_size: :@sequence_size, step: :@step
+    }.freeze
+
+    KEYS = VARIABLE_NAMES.keys.freeze
 
     def preprocess(value)
       if value.is_a?(Hash)
@@ -83,18 +87,38 @@ RgGen.define_simple_feature(:bit_field, :bit_assignment) do
 
     def parse_value(input_value, key)
       input_value.key?(key) &&
-        instance_variable_set("@#{key}", Integer(input_value[key]))
+        instance_variable_set(VARIABLE_NAMES[key], Integer(input_value[key]))
     rescue ArgumentError, TypeError
       error "cannot convert #{input_value[key].inspect} into " \
             "bit assignment(#{key.to_s.tr('_', ' ')})"
     end
 
+    def lsb_base
+      @lsb_base ||=
+        ((bit_field.component_index.zero? && 0) || calc_next_lsb(previous_bit_field))
+    end
+
+    def previous_bit_field
+      index = bit_field.component_index - 1
+      register.bit_fields[index]
+    end
+
+    def calc_next_lsb(bit_field)
+      compact_sequential_bit_field?(bit_field) &&
+        (bit_field.lsb + bit_field.width * bit_field.sequence_size) ||
+        (bit_field.lsb + bit_field.width)
+    end
+
+    def compact_sequential_bit_field?(bit_field)
+      bit_field.sequential? && (bit_field.step == bit_field.width)
+    end
+
     def lsb_bit(index = 0)
-      lsb_msb_bit(index, @lsb)
+      lsb_msb_bit(index, lsb_base)
     end
 
     def msb_bit(index = 0)
-      lsb_msb_bit(index, @lsb + width - 1)
+      lsb_msb_bit(index, lsb_base + width - 1)
     end
 
     def lsb_msb_bit(index, base)

data/lib/rggen/default_register_map/bit_field/type/{rw.rb → rw_w1.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :rw) do
+RgGen.define_list_item_feature(:bit_field, :type, [:rw, :w1]) do
   register_map do
     read_write
     non_volatile

data/lib/rggen/default_register_map/bit_field/type/{wo.rb → wo_wo1.rb}

@@ -1,6 +1,6 @@
 # frozen_string_literal: true
 
-RgGen.define_list_item_feature(:bit_field, :type, :wo) do
+RgGen.define_list_item_feature(:bit_field, :type, [:wo, :wo1]) do
   register_map do
     write_only
     non_volatile

data/lib/rggen/default_register_map/register/offset_address.rb

@@ -2,7 +2,7 @@
 
 RgGen.define_simple_feature(:register, :offset_address) do
   register_map do
-    property :offset_address
+    property :offset_address, initial: -> { default_offset_address }
     property :address_range, initial: -> { start_address..end_address }
     property :overlap?, forward_to: :overlap_address_range?
 
@@ -15,11 +15,6 @@ RgGen.define_simple_feature(:register, :offset_address) do
         end
     end
 
-    verify(:feature) do
-      error_condition { !offset_address }
-      message { 'no offset address is given' }
-    end
-
     verify(:feature) do
       error_condition { offset_address.negative? }
       message { "offset address is less than 0: #{offset_address}" }
@@ -62,6 +57,16 @@ RgGen.define_simple_feature(:register, :offset_address) do
 
     private
 
+    def default_offset_address
+      register.component_index.zero? && 0 ||
+        (previous_register.offset_address + previous_register.byte_size)
+    end
+
+    def previous_register
+      index = register.component_index - 1
+      register_block.registers[index]
+    end
+
     def bus_width
       configuration.bus_width
     end

data/lib/rggen/default_register_map/setup.rb

@@ -14,6 +14,6 @@ RgGen.setup :'rggen-defualt-register-map', RgGen::DefaultRegisterMap do |builder
     :rc, :reserved, :ro, :rof, :rs,
     :rw, :rwc, :rwe, :rwl, :rws,
     :w0c, :w0crs, :w0s, :w0src, :w0trg,
-    :w1c, :w1crs, :w1s, :w1src, :w1trg, :wo
+    :w1, :w1c, :w1crs, :w1s, :w1src, :w1trg, :wo, :wo1
   ]
 end

data/lib/rggen/default_register_map/version.rb

@@ -2,6 +2,6 @@
 
 module RgGen
   module DefaultRegisterMap
-    VERSION = '0.17.0'
+    VERSION = '0.18.0'
   end
 end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: rggen-default-register-map
 version: !ruby/object:Gem::Version
-  version: 0.17.0
+  version: 0.18.0
 platform: ruby
 authors:
 - Taichi Ishitani
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-11-13 00:00:00.000000000 Z
+date: 2019-11-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: bundler
@@ -46,14 +46,14 @@ files:
 - lib/rggen/default_register_map/bit_field/type/ro.rb
 - lib/rggen/default_register_map/bit_field/type/rof.rb
 - lib/rggen/default_register_map/bit_field/type/rs.rb
-- lib/rggen/default_register_map/bit_field/type/rw.rb
+- lib/rggen/default_register_map/bit_field/type/rw_w1.rb
 - lib/rggen/default_register_map/bit_field/type/rwc_rws.rb
 - lib/rggen/default_register_map/bit_field/type/rwe_rwl.rb
 - lib/rggen/default_register_map/bit_field/type/w0c_w1c.rb
 - lib/rggen/default_register_map/bit_field/type/w0crs_w1crs_w0src_w1src.rb
 - lib/rggen/default_register_map/bit_field/type/w0s_w1s.rb
 - lib/rggen/default_register_map/bit_field/type/w0trg_w1trg.rb
-- lib/rggen/default_register_map/bit_field/type/wo.rb
+- lib/rggen/default_register_map/bit_field/type/wo_wo1.rb
 - lib/rggen/default_register_map/global/address_width.rb
 - lib/rggen/default_register_map/global/bus_width.rb
 - lib/rggen/default_register_map/register/name.rb
@@ -92,5 +92,5 @@ requirements: []
 rubygems_version: 3.0.3
 signing_key: 
 specification_version: 4
-summary: rggen-default-register-map-0.17.0
+summary: rggen-default-register-map-0.18.0
 test_files: []