origen_verilog 0.5.0 → 0.5.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
-SHA1:
-  metadata.gz: 04b3e2c736fb06dd06fe0bbe6a4a4a163f2575a1
-  data.tar.gz: 0c8bedd2f0affdcbfda380df15c908526bdea19e
+SHA256:
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+  data.tar.gz: dfecefa841ca3bcc4da160b105e7af3c4556ffd7f6312f07c84c5d98565353e3
 SHA512:
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+  data.tar.gz: 5d6c02e83a3b8e4035b87e46ab0330416a31619bec2fc3c32d72344d219754fe2dc7f417e99297c66dde34fbaf85e618523e47726b8380dd14928b041b5eaeb9

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenVerilog
   MAJOR = 0
   MINOR = 5
-  BUGFIX = 0
+  BUGFIX = 1
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/grammars/verilog.rb

@@ -48593,12 +48593,6 @@ module OrigenVerilog
         r0
       end
 
-      module PortIdentifier0
-        def identifier
-          elements[3]
-        end
-      end
-
       def _nt_port_identifier
         start_index = index
         if node_cache[:port_identifier].has_key?(index)
@@ -48610,52 +48604,7 @@ module OrigenVerilog
           return cached
         end
 
-        i0, s0 = index, []
-        i1 = index
-        r2 = _nt_inout_declaration
-        if r2
-          @index = i1
-          r1 = nil
-        else
-          @index = i1
-          r1 = instantiate_node(SyntaxNode,input, index...index)
-        end
-        s0 << r1
-        if r1
-          i3 = index
-          r4 = _nt_input_declaration
-          if r4
-            @index = i3
-            r3 = nil
-          else
-            @index = i3
-            r3 = instantiate_node(SyntaxNode,input, index...index)
-          end
-          s0 << r3
-          if r3
-            i5 = index
-            r6 = _nt_output_declaration
-            if r6
-              @index = i5
-              r5 = nil
-            else
-              @index = i5
-              r5 = instantiate_node(SyntaxNode,input, index...index)
-            end
-            s0 << r5
-            if r5
-              r7 = _nt_identifier
-              s0 << r7
-            end
-          end
-        end
-        if s0.last
-          r0 = instantiate_node(SyntaxNode,input, i0...index, s0)
-          r0.extend(PortIdentifier0)
-        else
-          @index = i0
-          r0 = nil
-        end
+        r0 = _nt_identifier
 
         node_cache[:port_identifier][start_index] = r0
 
@@ -48684,6 +48633,9 @@ module OrigenVerilog
       end
 
       module SimpleIdentifier1
+      end
+
+      module SimpleIdentifier2
         def to_ast
           text_value
         end
@@ -48701,37 +48653,118 @@ module OrigenVerilog
         end
 
         i0, s0 = index, []
-        if has_terminal?(@regexps[gr = '\A[a-zA-Z_]'] ||= Regexp.new(gr), :regexp, index)
-          r1 = true
-          @index += 1
+        i1 = index
+        i2, s2 = index, []
+        i3 = index
+        if (match_len = has_terminal?("input", false, index))
+          r4 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+          @index += match_len
         else
-          terminal_parse_failure('[a-zA-Z_]')
-          r1 = nil
+          terminal_parse_failure('"input"')
+          r4 = nil
         end
-        s0 << r1
-        if r1
-          s2, i2 = [], index
-          loop do
-            if has_terminal?(@regexps[gr = '\A[a-zA-Z0-9_]'] ||= Regexp.new(gr), :regexp, index)
-              r3 = true
-              @index += 1
+        if r4
+          r4 = SyntaxNode.new(input, (index-1)...index) if r4 == true
+          r3 = r4
+        else
+          if (match_len = has_terminal?("output", false, index))
+            r5 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+            @index += match_len
+          else
+            terminal_parse_failure('"output"')
+            r5 = nil
+          end
+          if r5
+            r5 = SyntaxNode.new(input, (index-1)...index) if r5 == true
+            r3 = r5
+          else
+            if (match_len = has_terminal?("inout", false, index))
+              r6 = instantiate_node(SyntaxNode,input, index...(index + match_len))
+              @index += match_len
             else
-              terminal_parse_failure('[a-zA-Z0-9_]')
-              r3 = nil
+              terminal_parse_failure('"inout"')
+              r6 = nil
             end
-            if r3
-              s2 << r3
+            if r6
+              r6 = SyntaxNode.new(input, (index-1)...index) if r6 == true
+              r3 = r6
             else
-              break
+              @index = i3
+              r3 = nil
             end
           end
+        end
+        s2 << r3
+        if r3
+          i7 = index
+          if has_terminal?(@regexps[gr = '\A[a-zA-Z0-9_]'] ||= Regexp.new(gr), :regexp, index)
+            r8 = true
+            @index += 1
+          else
+            terminal_parse_failure('[a-zA-Z0-9_]')
+            r8 = nil
+          end
+          if r8
+            @index = i7
+            r7 = nil
+            terminal_parse_failure('[a-zA-Z0-9_]', true)
+          else
+            @terminal_failures.pop
+            @index = i7
+            r7 = instantiate_node(SyntaxNode,input, index...index)
+          end
+          s2 << r7
+        end
+        if s2.last
           r2 = instantiate_node(SyntaxNode,input, i2...index, s2)
-          s0 << r2
+          r2.extend(SimpleIdentifier0)
+        else
+          @index = i2
+          r2 = nil
+        end
+        if r2
+          @index = i1
+          r1 = nil
+          terminal_parse_failure("<a sequence>", true)
+        else
+          @terminal_failures.pop
+          @index = i1
+          r1 = instantiate_node(SyntaxNode,input, index...index)
+        end
+        s0 << r1
+        if r1
+          if has_terminal?(@regexps[gr = '\A[a-zA-Z_]'] ||= Regexp.new(gr), :regexp, index)
+            r9 = true
+            @index += 1
+          else
+            terminal_parse_failure('[a-zA-Z_]')
+            r9 = nil
+          end
+          s0 << r9
+          if r9
+            s10, i10 = [], index
+            loop do
+              if has_terminal?(@regexps[gr = '\A[a-zA-Z0-9_]'] ||= Regexp.new(gr), :regexp, index)
+                r11 = true
+                @index += 1
+              else
+                terminal_parse_failure('[a-zA-Z0-9_]')
+                r11 = nil
+              end
+              if r11
+                s10 << r11
+              else
+                break
+              end
+            end
+            r10 = instantiate_node(SyntaxNode,input, i10...index, s10)
+            s0 << r10
+          end
         end
         if s0.last
           r0 = instantiate_node(SyntaxNode,input, i0...index, s0)
-          r0.extend(SimpleIdentifier0)
           r0.extend(SimpleIdentifier1)
+          r0.extend(SimpleIdentifier2)
         else
           @index = i0
           r0 = nil

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_verilog
 version: !ruby/object:Gem::Version
-  version: 0.5.0
+  version: 0.5.1
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-06-21 00:00:00.000000000 Z
+date: 2018-11-27 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: ast
@@ -93,7 +93,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.6.14.1
+rubygems_version: 2.7.6
 signing_key: 
 specification_version: 4
 summary: A parser and generator for Verilog (IEEE 1364)