origen_verilog 0.2.2 → 0.3.0

checksums.yaml

@@ -1,7 +1,7 @@
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+  data.tar.gz: d7c47379ab7e2eba83b5637166f956f970feeffaac0fe1f299d35f478316dda88e4a477ce8c46b59895fc5d342d65668330812208cc8db17e24771110da7cf82

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenVerilog
   MAJOR = 0
-  MINOR = 2
-  BUGFIX = 2
+  MINOR = 3
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/grammars/verilog.rb

@@ -2335,6 +2335,72 @@ module OrigenVerilog
         r0
       end
 
+      module ModuleItem0
+        def port_declaration
+          elements[0]
+        end
+
+        def s
+          elements[1]
+        end
+
+      end
+
+      def _nt_module_item
+        start_index = index
+        if node_cache[:module_item].has_key?(index)
+          cached = node_cache[:module_item][index]
+          if cached
+            node_cache[:module_item][index] = cached = SyntaxNode.new(input, index...(index + 1)) if cached == true
+            @index = cached.interval.end
+          end
+          return cached
+        end
+
+        i0 = index
+        i1, s1 = index, []
+        r2 = _nt_port_declaration
+        s1 << r2
+        if r2
+          r3 = _nt_s
+          s1 << r3
+          if r3
+            if (match_len = has_terminal?(";", false, index))
+              r4 = true
+              @index += match_len
+            else
+              terminal_parse_failure('";"')
+              r4 = nil
+            end
+            s1 << r4
+          end
+        end
+        if s1.last
+          r1 = instantiate_node(SyntaxNode,input, i1...index, s1)
+          r1.extend(ModuleItem0)
+        else
+          @index = i1
+          r1 = nil
+        end
+        if r1
+          r1 = SyntaxNode.new(input, (index-1)...index) if r1 == true
+          r0 = r1
+        else
+          r5 = _nt_non_port_module_item
+          if r5
+            r5 = SyntaxNode.new(input, (index-1)...index) if r5 == true
+            r0 = r5
+          else
+            @index = i0
+            r0 = nil
+          end
+        end
+
+        node_cache[:module_item][start_index] = r0
+
+        r0
+      end
+
       module ModuleOrGenerateItem0
         def s1
           elements[0]
@@ -7738,38 +7804,38 @@ module OrigenVerilog
       end
 
       module VariableType0
-        def s
+        def variable_identifier
           elements[0]
         end
 
-        def dimension
+        def s1
           elements[1]
         end
-      end
 
-      module VariableType1
-        def variable_identifier
-          elements[0]
+        def s2
+          elements[3]
         end
 
+        def constant_expression
+          elements[4]
+        end
       end
 
-      module VariableType2
-        def variable_identifier
+      module VariableType1
+        def s
           elements[0]
         end
 
-        def s1
+        def dimension
           elements[1]
         end
+      end
 
-        def s2
-          elements[3]
+      module VariableType2
+        def variable_identifier
+          elements[0]
         end
 
-        def constant_expression
-          elements[4]
-        end
       end
 
       module VariableType3
@@ -7794,34 +7860,30 @@ module OrigenVerilog
         r2 = _nt_variable_identifier
         s1 << r2
         if r2
-          s3, i3 = [], index
-          loop do
-            i4, s4 = index, []
-            r5 = _nt_s
-            s4 << r5
-            if r5
-              r6 = _nt_dimension
-              s4 << r6
-            end
-            if s4.last
-              r4 = instantiate_node(SyntaxNode,input, i4...index, s4)
-              r4.extend(VariableType0)
+          r3 = _nt_s
+          s1 << r3
+          if r3
+            if (match_len = has_terminal?("=", false, index))
+              r4 = true
+              @index += match_len
             else
-              @index = i4
+              terminal_parse_failure('"="')
               r4 = nil
             end
+            s1 << r4
             if r4
-              s3 << r4
-            else
-              break
+              r5 = _nt_s
+              s1 << r5
+              if r5
+                r6 = _nt_constant_expression
+                s1 << r6
+              end
             end
           end
-          r3 = instantiate_node(SyntaxNode,input, i3...index, s3)
-          s1 << r3
         end
         if s1.last
           r1 = instantiate_node(SyntaxNode,input, i1...index, s1)
-          r1.extend(VariableType1)
+          r1.extend(VariableType0)
         else
           @index = i1
           r1 = nil
@@ -7836,26 +7898,30 @@ module OrigenVerilog
           r8 = _nt_variable_identifier
           s7 << r8
           if r8
-            r9 = _nt_s
-            s7 << r9
-            if r9
-              if (match_len = has_terminal?("=", false, index))
-                r10 = true
-                @index += match_len
+            s9, i9 = [], index
+            loop do
+              i10, s10 = index, []
+              r11 = _nt_s
+              s10 << r11
+              if r11
+                r12 = _nt_dimension
+                s10 << r12
+              end
+              if s10.last
+                r10 = instantiate_node(SyntaxNode,input, i10...index, s10)
+                r10.extend(VariableType1)
               else
-                terminal_parse_failure('"="')
+                @index = i10
                 r10 = nil
               end
-              s7 << r10
               if r10
-                r11 = _nt_s
-                s7 << r11
-                if r11
-                  r12 = _nt_constant_expression
-                  s7 << r12
-                end
+                s9 << r10
+              else
+                break
               end
             end
+            r9 = instantiate_node(SyntaxNode,input, i9...index, s9)
+            s7 << r9
           end
           if s7.last
             r7 = instantiate_node(SyntaxNode,input, i7...index, s7)

data/lib/origen_verilog.rb

@@ -26,9 +26,13 @@ module OrigenVerilog
 
   # Returns an AST for the given file
   def self.parse_file(file, options = {})
+    top_dir = Pathname.new(file).dirname
+    options[:source_dirs] ||= []
+    options[:source_dirs] << top_dir unless options[:source_dirs].include?(top_dir)
     # Evaluates all compiler directives
-    ast = Preprocessor::Parser.parse_file(file).process
+    ast = Preprocessor::Parser.parse_file(file, options).process(options)
+
     # Now parse as verilog
-    Verilog::Parser.parse(ast.to_s)
+    Verilog::Parser.parse(ast.to_s, options)
   end
 end

data/lib/origen_verilog/top_level.rb

@@ -8,7 +8,6 @@ module OrigenVerilog
       @name = options[:ast].to_a[0]
 
       options[:ast].pins.each do |node|
-        name = node.to_a.last
         if node.type == :input_declaration
           direction = :input
         elsif node.type == :ouput_declaration
@@ -21,7 +20,10 @@ module OrigenVerilog
         else
           size = 1
         end
-        add_pin name, direction: direction, size: size
+        n = node.to_a.dup
+        while n.last.is_a?(String)
+          add_pin n.pop, direction: direction, size: size
+        end
       end
     end
   end

data/lib/origen_verilog/verilog/node.rb

@@ -11,22 +11,45 @@ module OrigenVerilog
         end
       end
 
-      # Returns an array containing the names of all top-level modules in
-      # the AST
-      def module_names
-        find_all(:module_declaration).map { |n| n.to_a[0] }
-      end
-
       # Returns an array containing the AST node for all modules in the AST
       def modules
         find_all(:module_declaration)
       end
 
+      # Similar to the modules method, but removes any modules which are instantiated
+      # within other modules, therefore leaving only those which could be considered top
+      # level
+      def top_level_modules
+        mods = modules
+        modules.reject { |m| mods.any? { |mod| mod.instantiates?(m) } }
+      end
+
+      # Returns true if the node instantiates the given module node or module name
+      def instantiates?(module_or_name)
+        name = module_or_name.respond_to?(:to_a) ? module_or_name.to_a[0] : module_or_name
+        instantiations = find_all(:module_instantiation)
+        if instantiations.empty?
+          false
+        else
+          instantiations.any? { |i| i.to_a[0].to_s == name.to_s }
+        end
+      end
+
       # Returns the AST node for the module with the given name
       def module(name)
         find_all(:module_declaration).find { |n| n.to_a[0].to_s == name.to_s }
       end
 
+      # Returns the name of the node, will raise an error if called on a node type for
+      # which the name extraction is not yet implemented
+      def name
+        if type == :module_declaration
+          to_a[0]
+        else
+          fail "Don't know how to extract the name from a #{type} node yet!"
+        end
+      end
+
       # Returns an array containing all input, output and inout AST nodes
       def pins
         find_all(:input_declaration, :output_declaration, :inout_declaration)

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_verilog
 version: !ruby/object:Gem::Version
-  version: 0.2.2
+  version: 0.3.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2017-12-13 00:00:00.000000000 Z
+date: 2018-01-15 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: ast
@@ -90,7 +90,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.5.2
+rubygems_version: 2.6.8
 signing_key: 
 specification_version: 4
 summary: A parser and generator for Verilog (IEEE 1364)