origen_swd 1.0.0 → 1.1.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
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-  data.tar.gz: 0623f5d41b8a0ae7cb9fa527ecbdf1fbdf940ef2
+  metadata.gz: 32e3a4ba31f96f540948b330acce8492d086d611
+  data.tar.gz: da2d96d5848554de9567b75cf00f5d1d2f3e889f
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+  data.tar.gz: 30985d2ececf9375b45fa865cc0b881c4408d6fee57d33401663c0b2f8435b66e1e5b638491128307326b539300e1bd42b94fbaa5474c19a7a62d647d35e191e

data/config/version.rb

@@ -1,6 +1,6 @@
 module OrigenSWD
   MAJOR = 1
-  MINOR = 0
+  MINOR = 1
   BUGFIX = 0
   DEV = nil
 

data/lib/origen_swd/driver.rb

@@ -247,49 +247,51 @@ module OrigenSWD
     # @option options [String] :overlay String for pattern label to
     #   facilitate pattern overlay
     def shift_payload(reg_or_val, options)
-      cc options[:arm_debug_comment] if options.key?(:arm_debug_comment)
+      options = { no_subr: false }.merge(options)
+
+      reg = to_reg(reg_or_val, options)
       size = 32    # SWD only used to write to DP and AP registers of ARM Debugger (32 bits)
-      contains_bits = (contains_bits?(reg_or_val) || is_a_bit?(reg_or_val))
-      if options.key?(:arm_debug_overlay)
-        options[:overlay] = options[:arm_debug_overlay]
-        options[:overlay_label] = options[:arm_debug_overlay]
-      end
-      if options.key?(:overlay)
-        if options[:overlay_label].nil?
-          options[:overlay_label] = options[:overlay]
-          $tester.label(options[:overlay_label]) if options.key?(:overlay)
-        end
+
+      # tester does not support direct labels, so can't do
+      if options[:no_subr] && !$tester.respond_to?('label')
+        cc 'This tester does not support use of labels, cannot do no_subr option as requested'
+        cc '  going with subroutine overlay instead'
+        options[:no_subr] = false
       end
+
+      cc options[:arm_debug_comment] if options.key?(:arm_debug_comment)
       swd_clk.drive(1)
-      size.times do |i|
-        if options[:read]
-          # If it's a register support bit-wise reads
-          if contains_bits
-            if reg_or_val[i].is_to_be_stored?
+
+      reg_overlay = extract_reg_overlay(reg)
+      if reg_overlay && !options[:no_subr] && !Origen.mode.simulation?
+        Origen.tester.call_subroutine(reg[0].overlay_str)
+      else
+        last_overlay_label = ''
+        size.times do |i|
+          swd_dio.dont_care
+          if options[:read]
+            if reg[i].is_to_be_stored?
               Origen.tester.store_next_cycle(swd_dio)
               swd_dio.dont_care if Origen.tester.j750?
-            elsif reg_or_val[i].has_overlay?
-              $tester.label(reg_or_val[i].overlay_str)
-            elsif reg_or_val[i].is_to_be_read?
-              swd_dio.assert(reg_or_val[i] ? reg_or_val[i] : 0)
-            elsif options[:compare_data]
-              swd_dio.assert(reg_or_val[i] ? reg_or_val[i] : 0)
-            else
-              swd_dio.dont_care
+            elsif reg[i].is_to_be_read?
+              swd_dio.assert(reg[i] ? reg[i] : 0)
             end
           else
-            if options[:compare_data] && reg_or_val
-              swd_dio.assert(reg_or_val[i] ? reg_or_val[i] : 0)
-            else
-              swd_dio.dont_care
+            swd_dio.drive(reg_or_val[i])
+          end
+
+          if reg[i].has_overlay? && !Origen.mode.simulation? && tester.respond_to?('label')
+            if reg[i].overlay_str != last_overlay_label
+              Origen.tester.label(reg[i].overlay_str)
+              last_overlay_label = reg[i].overlay_str
             end
+            tester.cycle dont_compress: true
+          else
+            tester.cycle
           end
-          $tester.cycle
-        else
-          $tester.label("// SWD Data Pin #{i}") if options.key?(:overlay) && !Origen.mode.simulation?
-          swd_dio.drive!(reg_or_val[i])
         end
       end
+
       # Clear read and similar flags to reflect that the request has just
       # been fulfilled
       reg_or_val.clear_flags if reg_or_val.respond_to?(:clear_flags)
@@ -317,5 +319,33 @@ module OrigenSWD
     def swd_dio
       owner.pin(:swd_dio)
     end
+
+    # Converts reg_or_val to reg
+    def to_reg(reg_or_val, options)
+      if reg_or_val.respond_to?(:data)
+        reg = reg_or_val.dup
+      else
+        reg = Reg.dummy(32)
+        if reg_or_val.nil?
+          reg.read(options[:compare_data]) if options[:compare_data]
+        else
+          reg.write(reg_or_val)
+          reg.read if options[:read]
+        end
+      end
+      reg.overlay(options[:arm_debug_overlay]) if options.key?(:arm_debug_overlay)
+      reg.overlay(options[:overlay_label]) if options.key?(:overlay)
+      reg
+    end
+
+    # Return overlay sting if same for all bits, otherwise return nil
+    def extract_reg_overlay(reg)
+      ovl = reg[0].overlay_str
+      reg.size.times do |i|
+        return nil unless reg[i].has_overlay?
+        return nil if ovl != reg[i].overlay_str || ovl.nil?
+      end
+      ovl
+    end
   end
 end

data/pattern/example_reg.rb

@@ -11,14 +11,21 @@ Pattern.create do
   reg.write(0xFF01FF01)
   swd.write(0, reg, 0xFF01FF01)
 
-  test "Write to DR register with overlay"
+  test "Write to DR register with overlay, no subroutine"
   reg.overlay("write_overlay")
+  swd.write(0, reg, 0xFF01FF01, no_subr: true)
+  reg.overlay(nil)
+
+  test "Write to DR register with overlay, use subroutine if available"
+  reg.overlay("write_overlay_subr")
   swd.write(0, reg, 0xFF01FF01)
+  reg.overlay(nil)
     
   test "Write to DR register with single bit overlay"
   reg.overlay(nil)
-  reg.bit(:bit).overlay("write_overlay")
+  reg.bit(:bit).overlay("bit_write_overlay")
   swd.write(0, reg, 0xFF01FF01)
+  reg.overlay(nil)
 
 
   test "Read full DR register"
@@ -26,6 +33,18 @@ Pattern.create do
   reg.read
   swd.read(0, reg)
 
+  test "Full register (32 bits) read with overlay, no subroutine"
+  reg.overlay('read_overlay')
+  reg.read
+  swd.read(0, reg, no_subr: true)
+  reg.overlay(nil)
+
+  test "Full register (32 bits) read with overlay, use subroutine if available"
+  reg.overlay('read_overlay_subr')
+  reg.read
+  swd.read(0, reg)
+  reg.overlay(nil)
+
   test "Read single bit out of DR register"
   reg.bit(:bit).read
   swd.read(0, reg)

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_swd
 version: !ruby/object:Gem::Version
-  version: 1.0.0
+  version: 1.1.0
 platform: ruby
 authors:
 - Ronnie Lajaunie
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2017-04-28 00:00:00.000000000 Z
+date: 2017-05-10 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -64,7 +64,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.5.2
+rubygems_version: 2.6.7
 signing_key: 
 specification_version: 4
 summary: Driver for single-wire-debug interface.