origen_sim 0.20.7 → 0.21.0

checksums.yaml

@@ -1,7 +1,7 @@
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data/config/commands.rb

@@ -23,13 +23,36 @@ when "sim:build_example"
       ARGV.delete_at(index)
       Origen.environment.temporary = ARGV.delete_at(index)
     end
+    if ['cadence'].include?(Origen.environment.name)
+      cmd += ' --define ORIGEN_SIM_CADENCE'
+    elsif ['synopsys', 'synopsys_verdi'].include?(Origen.environment.name)
+      cmd += ' --define ORIGEN_SIM_SYNOPSIS'
+    elsif ['icarus'].include?(Origen.environment.name)
+      cmd += ' --define ORIGEN_SIM_ICARUS'
+    end
+
+    clean = false
+    if ARGV.include?('--clean')
+      ARGV.delete_at(ARGV.index('--clean'))
+      clean = true
+    end
     cmd += ' ' + ARGV.join(' ') unless ARGV.empty?
+
+
     # Enable wreal pins in the DUT RTL
     cmd += '  --define ORIGEN_WREAL' if ARGV.include?('--wreal')
+    #cmd += "  --define ORIGEN_WREALAVG --sv --force_pin_type vdd:real --force_pin_type ana:real --passthrough \"-sysv_ext +.v -define ORIGEN_WREALAVG +define+ORIGEN_SIM_CADENCE #{Origen.app.root}/top.scs\"" if ARGV.include?('--wrealavg')
+    cmd += "  --define ORIGEN_WREALAVG --sv --force_pin_type vdd:real --force_pin_type ana:real --passthrough \"+define+ORIGEN_SIM_SYNOPSIS\"" if ARGV.include?('--wrealavg')
     output = `#{cmd}`
     puts output
     Origen.load_target
     dir = "simulation/default/#{tester.simulator.config[:vendor]}"
+    
+    if clean
+      puts "Cleaning directory: #{dir}"
+      FileUtils.rm_r(dir)
+    end
+    
     FileUtils.mkdir_p(dir)
     Dir.chdir dir do
       case tester.simulator.config[:vendor]
@@ -42,7 +65,10 @@ when "sim:build_example"
 
       when :cadence
         output =~ /\n(.*irun .*)\n/
-        system $1.gsub('stub', 'dut1')
+        compile_cmd = $1.gsub('stub', 'dut1')
+        compile_cmd.gsub!('origen.v', 'origen.sv') if cmd.include?('--define ORIGEN_SV')
+        puts compile_cmd.green
+        system compile_cmd
 
       when :synopsys
         if tester.simulator.config[:verdi]

data/config/shared_commands.rb

@@ -48,7 +48,7 @@ when "sim:unpack"
 when "sim:run"
   OrigenSim.run_source(ARGV[0])
   exit 0
-  
+
 #when "sim:list"
 #  require "#{Origen.root!}/lib/origen_sim/commands/pack"
 #  OrigenSim::Commands::Pack.list
@@ -60,7 +60,14 @@ else
  sim:co       Checkout a simulation snapshot
  sim:pack     Packs the snapshot into a compressed directory
  sim:unpack   Unpacks a snapshot
- sim:list     List the available snapshot packs
   EOT
+ # sim:list     List the available snapshot packs
+  
+ if OrigenTesters.respond_to?(:decompile)
+  @plugin_commands << <<-EOT
+ sim:run      Simulates the given source without using any of Origen's 'startup' collateral.
+              Requires: a decompiler for the given source and timing information setup beforehand. 
+  EOT
+ end
 
 end

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 20
-  BUGFIX = 7
+  MINOR = 21
+  BUGFIX = 0
   DEV = nil
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/ext/bridge.c

@@ -112,11 +112,11 @@ static void define_pin(char * name, char * pin_ix, char * drive_wave_ix, char *
   (*pin).drive_data = 0;
 
 
-  char * driver = (char *) malloc(strlen(name) + 16);
+  char * driver = (char *) malloc(strlen(name) + ORIGEN_SIM_TB_NAME_LEN + 7); // testbench name + . + 'pins.' + '\0'
   strcpy(driver, ORIGEN_SIM_TESTBENCH_CAT("pins."));
   strcat(driver, name);
 
-  char * data = (char *) malloc(strlen(driver) + 16);
+  char * data = (char *) malloc(strlen(driver) + 6);
   strcpy(data, driver);
   strcat(data, ".data");
   (*pin).data = vpi_handle_by_name(data, NULL);
@@ -129,25 +129,25 @@ static void define_pin(char * name, char * pin_ix, char * drive_wave_ix, char *
     (*pin).present = true;
   }
 
-  char * drive = (char *) malloc(strlen(driver) + 16);
+  char * drive = (char *) malloc(strlen(driver) + 7);
   strcpy(drive, driver);
   strcat(drive, ".drive");
   (*pin).drive = vpi_handle_by_name(drive, NULL);
   free(drive);
 
-  char * force = (char *) malloc(strlen(driver) + 16);
+  char * force = (char *) malloc(strlen(driver) + 12);
   strcpy(force, driver);
   strcat(force, ".force_data");
   (*pin).force_data = vpi_handle_by_name(force, NULL);
   free(force);
 
-  char * compare = (char *) malloc(strlen(driver) + 16);
+  char * compare = (char *) malloc(strlen(driver) + 9);
   strcpy(compare, driver);
   strcat(compare, ".compare");
   (*pin).compare = vpi_handle_by_name(compare, NULL);
   free(compare);
 
-  char * capture = (char *) malloc(strlen(driver) + 16);
+  char * capture = (char *) malloc(strlen(driver) + 9);
   strcpy(capture, driver);
   strcat(capture, ".capture");
   (*pin).capture = vpi_handle_by_name(capture, NULL);
@@ -764,7 +764,7 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
         // Set Pattern Name
         //   a^atd_ramp_25mhz
         case 'a' :
-          handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("debug.pattern"), NULL);
+          handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("pattern")), NULL);
           arg1 = strtok(NULL, "^");
 
           v.format = vpiStringVal;
@@ -800,7 +800,7 @@ PLI_INT32 bridge_wait_for_msg(p_cb_data data) {
           arg1 = strtok(NULL, "^");
           arg2 = strtok(NULL, "^");
 
-          strcpy(comment, ORIGEN_SIM_TESTBENCH_CAT("debug.comments"));
+          strcpy(comment, ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("comments")));
           strcat(comment, arg1);
 
           handle = vpi_handle_by_name(comment, NULL);
@@ -1003,7 +1003,7 @@ static void end_simulation() {
   s_vpi_value v;
 
   // Setting this node will cause the testbench to call $finish
-  handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("finish"), NULL);
+  handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_FINISH_SIG_NAME), NULL);
   v.format = vpiDecStrVal;
   v.value.str = "1";
   vpi_put_value(handle, &v, NULL, vpiNoDelay);
@@ -1071,7 +1071,7 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
   if (match_loop_open) {
     match_loop_error_count++;
 
-    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("debug.match_errors"), NULL);
+    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("match_errors")), NULL);
     val.format = vpiIntVal;
     val.value.integer = match_loop_error_count;
     vpi_put_value(handle, &val, NULL, vpiNoDelay);
@@ -1108,7 +1108,7 @@ PLI_INT32 bridge_on_miscompare(PLI_BYTE8 * user_dat) {
 
     error_count++;
 
-    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT("debug.errors"), NULL);
+    handle = vpi_handle_by_name(ORIGEN_SIM_TESTBENCH_CAT(ORIGEN_SIM_DEBUG_MODULE_CAT("errors")), NULL);
     val.format = vpiIntVal;
     val.value.integer = error_count;
     vpi_put_value(handle, &val, NULL, vpiNoDelay);

data/ext/common.h

@@ -14,6 +14,7 @@
 /// Prepends the testbench name to the signal.
 /// e.g.: TESTBENCH_CAT(pins) => TESTBENCH_NAME.pins => origen.pins
 #define ORIGEN_SIM_TESTBENCH_CAT(signal) ORIGEN_SIM_TESTBENCH_NAME "." signal
+#define ORIGEN_SIM_DEBUG_MODULE_CAT(signal) ORIGEN_SIM_DEBUG_MODULE_NAME "." signal
 
 #ifdef ENABLE_DEBUG
 /* #define DEBUG(fmt, args...) fprintf(stderr, "DEBUG: %s:%d:%s(): " fmt, \

data/ext/defines.h.erb

@@ -1,8 +1,11 @@
 #ifndef DEFINES_H
 #define DEFINES_H
 
+#define ORIGEN_FINISH_SIG_NAME "<%= options[:finish_signal] %>"
 #define ORIGEN_SIM_VERSION "<%= OrigenSim::VERSION %>"
 #define ORIGEN_SIM_TESTBENCH_NAME "<%= options[:testbench_name] %>"
+#define ORIGEN_SIM_DEBUG_MODULE_NAME "<%= options[:debug_module_name] %>"
+#define ORIGEN_SIM_TB_NAME_LEN <%= options[:testbench_name].size %>
 #define LOG_DEBUG 0
 #define LOG_INFO 1
 #define LOG_WARN 2

data/lib/origen_sim/commands/build.rb

@@ -3,7 +3,22 @@ require 'origen_sim'
 require_relative '../../../config/version'
 require 'origen_verilog'
 
-options = { incl_files: [], source_dirs: [], testbench_name: 'origen', defines: [], user_details: {}, initial_pin_states: {}, verilog_top_output_name: 'origen' }
+options = {
+  incl_files:              [],
+  source_dirs:             [],
+  testbench_name:          'origen',
+  defines:                 [],
+  user_details:            {},
+  initial_pin_states:      {},
+  forced_pin_types:        {},
+  verilog_top_output_name: 'origen',
+  file_type:               :v,
+  power_pins:              [],
+  ground_pins:             [],
+  virtual_pins:            [],
+  other_pins:              [],
+  passthrough:             []
+}
 
 # App options are options that the application can supply to extend this command
 app_options = @application_options || []
@@ -22,8 +37,9 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('-s', '--source_dir PATH', 'Directories to look for include files in (the directory containing the top-level is already considered)') do |path|
     options[:source_dirs] << path
   end
-  opts.on('--sv', 'Generate a .sv file instead of a .v file.') { |t| options[:sv] = t }
+  opts.on('--sv', 'Generate a .sv file instead of a .v file.') { |t| options[:sv] = t; options[:file_type] = :sv }
   opts.on('--wreal', 'Enable real number modeling support on DUT pins defined as real wires (wreal)') { |t| options[:wreal] = t }
+  opts.on('--wrealavg', 'Enable real number modeling support on DUT pins defined as real wires - averaged (wrealavg)') { |t| options[:wrealavg] = t }
   opts.on('--verilog_top_output_name NAME', 'Renames the output filename from origen.v to NAME.v') do |name|
     options[:verilog_top_output_name] = name
   end
@@ -39,7 +55,25 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
     end
     (options[:initial_pin_states])[name.to_sym] = OrigenSim::INIT_PIN_STATE_MAPPING[state]
   end
-  opts.on('--include FILE' 'Specify files to include in the top verilog file.') { |f| options[:incl_files] << f }
+  opts.on('--force_pin_type PIN_AND_TYPE', 'Overwrite the pin driver discerned from DUT module') do |pin_and_type|
+    name, type = pin_and_type.split(':')
+    (options[:forced_pin_types])[name] = OrigenSim::FORCE_PIN_TYPES_MAPPING[type]
+  end
+  opts.on('--power_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are power pins, seperated by tildas') do |str_or_regex|
+    options[:power_pins] << str_or_regex
+  end
+  opts.on('--ground_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are ground pins, seperated by tildas') do |str_or_regex|
+    options[:ground_pins] << str_or_regex
+  end
+  opts.on('--virtual_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are virtual pins, seperated by tildas') do |str_or_regex|
+    options[:virtual_pins] << str_or_regex
+  end
+  opts.on('--other_pins PINS_AND_REGEXES', 'Using pin names or regexes, indicate which pins are \'other\' pins, seperated by tildas') do |str_or_regex|
+    options[:other_pins] << str_or_regex
+  end
+  opts.on('--include FILE', 'Specify files to include in the top verilog file.') { |f| options[:incl_files] << f }
+  opts.on('--vendor VENDOR', 'Specify the target vendor (Cadence, Synopsis, Icarus') { |v| options[:vendor] = v.downcase.to_sym }
+  opts.on('--passthrough SWITCHES', 'Raw switches that will be ignored by OrigenSim, but appear in the final build command') { |s| options[:passthrough] << s }
 
   # Specifying snapshot details
   opts.on('--device_name NAME', '(Snapshot Detail) Specify a device name') { |n| options[:device_name] = n }
@@ -48,6 +82,9 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('--revision_note REV_NOTE', '(Snapshot Detail) Specify a brief note on this revision of the snapshot') { |n| options[:revision_note] = n }
   opts.on('--author AUTHOR', '(Snapshot Detail) Specify the author of the snapshot (default is just Origen.current_user)') { |a| options[:author] = a }
 
+  opts.on('--finish_signal FINISH_SIGNAL', 'Specify the finish signal') { |f| options[:finish_signal] = f }
+  opts.on('--debug_module_name MOD_NAME', 'Specify the debug module name') { |d| options[:debug_module_name] = d }
+
   # User-defined snapshot details
   opts.on('--USER_DETAIL NAME_AND_VALUE', 'Specify custom user-defined details to build into the snapshot details. Format as NAME:VALUE, e.g.: \'--USER_DETAIL BUILD_TYPE:RTL\'') do |name_and_value|
     name, value = name_and_value.split(':')
@@ -68,8 +105,41 @@ Usage: origen sim:build TOP_LEVEL_VERILOG_FILE [options]
   opts.on('-h', '--help', 'Show this message') { puts opts; exit 0 }
 end
 
+build_cmd = 'origen sim:build ' + ARGV.map do |arg|
+  # Command-line-ify some of the argument values.
+  if arg.include?(' ') || (arg[0] == '/' && arg[1] == '/' && arg.size > 1)
+    # if the argument is a string, wrap it in quotes.
+    # Likewise, if the argument looks like a regex, wrap it in quotes as well.
+    arg = "\"#{arg}\""
+  end
+
+  # If the argument includes any !s, escape them
+  arg = arg.gsub('!', '\!')
+
+  arg
+end.join(' ')
 opt_parser.parse! ARGV
 
+options.select { |k, v| [:power_pins, :ground_pins, :virtual_pins, :other_pins].include?(k) }.each do |k, pins_or_regexes|
+  options[k] = pins_or_regexes.map { |input| input.split('~') }.flatten.map do |p|
+    if p.start_with?('/') && p.end_with?('/')
+      Regexp.new(p[1..-2])
+    else
+      p
+    end
+  end
+end
+
+options[:forced_pin_types] = options[:forced_pin_types].map do |pin_or_regex, type|
+  if pin_or_regex.start_with?('/') && pin_or_regex.end_with?('/')
+    # run this as a regex, not as a single pin name
+    # Cut out the leading / and trailing / characters though
+    [Regexp.new(pin_or_regex.to_s[1..-2]), type]
+  else
+    [pin_or_regex, type]
+  end
+end.to_h
+
 def _exit_fail_
   if $_testing_build_return_dut_
     return nil
@@ -115,7 +185,7 @@ end
 
 rtl_top_module = mod.name
 
-mod.to_top_level # Creates dut
+mod.to_top_level(options) # Creates dut
 
 # Update the pins with any settings from the command line
 options[:initial_pin_states].each do |pin, state|
@@ -138,7 +208,7 @@ else
                            quiet:             true,
                            preserve_target:   true,
                            options:           {
-                             vendor:            :cadence,
+                             vendor:            options[:vendor],
                              top:               dut.name,
                              testbench_name:    options[:testbench_name],
                              incl:              options[:incl_files],
@@ -147,7 +217,13 @@ else
                              revision_note:     options[:revision_note],
                              parent_tb_version: options[:testbench_version],
                              user_details:      options[:user_details],
-                             author:            options[:author]
+                             author:            options[:author],
+                             build_cmd:         build_cmd,
+                             file_type:         options[:file_type],
+                             testbench:         options[:testbench_name] || 'origen',
+                             top_level_name:    options[:top_level_name] || 'dut',
+                             finish_signal:     options[:finish_signal] || 'finish',
+                             debug_module_name: options[:debug_module_name] || 'debug'
                            }
 
   Origen.app.runner.launch action:            :compile,
@@ -183,6 +259,16 @@ else
     )
   end
 
+  if options[:wrealavg]
+    SYNOPSYS_SWITCHES += %w(
+      +define+ORIGEN_WREALAVG
+      -realport
+      -sverilog
+      -lca
+      -xlrm\ coerce_nettype
+    )
+  end
+
   SYNOPSYS_DVE_SWITCHES = SYNOPSYS_SWITCHES + %w(
     +define+ORIGEN_VPD
   )
@@ -212,96 +298,108 @@ else
     )
   end
 
-  puts
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Icarus Verilog'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Compile the VPI extension using the following command:'
-  puts
-  puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  puts "  #{output_directory}/#{output_name} \\"
-  puts '  -o origen.vvp \\'
-  puts '  -DORIGEN_VCD'
-  puts
-  puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
-  puts
-  puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
-  puts
-  puts "  #{output_directory}/origen.vpi"
-  puts '  origen.vvp'
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Synopsys VCS w/ DVE Waveviewer'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  SYNOPSYS_DVE_SWITCHES.each do |switch|
-    puts "  #{switch} \\"
+  if options[:wrealavg]
+    CADENCE_SWITCHES += %w(
+      +define+ORIGEN_WREALAVG
+    )
   end
+
   puts
-  puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_DVE_SWITCHES.join(' ')
-  puts
-  puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
-  puts
-  puts '  simv'
-  puts '  simv.daidir'
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Synopsys VCS w/ Verdi Waveviewer'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  SYNOPSYS_VERDI_SWITCHES.each do |switch|
-    puts "  #{switch} \\"
+  if options[:vendor].nil? || options[:vendor] == :icarus
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Icarus Verilog'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Compile the VPI extension using the following command:'
+    puts
+    puts "  cd #{output_directory} && #{ENV['ORIGEN_SIM_IVERILOG_VPI'] || 'iverilog-vpi'} *.c --name=origen && cd #{Pathname.pwd}"
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+    puts
+    puts "  #{output_directory}/#{output_name} \\"
+    puts '  -o origen.vvp \\'
+    puts '  -DORIGEN_VCD'
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional source dirs with more -I options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_IVERILOG'] || 'iverilog'} #{rtl_top} #{output_directory}/#{output_name} -o origen.vvp -DORIGEN_VCD -I #{Pathname.new(rtl_top).dirname}"
+    puts
+    puts 'Copy the following files (produced by iverilog) to simulation/<target>/icarus/. within your Origen application:'
+    puts
+    puts "  #{output_directory}/origen.vpi"
+    puts '  origen.vvp'
   end
-  puts
-  puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_VERDI_SWITCHES.join(' ')
-  puts
-  puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
-  puts
-  puts '  simv'
-  puts '  simv.daidir'
-  puts
-  puts '-----------------------------------------------------------'
-  puts 'Cadence Incisive (irun)'
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
-  puts
-  CADENCE_SWITCHES.each do |switch|
-    puts "  #{switch} \\"
+  if options[:vendor].nil? || options[:vendor] == :synopsis
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Synopsys VCS w/ DVE Waveviewer'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+    puts
+    SYNOPSYS_DVE_SWITCHES.each do |switch|
+      puts "  #{switch} \\"
+    end
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_DVE_SWITCHES.join(' ') + (options[:passthrough] ? " #{options[:passthrough].join(' ')}" : '')
+    puts
+    puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
+    puts
+    puts '  simv'
+    puts '  simv.daidir'
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Synopsys VCS w/ Verdi Waveviewer'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+    puts
+    SYNOPSYS_VERDI_SWITCHES.each do |switch|
+      puts "  #{switch} \\"
+    end
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional +incdir+ options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_VCS'] || 'vcs'} #{rtl_top} +incdir+#{Pathname.new(rtl_top).dirname} " + SYNOPSYS_VERDI_SWITCHES.join(' ') + (options[:passthrough] ? " #{options[:passthrough].join(' ')}" : '')
+    puts
+    puts 'Copy the following files (produced by vcs) to simulation/<target>/synopsys/. within your Origen application:'
+    puts
+    puts '  simv'
+    puts '  simv.daidir'
+    puts
+    puts '-----------------------------------------------------------'
+    puts 'Cadence Incisive (irun)'
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Add the following to your build script (AND REMOVE ANY OTHER TESTBENCH!):'
+  end
+  if options[:vendor].nil? || options[:vendor] == :cadence
+    puts
+    CADENCE_SWITCHES.each do |switch|
+      puts "  #{switch} \\"
+    end
+    puts
+    puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
+    puts
+    puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} -incdir #{Pathname.new(rtl_top).dirname} " + CADENCE_SWITCHES.join(' ') + (options[:passthrough] ? " #{options[:passthrough].join(' ')}" : '')
+    puts
+    puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
+    puts
+    puts '  INCA_libs'
+    puts
+    puts '-----------------------------------------------------------'
+    puts
+    puts 'Testbench and VPI extension created!'
+    puts
+    puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
+    puts
+    puts "  #{output_directory}/#{rtl_top_module}.rb"
+    puts
+    puts 'See above for what to do now to create an Origen-enabled simulation object for your particular simulator.'
   end
-  puts
-  puts 'Here is an example which may work for the file you just parsed (add additional -incdir options at the end if required):'
-  puts
-  puts "  #{ENV['ORIGEN_SIM_IRUN'] || 'irun'} #{rtl_top} -incdir #{Pathname.new(rtl_top).dirname} " + CADENCE_SWITCHES.join(' ')
-  puts
-  puts 'Copy the following directory (produced by irun) to simulation/<target>/cadence/. within your Origen application:'
-  puts
-  puts '  INCA_libs'
-  puts
-  puts '-----------------------------------------------------------'
-  puts
-  puts 'Testbench and VPI extension created!'
-  puts
-  puts 'This file can be imported into an Origen top-level DUT model to define the pins:'
-  puts
-  puts "  #{output_directory}/#{rtl_top_module}.rb"
-  puts
-  puts 'See above for what to do now to create an Origen-enabled simulation object for your particular simulator.'
   puts
 
 end

data/lib/origen_sim/origen/pins/pin.rb

@@ -57,7 +57,7 @@ module Origen
 
       alias_method :_orig_drive, :drive
       def drive(*args)
-        if _analog_pin_? && simulation_running? && tester.simulator.wreal?
+        if _analog_pin_? && simulation_running? && tester.simulator.real?
           tester.poke("#{driver_net}.drive_en", 1)
           tester.poke("#{driver_net}.drive", args.first + 0.0)
         else
@@ -68,11 +68,11 @@ module Origen
 
       alias_method :_orig_assert, :assert
       def assert(*args)
-        if _analog_pin_? && simulation_running? && tester.simulator.wreal?
+        if _analog_pin_? && simulation_running? && tester.simulator.real?
           drive_enabled = tester.peek("#{driver_net}.drive_en").to_i
           if drive_enabled == 1
-            tester.poke("#{driver_net}.drive_en", 0)
-            tester.cycle
+            # tester.poke("#{driver_net}.drive_en", 0)
+            # tester.cycle
           end
           measured = tester.peek("#{driver_net}.pin", true)
           # Could implement checking/limits here in future

data/lib/origen_sim/origen/top_level.rb

@@ -6,18 +6,27 @@ module Origen
     # Optionally pass in a type: option set to either :analog or :digital to
     # have only the pins with that type returned
     def rtl_pins(options = {})
+      _add_rtl_pin_ = lambda do |name, pin, opts, p|
+        options = {}
+        unless pin.rtl_name.to_s.downcase == 'nc' ||
+               (opts[:type] && pin.type && opts[:type] != pin.type) ||
+               (pin.meta[:origen_sim_init_pin_state] && pin.meta[:origen_sim_init_pin_state] == -2)
+          if pin.primary_group
+            options[:group] = true
+          end
+          p << [name, pin, options]
+        end
+      end
+
+      pin_roles = [:pins, :power_pins, :ground_pins, :virtual_pins, :other_pins]
       @rtl_pins ||= {}
       @rtl_pins[options[:type]] ||= begin
         opts = options.dup
         p = []
-        pins.each do |name, pin|
-          options = {}
-          unless pin.rtl_name.to_s.downcase == 'nc' ||
-                 (opts[:type] && pin.type && opts[:type] != pin.type)
-            if pin.primary_group
-              options[:group] = true
-            end
-            p << [name, pin, options]
+        # pins.each do |name, pin|
+        pin_roles.each do |role|
+          dut.send(role).each do |name, pin|
+            _add_rtl_pin_.call(name, pin, opts, p)
           end
         end
         p

data/lib/origen_sim/origen_testers/api.rb

@@ -26,7 +26,7 @@ module OrigenTesters
       if @sim_capture || @sim_delay
         fail 'Nesting of sim_capture and/or sim_delay blocks is not yet supported!'
       end
-      Origen::OrgFile.open(id, path: OrigenSim.capture_dir) do |org_file|
+      Origen::OrgFile.open(id, path: (options[:path] || OrigenSim.capture_dir)) do |org_file|
         @org_file = org_file
         if update_capture?
           @sim_delay = true

data/lib/origen_sim/simulator.rb

@@ -21,7 +21,7 @@ module OrigenSim
 
     # These config attributes are accepted by OrigenSim, but cannot be
     # 'Marshal-ed'.
-    NON_DATA_CONFIG_ATTRIBUTES = [:post_process_run_cmd]
+    NON_DATA_CONFIG_ATTRIBUTES = [:post_process_run_cmd, :post_process_view_wave_cmd, :post_process_probe_cmd]
 
     TIMESCALES = { -15 => '1fs',
                    -14 => '10fs',
@@ -86,6 +86,26 @@ module OrigenSim
       config[:post_process_run_cmd]
     end
 
+    def post_process_view_wave_cmd
+      config[:post_process_view_wave_cmd]
+    end
+
+    def post_process_probe_cmd
+      config[:post_process_probe_cmd]
+    end
+
+    def post_process_probe_cmd?
+      !post_process_probe_cmd.nil?
+    end
+
+    def force_config_update?
+      !!config[:force_config_update]
+    end
+
+    def debug_path
+      config[:debug_module_path] || 'debug'
+    end
+
     def fetch_simulation_objects(options = {})
       sid = options[:id] || id
       ldir = "#{Origen.root}/simulation/#{sid}"
@@ -166,8 +186,8 @@ module OrigenSim
       clear_artifacts
 
       # Add any artifacts in the given artifact path
-      if Dir.exist?(default_artifact_dir)
-        default_artifact_dir.children.each { |a| artifact(a.basename.to_s, target: a) }
+      if Dir.exist?(self.class.default_artifact_dir)
+        self.class.default_artifact_dir.children.each { |a| artifact(a.basename.to_s, target: a) }
       end
 
       # Add any artifacts from the target-specific path (simulation/<target>/artifacts). Files of the same name
@@ -197,7 +217,7 @@ module OrigenSim
       self
     end
 
-    def default_artifact_dir
+    def self.default_artifact_dir
       # Removed this from a constant at the top of the file since it gave boot errors when the file was
       # being required while Origen.app was still loading
       Pathname("#{Origen.app.root}/simulation/application/artifacts")
@@ -212,7 +232,7 @@ module OrigenSim
     end
 
     def target_artifact_dir
-      Pathname(@configuration[:target_artifact_dir] || "#{Origen.app.root}/simulation/#{id}/artifacts")
+      Pathname(@configuration[:target_artifact_dir] || "#{Origen.app.root}/simulation/").join("#{id}/artifacts")
     end
 
     def artifact_run_dir
@@ -253,9 +273,11 @@ module OrigenSim
     # be checked into your Origen app's repository
     def compiled_dir
       @compiled_dir ||= begin
-        d = "#{Origen.root}/simulation/#{id}/#{config[:vendor]}"
-        FileUtils.mkdir_p(d)
-        d
+        config[:compiled_dir] || begin
+          d = "#{Origen.root}/simulation/#{id}/#{config[:vendor]}"
+          FileUtils.mkdir_p(d)
+          d
+        end
       end
     end
 
@@ -323,35 +345,45 @@ module OrigenSim
       when :cadence
         input_file = "#{tmp_dir}/#{wave_file_basename}.tcl"
         if !File.exist?(input_file) || config_changed?
+          probe_cmd = "probe -create -shm #{testbench_top} -depth all -database waves"
+          if post_process_probe_cmd?
+            probe_cmd = post_process_probe_cmd.call(probe_cmd, self, fast_probe: false)
+          end
+
           Origen.app.runner.launch action:            :compile,
                                    files:             "#{Origen.root!}/templates/probe.tcl.erb",
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir:           wave_dir,
-                                                        wave_file:     wave_file_basename,
-                                                        force:         config[:force],
-                                                        setup:         config[:setup],
-                                                        depth:         :all,
-                                                        testbench_top: config[:testbench_top] || 'origen'
+                                   options:           { dir:        wave_dir,
+                                                        wave_file:  wave_file_basename,
+                                                        force:      config[:force],
+                                                        setup:      config[:setup],
+                                                        tcl_inputs: config[:tcl_inputs],
+                                                        probe_cmd:  probe_cmd
                                                       },
                                    output_file_name:  "#{wave_file_basename}.tcl",
                                    preserve_target:   true
         end
+
         input_file_fast = "#{tmp_dir}/#{wave_file_basename}_fast.tcl"
         if !File.exist?(input_file_fast) || config_changed?
           fast_probe_depth = config[:fast_probe_depth] || 1
+          probe_cmd = "probe -create -shm #{testbench_top} -depth #{fast_probe_depth} -database waves"
+          if post_process_probe_cmd?
+            probe_cmd = post_process_probe_cmd.call(probe_cmd, self, fast_probe: true)
+          end
+
           Origen.app.runner.launch action:            :compile,
                                    files:             "#{Origen.root!}/templates/probe.tcl.erb",
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir:           wave_dir,
-                                                        wave_file:     wave_file_basename,
-                                                        force:         config[:force],
-                                                        setup:         config[:setup],
-                                                        depth:         fast_probe_depth,
-                                                        testbench_top: config[:testbench_top] || 'origen'
+                                   options:           { dir:       wave_dir,
+                                                        wave_file: wave_file_basename,
+                                                        force:     config[:force],
+                                                        setup:     config[:setup],
+                                                        probe_cmd: probe_cmd
                                                       },
                                    output_file_name:  "#{wave_file_basename}_fast.tcl",
                                    preserve_target:   true
@@ -365,10 +397,11 @@ module OrigenSim
         cmd += " -nclibdirpath #{compiled_dir}"
 
       when :synopsys
+        syn_comp_n = config[:synopsys_compiled_name] || 'simv'
         if configuration[:verdi]
-          cmd = "#{compiled_dir}/simv +socket+#{socket_id} +FSDB_ON +fsdbfile+#{Origen.root}/waves/#{id}/#{wave_file_basename}.fsdb +memcbk +vcsd"
+          cmd = "#{compiled_dir}/#{syn_comp_n} +socket+#{socket_id} +FSDB_ON +fsdbfile+#{Origen.root}/waves/#{id}/#{wave_file_basename}.fsdb +memcbk +vcsd"
         else
-          cmd = "#{compiled_dir}/simv +socket+#{socket_id} -vpd_file #{wave_file_basename}.vpd"
+          cmd = "#{compiled_dir}/#{syn_comp_n} +socket+#{socket_id} -vpd_file #{wave_file_basename}.vpd"
         end
 
       when :generic
@@ -490,6 +523,10 @@ module OrigenSim
         Origen.log.warn "OrigenSim does not know the command to view waveforms for vendor :#{config[:vendor]}!"
 
       end
+
+      cmd = post_process_view_wave_cmd.call(cmd, self) if post_process_view_wave_cmd
+      fail "OrigenSim: :post_process_view_wave_cmd returned object of class #{cmd.class}. Must return a String." unless cmd.is_a?(String)
+
       cmd
     end
 
@@ -906,13 +943,13 @@ module OrigenSim
 
     def error(message)
       simulation.logged_errors = true
-      poke "#{testbench_top}.debug.errors", error_count + 1
+      poke "#{testbench_top}.#{debug_path}.errors", error_count + 1
       log message, :error
     end
 
     # Returns the current simulation error count
     def error_count
-      peek("#{testbench_top}.debug.errors").to_i
+      peek("#{testbench_top}.#{debug_path}.errors").to_i
     end
 
     # Returns the current value of the given net, or nil if the given path does not
@@ -1091,7 +1128,7 @@ module OrigenSim
 
     # Returns true if the config has been changed since the last time we called save_config_signature
     def config_changed?
-      Origen.app.session.origen_sim["#{id}_config"] != config.except(*NON_DATA_CONFIG_ATTRIBUTES)
+      config[:force_config_update] || Origen.app.session.origen_sim["#{id}_config"] != config.except(*NON_DATA_CONFIG_ATTRIBUTES)
     end
 
     # Locally saves a signature for the current config, this will cause config_changed? to return false
@@ -1154,7 +1191,7 @@ module OrigenSim
 
     def match_errors
       if dut_version > '0.15.0'
-        peek("#{testbench_top}.debug.match_errors").to_i
+        peek("#{testbench_top}.#{debug_path}.match_errors").to_i
       else
         peek("#{testbench_top}.pins.match_errors").to_i
       end
@@ -1165,7 +1202,7 @@ module OrigenSim
       unless val.nil?
         # All zeros seems to be what an empty string is returned from the VPI,
         # Otherwise, break the string up into 8-bit chunks and decode the ASCII>
-        val = (val.to_s == 'b00000000' ? '' : val.to_s[1..-1].scan(/.{1,8}/).collect { |char| char.to_i(2).chr }.join)
+        val = (val.to_s == 'b00000000' ? '' : val.to_s[1..-1].scan(/.{1,8}/).select { |char| char != '00000000' }.collect { |char| char.to_i(2).chr }.join)
       end
       val
     end
@@ -1179,7 +1216,7 @@ module OrigenSim
     end
 
     def marker=(val)
-      poke("#{testbench_top}.debug.marker", val)
+      poke("#{testbench_top}.#{debug_path}.marker", val)
     end
 
     def start_read_reg_transaction
@@ -1216,14 +1253,73 @@ module OrigenSim
       end
     end
 
+    # Returns true if the snapshot has been compiled with some kind of REAL support.
+    # Not picky about what type of real support though.
+    def real?
+      @real ||= begin
+        if dut_version > '0.19.0' && dut_version < '0.20.3'
+          # These versions of OrigenSim only support WREAL
+          if wreal?
+            @real_type = :wreal
+            true
+          else
+            false
+          end
+        elsif dut_version >= '0.20.3'
+          # These versions support multiple REAL types.
+          if peek_str("#{testbench_top}.#{debug_path}.real_type").nil?
+            @real_type = false
+          else
+            @real_type = peek_str("#{testbench_top}.#{debug_path}.real_type").to_sym
+            peek("#{testbench_top}.#{debug_path}.real_enabled").to_i == 1
+          end
+        else
+          # Older version don't support REAL at all
+          @real_type = false
+          false
+        end
+      end
+    end
+    alias_method :real_enabled?, :real?
+
+    # Returns the type of REAL support or <code>false</code> if no REAL support is enabled.
+    # @note Calling {#real?} will set the value of <code>real_type</code> appropriately
+    def real_type
+      @real_type || begin
+        real?
+        @real_type
+      end
+    end
+
     # Returns true if the snapshot has been compiled with WREAL support
     def wreal?
-      return @wreal if defined?(@wreal)
-      @wreal = (dut_version > '0.19.0' &&
-                peek("#{testbench_top}.debug.wreal_enabled").to_i == 1)
+      if dut_version > '0.19.0' && dut_version < '0.20.3'
+        @wreal ||= peek("#{testbench_top}.#{debug_path}.wreal_enabled").to_i == 1
+      elsif dut_version >= '0.20.3'
+        puts 'wreal?'.cyan
+        puts @real_type.class
+        puts @real_type[0]
+        puts @real_type.to_s.size
+        puts 'wreal'.size
+        puts @real_type.to_s == 'wreal'
+        (@real_type || begin
+          real?
+          @real_type
+        end) == :wreal
+      else
+        false
+      end
     end
     alias_method :wreal_enabled?, :wreal?
 
+    def wrealavg?
+      (@real_type || begin
+        real?
+        @real_type
+      end) == :wrealavg
+    end
+    alias_method :wrealavg_enabled?, :wrealavg?
+
     private
 
     # Will be called when the simulator has aborted due to the max error count being exceeded

data/lib/origen_sim/tester.rb

@@ -81,11 +81,15 @@ module OrigenSim
       simulator.flush(*args)
     end
 
-    def set_timeset(name, period_in_ns)
+    def set_timeset(name, period_in_ns = nil)
       super
+
       # Need to remove this once OrigenTesters does it
-      dut.timeset = name
-      dut.current_timeset_period = period_in_ns
+      # OrigenTesters with decompiler supports this.
+      if period_in_ns
+        dut.timeset = name
+        dut.current_timeset_period = period_in_ns
+      end
 
       # Now update the simulator with the new waves
       simulator.on_timeset_changed

data/lib/origen_sim.rb

@@ -64,6 +64,15 @@ module OrigenSim
     'disconnected'   => -2
   }
 
+  FORCE_PIN_TYPES_MAPPING = {
+    'real'    => :analog,
+    'ana'     => :analog,
+    'analog'  => :analog,
+
+    'dig'     => :digital,
+    'digital' => :digital
+  }
+
   def self.__instantiate_simulator__
     @simulator ||= Simulator.new
   end
@@ -216,6 +225,10 @@ module OrigenSim
     Origen.load_application
     Origen.app.load_target!
 
+    unless tester.simulator?
+      Origen.app!.fail!(message: 'OrigenSim.run cannot be used when the simulator is not the current tester!')
+    end
+
     # Start up the simulator and run whatever's in the target block.
     # After the block completes, shutdown the simulator
     tester.simulator.setup_simulation(name)

data/pattern/test.rb

@@ -127,7 +127,7 @@ Pattern.create do
       peek("dut.real_val", 1.25)
     end
 
-    if tester.simulator.wreal?
+    if tester.simulator.wreal? || tester.simulator.wrealavg?
       ss "Test analog pin API by ramping dut.vdd"
       v = 0
       dut.power_pin(:vdd).drive!(v)

data/templates/probe.tcl.erb

@@ -1,6 +1,5 @@
 database -open waves -into <%= options[:dir] %>/<%= options[:wave_file] %> -default -event
-probe -create -shm <%= options[:testbench_top] || 'origen' %> -depth <%= options[:depth] %> -database waves
-#probe -create -assertions -transaction  <%= options[:testbench_top] || 'origen' %> -depth all -database waves
+<%= options[:probe_cmd] %>
 % Array(options[:tcl_inputs]).each do |line|
 <%= line %>
 % end

data/templates/rtl_v/origen.v.erb

@@ -1,4 +1,53 @@
-%#`include "<%= options[:top] %>"
+// This is an auto-generated file from OrigenSim
+//   (https://origen-sdk.org/origen/guides/simulation/introduction/)
+// This file was generated with this command:
+//   <%= options[:build_cmd] %>
+
+% pins_by_type = [[nil]]
+% type = nil
+% dut.rtl_pins.each do |n, p|
+%  if p.type == type
+%    pins_by_type.last << p
+%  else
+%    pins_by_type << [p.type, p]
+%    type = p.type
+%  end
+% end
+
+// Utility Macros
+// Cast define value as a string.
+`define ORIGEN_SIM_TO_S(s) `"s`"
+
+// Indicate the target vendor
+% if options[:vendor] == :cadence
+`define ORIGEN_SIM_CADENCE
+% elsif options[:vendor] == :synopsis
+`define ORIGEN_SIM_SYNOPSIS
+% elsif options[:vendor] == :icarus
+`define ORIGEN_SIM_ICARUS
+% end
+
+// Indicate the file type, without resorting to System Verilog or vendor-specific functions
+% if options[:file_type] == :sv
+`define ORIGEN_SV_FILE
+% elsif options[:file_type] == :vams
+`define ORIGEN_VAMS_FILE
+% else
+`define ORIGEN_V_FILE
+% end
+
+`ifdef ORIGEN_WREAL
+  `define ORIGEN_USE_REAL
+  `define ORIGEN_REAL_TYPE wreal
+`elsif ORIGEN_WREALAVG
+  `define ORIGEN_USE_REAL
+  `define ORIGEN_REAL_TYPE wrealavg
+  `ifdef ORIGEN_SIM_CADENCE
+    import cds_rnm_pkg::*;
+  `elsif ORIGEN_SIM_SYNOPSIS
+    import snps_msv_nettype_pkg::*;
+  `endif
+`endif
 
 // To create the big fonts - http://patorjk.com/software/taag/#p=display&f=Big
 
@@ -103,7 +152,7 @@ module pin_driver(pin, sync);
 endmodule
 
 
-`ifdef ORIGEN_WREAL 
+`ifdef ORIGEN_USE_REAL
 //                       _               _____ _         _____       _                
 //     /\               | |             |  __ (_)       |  __ \     (_)               
 //    /  \   _ __   __ _| | ___   __ _  | |__) | _ __   | |  | |_ __ ___   _____ _ __ 
@@ -113,13 +162,13 @@ endmodule
 //                                __/ |                                               
 //                               |___/                                                
 
-// A simple WREAL pin driver that can drive real value on a pin or else hi-Z, when the driver is in
+// A simple WREAL/WREALAVG pin driver that can drive real value on a pin or else hi-Z, when the driver is in
 // hi-Z mode the value applied by any other driver connected to the pin can be measured by peeking
 // the value on pin
 module ana_pin_driver(pin);
   inout pin;
 
-  wreal pin;
+  `ORIGEN_REAL_TYPE pin;
 
   reg drive_en = 0;
   real drive = 0.0;      // Value that will be driven on pin when drive is enabled
@@ -140,36 +189,52 @@ endmodule
 // drivers are therefore accessible via origen.pins.my_pin_name
 module pin_drivers(<%= dut.rtl_pins.map { |n, p, o| "#{p.id}_o" }.join(', ') %>);
 
-% dut.rtl_pins.each do |name, pin, options|
-%   if pin.type == :analog
-`ifdef ORIGEN_WREAL 
+% pins_by_type.each do |group|
+%   if group.first == :analog
+`ifdef ORIGEN_USE_REAL
+%     group[1..-1].each do |pin|
   inout <%= pin.id %>_o;
+%     end
 `else
+%     group[1..-1].each do |pin|
   output <%= pin.id %>_o;
+%     end
 `endif
 %   else
+%     group[1..-1].each do |pin|
   output <%= pin.id %>_o;
+%     end
 %   end
 % end
 
-`ifdef ORIGEN_WREAL 
+`ifdef ORIGEN_USE_REAL 
 % dut.rtl_pins(type: :analog).each do |name, pin, options|
-  wreal <%= pin.id %>_o;
+  `ORIGEN_REAL_TYPE <%= pin.id %>_o;
 % end
 `endif
 
   reg sync = 0;
 
-% dut.rtl_pins.each do |name, pin, options|
-%   unless pin.meta[:origen_sim_init_pin_state] == -2
-%     if pin.type == :analog
-`ifdef ORIGEN_WREAL 
+% pins_by_type.each do |group|
+%   if group.first == :analog
+`ifdef ORIGEN_USE_REAL
+%     group[1..-1].each do |pin|
+%       unless pin.meta[:origen_sim_init_pin_state] == -2
   ana_pin_driver <%= pin.id %>(.pin(<%= pin.id %>_o));
+%       end
+%     end
 `else
+%     group[1..-1].each do |pin|
+%       unless pin.meta[:origen_sim_init_pin_state] == -2
   pin_driver #(<%= pin.meta[:origen_sim_init_pin_state].nil? ? '' : ".init_drive(#{pin.meta[:origen_sim_init_pin_state]}), "%>.pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .sync(sync));
+%       end
+%     end
 `endif
-%     else
+%   else
+%     group[1..-1].each do |pin|
+%       unless pin.meta[:origen_sim_init_pin_state] == -2
   pin_driver #(<%= pin.meta[:origen_sim_init_pin_state].nil? ? '' : ".init_drive(#{pin.meta[:origen_sim_init_pin_state]}), "%>.pin_name("<%= pin.id %>")) <%= pin.id %>(.pin(<%= pin.id %>_o), .sync(sync));
+%       end
 %     end
 %   end
 % end
@@ -224,7 +289,7 @@ endmodule
 
 // Instantiated as origen.debug, this module contains the error count, current pattern name and comments,
 // metadata associated with the snapshot build, and other debug information
-module debug;
+module <%= options[:debug_module_name] %>;
   reg [31:0] errors = 0;
   reg [15:0] marker = 0;
   reg [31:0] match_errors = 0;
@@ -238,10 +303,16 @@ module debug;
 
   snapshot_details snapshot_details();
 
-`ifdef ORIGEN_WREAL 
-  reg wreal_enabled = 1;
+`ifdef ORIGEN_USE_REAL 
+  reg real_enabled = 1;
+`ifdef ORIGEN_SV_FILE
+  reg [1023:0] real_type = `ORIGEN_SIM_TO_S(`ORIGEN_REAL_TYPE`);
+`else
+  reg [1023:0] real_type = "wreal";
+`endif
 `else
-  reg wreal_enabled = 0;
+  reg real_enabled = 0;
+  reg [1023:0] real_type = 0;
 `endif
   
 endmodule
@@ -255,19 +326,25 @@ endmodule
 //            | |                                                 
 //            |_|                                                 
 
-module <%= options[:testbench_name] || 'origen' %>;
+module <%= options[:testbench] %>;
 
-  reg finish = 0;
+  reg <%= options[:finish_signal] %> = 0;
 
-% dut.rtl_pins.each do |name, pin, options|
-%   if pin.type == :analog
-`ifdef ORIGEN_WREAL 
-  wreal <%= pin.id %>;
+% pins_by_type.each do |group|
+%   if group.first == :analog
+`ifdef ORIGEN_USE_REAL
+%     group[1..-1].each do |pin|
+  `ORIGEN_REAL_TYPE <%= pin.id %>;
+%     end
 `else
+%     group[1..-1].each do |pin|
   wire <%= pin.id %>;
+%     end
 `endif
 %   else
+%     group[1..-1].each do |pin|
   wire <%= pin.id %>;
+%     end
 %   end
 % end
 
@@ -278,13 +355,7 @@ module <%= options[:testbench_name] || 'origen' %>;
   );
 
   // Instantiate the DUT
-  <%= options[:top].sub(/\..*/, '') %> dut (
-% dut.power_pins.each do |name, pin, options|
-    .<%= pin.id %>(<%= pin.id %>),
-% end
-% dut.ground_pins.each do |name, pin, options|
-    .<%= pin.id %>(<%= pin.id %>),
-% end
+  <%= options[:top].sub(/\..*/, '') %> <%= options[:top_level_name] %> (
 % # Keep track of the primary groups seen.
 % seen_groups = []
 % dut.rtl_pins.each_with_index do |(name, pin, options), i|
@@ -303,7 +374,7 @@ module <%= options[:testbench_name] || 'origen' %>;
 % end
   );
 
-  debug debug ();
+  <%= options[:debug_module_name] %> <%= options[:debug_module_name] %> ();
 
   initial
   begin
@@ -319,12 +390,11 @@ module <%= options[:testbench_name] || 'origen' %>;
     $vcdplusmemon;
 `endif
 `ifdef ORIGEN_FSDB
-    $fsdbDumpfile("origen.fsdb");
     $fsdbDumpvars(0, "+all");
 `endif
   end
 
-  always @(posedge finish) begin
+  always @(posedge <%= options[:finish_signal] %>) begin
     $finish(2);
   end
 

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.20.7
+  version: 0.21.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-01-28 00:00:00.000000000 Z
+date: 2025-02-22 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -44,14 +44,14 @@ dependencies:
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.6.2
+        version: 0.6.3
   type: :runtime
   prerelease: false
   version_requirements: !ruby/object:Gem::Requirement
     requirements:
     - - ">="
       - !ruby/object:Gem::Version
-        version: 0.6.2
+        version: 0.6.3
 description: 
 email:
 - stephen.f.mcginty@gmail.com
@@ -147,8 +147,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: 1.8.11
 requirements: []
-rubyforge_project: 
-rubygems_version: 2.7.7
+rubygems_version: 3.1.6
 signing_key: 
 specification_version: 4
 summary: Plugin that provides a testbench environment to simulate Origen test patterns