origen_sim 0.20.6 → 0.20.7

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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-  data.tar.gz: a76d417628ad05a2a8da4d6ad4a2c7d0f97e9f275c9fe8aaa8c3ec21fa2a3e57
+  metadata.gz: 4035df7e280d12364f716ead8d7a913c4d6ff4528319abc8864b3ef1d73126b2
+  data.tar.gz: 2e2fe5684ea80e5cad1816844274256879b0c73a502fa3394064634a43771488
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+  data.tar.gz: 9ffeb116e814958ab5ed504b8033321ae75054728e2afcc636ec51c299826d5b5bfe7e111ba1410c744b794ae62f9391346ee8ec5ac6de832be4078f3208cb7b

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenSim
   MAJOR = 0
   MINOR = 20
-  BUGFIX = 6
+  BUGFIX = 7
   DEV = nil
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/ext/bridge.c

@@ -29,6 +29,7 @@ typedef struct Pin {
   int compare_wave_pos;  // Position of the pin in the compare_wave's active pin array
   int index;             // The pin's index in the pins array
   int previous_state;    // Used to keep track of whether the pin was previously driving or comparing
+  int drive_data;        // Used to hold the new drive data for this pin until needed by the drive wave
   bool capture_en;       // Used to indicated when compare data should be captured instead of compared
   bool present;          // Set to true if the pin is present in the testbench
 } Pin;
@@ -108,6 +109,7 @@ static void define_pin(char * name, char * pin_ix, char * drive_wave_ix, char *
   (*pin).compare_wave = atoi(compare_wave_ix);
   (*pin).previous_state = 0;
   (*pin).capture_en = false;
+  (*pin).drive_data = 0;
 
 
   char * driver = (char *) malloc(strlen(name) + 16);
@@ -326,9 +328,15 @@ static void drive_pin(char * index, char * val) {
   s_vpi_value v = {vpiIntVal, {0}};
 
   if ((*pin).present) {
+    // Store the pin drive data to be applied at the data edge
+    (*pin).drive_data = (val[0] - '0');
+    
     // Apply the data value to the pin's driver
-    v.value.integer = (val[0] - '0');
-    vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
+    if (is_drive_whole_cycle(pin)) {
+      v.value.integer = (*pin).drive_data;
+      vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
+    }
+    
     // Make sure not comparing
     v.value.integer = 0;
     vpi_put_value((*pin).compare, &v, NULL, vpiNoDelay);
@@ -431,6 +439,7 @@ static void dont_care_pin(char * index) {
 PLI_INT32 apply_wave_event_cb(p_cb_data data) {
   s_vpi_value v = {vpiIntVal, {0}};
   s_vpi_value v2 = {vpiIntVal, {0}};
+  s_vpi_value v3 = {vpiIntVal, {0}};
 
   int * wave_ix  = (int*)(&(data->user_data[0]));
   int * event_ix = (int*)(&(data->user_data[sizeof(int)]));
@@ -486,6 +495,11 @@ PLI_INT32 apply_wave_event_cb(p_cb_data data) {
       case 'D' :
         d = 0;
         on = 1;
+        // Apply the data value to the pin's driver
+	for (int i = 0; i < (*wave).active_pin_count; i++) {
+          v3.value.integer = (*(*wave).active_pins[i]).drive_data;
+          vpi_put_value((*(*wave).active_pins[i]).data, &v3, NULL, vpiNoDelay);
+	}
         break;
       case 'X' :
         d = 0;

data/lib/origen_sim/commands/build.rb

@@ -140,6 +140,7 @@ else
                            options:           {
                              vendor:            :cadence,
                              top:               dut.name,
+                             testbench_name:    options[:testbench_name],
                              incl:              options[:incl_files],
                              device_name:       options[:device_name],
                              revision:          options[:revision],

data/lib/origen_sim/simulator.rb

@@ -328,7 +328,13 @@ module OrigenSim
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir: wave_dir, wave_file: wave_file_basename, force: config[:force], setup: config[:setup], depth: :all },
+                                   options:           { dir:           wave_dir,
+                                                        wave_file:     wave_file_basename,
+                                                        force:         config[:force],
+                                                        setup:         config[:setup],
+                                                        depth:         :all,
+                                                        testbench_top: config[:testbench_top] || 'origen'
+                                                      },
                                    output_file_name:  "#{wave_file_basename}.tcl",
                                    preserve_target:   true
         end
@@ -340,7 +346,13 @@ module OrigenSim
                                    output:            tmp_dir,
                                    check_for_changes: false,
                                    quiet:             true,
-                                   options:           { dir: wave_dir, wave_file: wave_file_basename, force: config[:force], setup: config[:setup], depth: fast_probe_depth },
+                                   options:           { dir:           wave_dir,
+                                                        wave_file:     wave_file_basename,
+                                                        force:         config[:force],
+                                                        setup:         config[:setup],
+                                                        depth:         fast_probe_depth,
+                                                        testbench_top: config[:testbench_top] || 'origen'
+                                                      },
                                    output_file_name:  "#{wave_file_basename}_fast.tcl",
                                    preserve_target:   true
         end

data/lib/origen_sim/tester.rb

@@ -41,9 +41,25 @@ module OrigenSim
       end
       @sync_pins.map do |pin|
         if @sync_cycles.size == 1
-          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")[0]
+          b = simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")[0]
+          if b.is_a?(Integer)
+            b
+          else
+            Origen.log.warning "The data captured on pin #{pin.id} was undefined (X or Z), the captured value is not correct!"
+            0
+          end
         else
-          simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory").to_i[(@sync_cycles - 1)..0]
+          val = 0
+          mem = simulator.peek("#{simulator.testbench_top}.pins.#{pin.id}.sync_memory")
+          @sync_cycles.times do |i|
+            b = mem[i]
+            if b.is_a?(Integer)
+              val |= b << i
+            else
+              Origen.log.warning "The data captured on cycle #{i} of pin #{pin.id} was undefined (X or Z), the captured value is not correct!"
+            end
+          end
+          val
         end
       end
     end
@@ -166,25 +182,21 @@ module OrigenSim
       if options[:pin2]
         expected_val2 = options[:state2] == :high ? 1 : 0
       end
-      timed_out = true
-      10.times do
-        (timeout_in_cycles / 10).cycles
+      matched = false
+      start_cycle = cycle_count
+      resolution = match_loop_resolution(timeout_in_cycles, options)
+      until matched || cycle_count > start_cycle + timeout_in_cycles
+        resolution.cycles
         current_val = simulator.peek("dut.#{pin.rtl_name}").to_i
         if options[:pin2]
           current_val2 = simulator.peek("dut.#{options[:pin2].rtl_name}").to_i
-          if current_val == expected_val || current_val2 == expected_val2
-            timed_out = false
-            break
-          end
+          matched = current_val == expected_val || current_val2 == expected_val2
         else
-          if current_val == expected_val
-            timed_out = false
-            break
-          end
+          matched = current_val == expected_val
         end
       end
       # Final assertion to make the pattern fail if the loop timed out
-      if timed_out
+      unless matched
         pin.restore_state do
           pin.assert!(expected_val)
         end
@@ -207,23 +219,22 @@ module OrigenSim
       else
         match_conditions.add(&block)
       end
-      timed_out = true
+      matched = false
+      start_cycle = cycle_count
+      resolution = match_loop_resolution(timeout_in_cycles, options)
       simulator.match_loop do
-        10.times do
-          (timeout_in_cycles / 10).cycles
+        until matched || cycle_count > start_cycle + timeout_in_cycles
+          resolution.cycles
           # Consider the match resolved if any condition can execute without generating errors
-          if match_conditions.any? do |condition|
+          matched = match_conditions.any? do |condition|
             e = simulator.match_errors
             condition.call
             e == simulator.match_errors
           end
-            timed_out = false
-            break
-          end
         end
       end
       # Final execution to make the pattern fail if the loop timed out
-      if timed_out
+      unless matched
         if fail_conditions.instance_variable_get(:@block_args).empty?
           match_conditions.each(&:call)
         else
@@ -232,6 +243,27 @@ module OrigenSim
       end
     end
 
+    # @api private
+    def match_loop_resolution(timeout_in_cycles, options)
+      if options[:resolution]
+        if options[:resolution].is_a?(Hash)
+          return time_to_cycles(options[:resolution])
+        else
+          return options[:resolution]
+        end
+      else
+        # Used to use the supplied timeout / 10, thinking that the supplied number would be
+        # roughly how long it would take. However, found that when users didn't know the timeout
+        # they would just put in really large numbers, like 1sec, which would mean we would not
+        # check until 100ms for an operation that might be done after 100us.
+        # So now if the old default comes out less than the new one, then use it, otherwise use
+        # the newer more fine-grained default.
+        old_default = timeout_in_cycles / 10
+        new_default = time_to_cycles(time_in_us: 100)
+        return old_default < new_default ? old_default : new_default
+      end
+    end
+
     def wait(*args)
       super
       if Origen.running_interactively? ||

data/lib/origen_sim_dev/dut.rb

@@ -35,6 +35,10 @@ module OrigenSimDev
           w.drive 0, at: 0
           w.drive :data, at: 'period / 2'
         end
+        # Generate drive timing that has only a data event which isn't at t0
+        t.wave :din_port do |w|
+          w.drive :data, at: 'period / 2'
+        end
       end
 
       add_reg :dr, 0x0, size: 66 do |reg|

data/pattern/test.rb

@@ -218,6 +218,13 @@ Pattern.create do
     60.cycles
   end
 
+  ss "Test timing implementation - drive timing, single data event only, not at t0"
+  dut.pins(:din_port).dont_care
+  tester.cycle
+  dut.pins(:din_port).drive! 1
+  dut.pins(:din_port).drive! 0
+  dut.pins(:din_port).drive! 1
+
   ss "Test the command works with static vectors"
   dut.pin(:done).assert!(1)
   dut.pin(:done).dont_care
@@ -262,7 +269,7 @@ Pattern.create do
   5.cycles
   dut.pin(:done).assert!(0)
   dut.pin(:done).dont_care
-  tester.wait match: true, time_in_cycles: 2000 do
+  tester.wait match: true, time_in_s: 2 do
     dut.pin(:done).assert!(1)
   end
   dut.pin(:done).assert!(1)

data/templates/origen_guides/simulation/patterns.md.erb

@@ -28,6 +28,14 @@ normally have two options:
 Both of these are fully supported by OrigenSim, see the
 [Timing and Waiting guide](<%= path "guides/pattern/timing" %>) for more information on these APIs.
 
+<div class="alert alert-info" role="alert"> <strong>A Note on Match Loops</strong>
+  <br>
+  When waiting for a match, the DUT will be polled every 100us by default or timeout / 10 if that
+  is less than 100us.
+  If you need it to poll more often (at the expense of simulation speed) then a `:resolution` option can
+  be supplied in the same way as described for the `sim_delay` method below.
+</div>
+
 However, if your pattern generation flow is going to be supported by simulation, then you also have
 a third option - to derive the required wait time from the simulation itself.
 

data/templates/probe.tcl.erb

@@ -1,6 +1,6 @@
 database -open waves -into <%= options[:dir] %>/<%= options[:wave_file] %> -default -event
-probe -create -shm origen -depth <%= options[:depth] %> -database waves
-#probe -create -assertions -transaction origen -depth all -database waves
+probe -create -shm <%= options[:testbench_top] || 'origen' %> -depth <%= options[:depth] %> -database waves
+#probe -create -assertions -transaction  <%= options[:testbench_top] || 'origen' %> -depth all -database waves
 % Array(options[:tcl_inputs]).each do |line|
 <%= line %>
 % end

data/templates/rtl_v/origen.v.erb

@@ -255,7 +255,7 @@ endmodule
 //            | |                                                 
 //            |_|                                                 
 
-module origen;
+module <%= options[:testbench_name] || 'origen' %>;
 
   reg finish = 0;
 

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.20.6
+  version: 0.20.7
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-08-02 00:00:00.000000000 Z
+date: 2020-01-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen