origen_sim 0.20.2 → 0.20.3

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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-  data.tar.gz: 7ef47fe8101f15e47314964d18f0f8634b8dfc6b902738ace2ccf5bc16bc19cd
+  metadata.gz: 4ab4654d80fd9cc6c3e3cd279e7a633dc2196c0f94af8de97d3b99f33139be71
+  data.tar.gz: 1fa51c18499e461e3b981d4c357959ef217436a0be96b4942e6858c9fd694ce2
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+  data.tar.gz: dbfdc64e64c808ebe6747e1eea50db6014a1fa17fe4c544dbf7a341583cf8490b0272495cbc5ddb2c4b5db5be451c5832a0a2b646af45115c49af397bd904e3a

data/config/version.rb

@@ -1,8 +1,7 @@
 module OrigenSim
   MAJOR = 0
   MINOR = 20
-  BUGFIX = 2
+  BUGFIX = 3
   DEV = nil
-
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/lib/origen_sim/tester.rb

@@ -297,7 +297,7 @@ module OrigenSim
                 if c = read_reg_cycles[error[:cycle]]
                   if p = c[simulator.pins_by_rtl_name[error[:pin_name]]]
                     if p[:position]
-                      diffs << [p[:position], error[:received], error[:expected]]
+                      diffs << [p[:position], error[:expected], error[:received]]
                     end
                   end
                 end
@@ -327,11 +327,11 @@ module OrigenSim
                   bit.read if read_flags[i]
                 end
 
-                diffs.each do |position, received, expected|
+                diffs.each do |position, expected, received|
                   if received == -1 || received == -2
                     reg_or_val[position].unknown = true
                   else
-                    reg_or_val[position].data = received
+                    reg_or_val[position].write(received, force: true)
                   end
                 end
 
@@ -344,8 +344,8 @@ module OrigenSim
 
                 # Put the data back so the application behaves as it would if generating
                 # for a non-simulation tester target
-                diffs.each do |position, received, expected|
-                  reg_or_val[position].data = expected
+                diffs.each do |position, expected, received|
+                  reg_or_val[position].write(expected, force: true)
                 end
               end
             end
@@ -376,7 +376,7 @@ module OrigenSim
             msg = "expected #{reg_or_val.to_s(16).upcase}"
             if actual_data_available
               actual = reg_or_val
-              diffs.each do |position, received, expected|
+              diffs.each do |position, expected, received|
                 if received == -1 || received == -2
                   actual = '?' * reg_or_val.to_s(16).size
                   break

data/pattern/fails.rb

@@ -5,6 +5,10 @@ Pattern.create do
   dut.cmd.write!(0x1234_5678)
   dut.cmd.read!(0x1233_5678)
 
+  ss "Test a register-level miscompare with named bits"
+  dut.power_pin(:vdd).drive!(0)
+  dut.ana_test.read!(1)
+
   ss "Test a bit-level miscompare, expect 1"
   dut.ana_test.write!(0)
   dut.ana_test.bgap_out.read!(1)

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.20.2
+  version: 0.20.3
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-05-30 00:00:00.000000000 Z
+date: 2019-05-31 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen