origen_sim 0.11.1 → 0.12.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA1:
-  metadata.gz: 7de67b84a878cf189e64f455cfa1ab4525a5711b
-  data.tar.gz: d091d30647c88bb40cd6fe305e158c6cb823113e
+  metadata.gz: c34ffd12e0b7df9632e5bad4dcb933cb46f88460
+  data.tar.gz: 6690aac5bb4335ac2de29b1757249eba1be026c0
 SHA512:
-  metadata.gz: c0fda1a65fb6108cd8ec8e7020ec24c00770f433e268b2c359da210d04ab2f4e21c385fac925ddc819f6fd6efc1149b455c4d59f622ec86d34f3802ac5761b9c
-  data.tar.gz: e1b129ab59cf25562e596c31fa05ef947833300bb3136d739d025afeb9dda4ea057af0768c66fde9e3911187c4cfaedea0fd21964f14ac68e2ec59de69ab6f00
+  metadata.gz: 71a090ebaa9f1440d3052773b0823187ada5fc10aab7786081b0c8274e079c78b6aab0866d85c90e7f6193c5a243d3c98012cf99e9d13b7078a4924510e3dda2
+  data.tar.gz: a617b1e824ef7b9c36583df618440115f35aac94462b1d9a9601f917444360729d81a26235d72bc5dd2aa91f90e398d1d240233feec2ec0d07e568ae38219d47

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenSim
   MAJOR = 0
-  MINOR = 11
-  BUGFIX = 1
+  MINOR = 12
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/ext/bridge.c

@@ -12,9 +12,10 @@
 #include <string.h>
 
 #define MAX_NUMBER_PINS 2000
-#define MAX_WAVE_EVENTS 10
+#define MAX_WAVE_EVENTS 50
 
 typedef struct Pin {
+  char *name;
   vpiHandle data;        // A handle to the driver data register
   vpiHandle drive;       // A handle to the driver drive enable register
   vpiHandle force_data;  // A handle to the driver force_data register
@@ -27,6 +28,7 @@ typedef struct Pin {
   int index;             // The pin's index in the pins array
   int previous_state;    // Used to keep track of whether the pin was previously driving or comparing
   bool capture_en;       // Used to indicated when compare data should be captured instead of compared
+  bool present;          // Set to true if the pin is present in the testbench
 } Pin;
 
 typedef struct Event {
@@ -76,12 +78,15 @@ static void bridge_define_pin(char * name, char * pin_ix, char * drive_wave_ix,
   Pin *pin = &pins[index];
   number_of_pins += 1;
 
+  (*pin).name = malloc(strlen(name) + 1);
+  strcpy((*pin).name, name);
   (*pin).index = index;
   (*pin).drive_wave = atoi(drive_wave_ix);
   (*pin).compare_wave = atoi(compare_wave_ix);
   (*pin).previous_state = 0;
   (*pin).capture_en = false;
 
+
   char * driver = (char *) malloc(strlen(name) + 16);
   strcpy(driver, ORIGEN_SIM_TESTBENCH_CAT("pins."));
   strcat(driver, name);
@@ -92,6 +97,13 @@ static void bridge_define_pin(char * name, char * pin_ix, char * drive_wave_ix,
   (*pin).data = vpi_handle_by_name(data, NULL);
   free(data);
 
+  if (!(*pin).data) {
+    vpi_printf("WARNING: Your DUT defines pin '%s', however it is not present in the testbench and will be ignored\n", (*pin).name);
+    (*pin).present = false;
+  } else {
+    (*pin).present = true;
+  }
+
   char * drive = (char *) malloc(strlen(driver) + 16);
   strcpy(drive, driver);
   strcat(drive, ".drive");
@@ -254,6 +266,10 @@ static void bridge_disable_compare_wave(Pin * pin) {
 
 
 static void bridge_clear_waves_and_pins() {
+  for (int i = 0; i < number_of_pins; i++) {
+    Pin *pin = &pins[i];
+    free((*pin).name);
+  }
   number_of_pins = 0;
   number_of_drive_waves = 0;
   number_of_compare_waves = 0;
@@ -286,30 +302,32 @@ static void bridge_drive_pin(char * index, char * val) {
   Pin *pin = &pins[atoi(index)];
   s_vpi_value v = {vpiIntVal, {0}};
 
-  // Apply the data value to the pin's driver
-  v.value.integer = (val[0] - '0');
-  vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
-  // Make sure not comparing
-  v.value.integer = 0;
-  vpi_put_value((*pin).compare, &v, NULL, vpiNoDelay);
-
-  // Register it as actively driving with it's wave
-  
-  // If it is already driving the wave will already be setup
-  if ((*pin).previous_state != 1) {
-    // If the drive is for the whole cycle, then we can enable it here
-    // and don't need a callback
-    if (bridge_is_drive_whole_cycle(pin)) {
-      v.value.integer = 1;
-      vpi_put_value((*pin).drive, &v, NULL, vpiNoDelay);
-    } else {
-      bridge_enable_drive_wave(pin);
-    }
+  if ((*pin).present) {
+    // Apply the data value to the pin's driver
+    v.value.integer = (val[0] - '0');
+    vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
+    // Make sure not comparing
+    v.value.integer = 0;
+    vpi_put_value((*pin).compare, &v, NULL, vpiNoDelay);
+
+    // Register it as actively driving with it's wave
+    
+    // If it is already driving the wave will already be setup
+    if ((*pin).previous_state != 1) {
+      // If the drive is for the whole cycle, then we can enable it here
+      // and don't need a callback
+      if (bridge_is_drive_whole_cycle(pin)) {
+        v.value.integer = 1;
+        vpi_put_value((*pin).drive, &v, NULL, vpiNoDelay);
+      } else {
+        bridge_enable_drive_wave(pin);
+      }
 
-    if ((*pin).previous_state == 2) {
-      bridge_disable_compare_wave(pin);
+      if ((*pin).previous_state == 2) {
+        bridge_disable_compare_wave(pin);
+      }
+      (*pin).previous_state = 1;
     }
-    (*pin).previous_state = 1;
   }
 }
 
@@ -319,23 +337,25 @@ static void bridge_compare_pin(char * index, char * val) {
   Pin *pin = &pins[atoi(index)];
   s_vpi_value v = {vpiIntVal, {0}};
 
-  // Apply the data value to the pin's driver, don't enable compare yet,
-  // the wave will do that later
-  v.value.integer = (val[0] - '0');
-  vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
-  // Make sure not driving
-  v.value.integer = 0;
-  vpi_put_value((*pin).drive, &v, NULL, vpiNoDelay);
-
-  // Register it as actively comparing with it's wave
-  
-  // If it is already comparing the wave will already be setup
-  if ((*pin).previous_state != 2) {
-    bridge_enable_compare_wave(pin);
-    if ((*pin).previous_state == 1) {
-      bridge_disable_drive_wave(pin);
+  if ((*pin).present) {
+    // Apply the data value to the pin's driver, don't enable compare yet,
+    // the wave will do that later
+    v.value.integer = (val[0] - '0');
+    vpi_put_value((*pin).data, &v, NULL, vpiNoDelay);
+    // Make sure not driving
+    v.value.integer = 0;
+    vpi_put_value((*pin).drive, &v, NULL, vpiNoDelay);
+
+    // Register it as actively comparing with it's wave
+    
+    // If it is already comparing the wave will already be setup
+    if ((*pin).previous_state != 2) {
+      bridge_enable_compare_wave(pin);
+      if ((*pin).previous_state == 1) {
+        bridge_disable_drive_wave(pin);
+      }
+      (*pin).previous_state = 2;
     }
-    (*pin).previous_state = 2;
   }
 }
 
@@ -361,21 +381,23 @@ static void bridge_dont_care_pin(char * index) {
   Pin *pin = &pins[atoi(index)];
   s_vpi_value v = {vpiIntVal, {0}};
 
-  // Disable drive and compare on the pin's driver
-  v.value.integer = 0;
-  vpi_put_value((*pin).drive, &v, NULL, vpiNoDelay);
-  vpi_put_value((*pin).compare, &v, NULL, vpiNoDelay);
+  if ((*pin).present) {
+    // Disable drive and compare on the pin's driver
+    v.value.integer = 0;
+    vpi_put_value((*pin).drive, &v, NULL, vpiNoDelay);
+    vpi_put_value((*pin).compare, &v, NULL, vpiNoDelay);
 
-  if ((*pin).previous_state != 0) {
-    if ((*pin).previous_state == 1) {
-      if (!bridge_is_drive_whole_cycle(pin)) {
-        bridge_disable_drive_wave(pin);
+    if ((*pin).previous_state != 0) {
+      if ((*pin).previous_state == 1) {
+        if (!bridge_is_drive_whole_cycle(pin)) {
+          bridge_disable_drive_wave(pin);
+        }
       }
+      if ((*pin).previous_state == 2) {
+        bridge_disable_compare_wave(pin);
+      }
+      (*pin).previous_state = 0;
     }
-    if ((*pin).previous_state == 2) {
-      bridge_disable_compare_wave(pin);
-    }
-    (*pin).previous_state = 0;
   }
 }
 

data/lib/origen_sim.rb

@@ -91,6 +91,28 @@ module OrigenSim
     @stderr_string_exceptions = val
   end
 
+  def self.warning_strings
+    @warning_strings ||= ['WARNING']
+  end
+
+  def self.warning_strings=(val)
+    unless val.is_a?(Array)
+      fail 'OrigenSim.warning_strings can only be set to an array of string values!'
+    end
+    @warning_strings = val
+  end
+
+  def self.warning_string_exceptions
+    @warning_string_exceptions ||= []
+  end
+
+  def self.warning_string_exceptions=(val)
+    unless val.is_a?(Array)
+      fail 'OrigenSim.warning_string_exceptions can only be set to an array of string values!'
+    end
+    @warning_string_exceptions = val
+  end
+
   def self.log_strings
     @log_strings ||= []
   end

data/lib/origen_sim/simulation.rb

@@ -28,10 +28,17 @@ module OrigenSim
       @error_count = 0
       @socket_ids = {}
 
-      @server = UNIXServer.new(socket_id) # Socket used to send Origen -> Verilog commands
+      # Socket used to send Origen -> Verilog commands
+      @server = UNIXServer.new(socket_id)
+
+      # Socket used to capture STDOUT from the simulator
       @server_stdout = UNIXServer.new(socket_id(:stdout))
+      # Socket used to capture STDERR from the simulator
       @server_stderr = UNIXServer.new(socket_id(:stderr))
+      # Socket used to send a heartbeat pulse from Origen to process running the simulator
       @server_heartbeat = UNIXServer.new(socket_id(:heartbeat))
+      # Socket used to receive status updates from the process running the simulator
+      @server_status = UNIXServer.new(socket_id(:status))
     end
 
     def failed?(in_progress = false)
@@ -54,7 +61,11 @@ module OrigenSim
     def log_results(in_progress = false)
       if failed?(in_progress)
         if failed_to_start
-          Origen.log.error 'The simulation failed to start!'
+          if Origen.debugger_enabled?
+            Origen.log.error 'The simulation failed to get underway!'
+          else
+            Origen.log.error 'The simulation failed to get underway! (run again with -d to see why)'
+          end
         else
           if in_progress
             Origen.log.error "The simulation has #{error_count} error#{error_count > 1 ? 's' : ''}!" if error_count > 0
@@ -80,7 +91,6 @@ module OrigenSim
     # heartbeats.
     def start_heartbeat
       @heartbeat = @server_heartbeat.accept
-      @pid = @heartbeat.gets.chomp.to_i
       @heartbeat_thread = Heartbeat.new(@heartbeat)
     end
 
@@ -89,16 +99,66 @@ module OrigenSim
     end
 
     # Open the communication channels with the simulator
-    def open
-      start_heartbeat
-      @stdout = @server_stdout.accept
-      @stderr = @server_stderr.accept
-      @socket = @server.accept
-      @stdout_reader = StdoutReader.new(@stdout)
-      @stderr_reader = StderrReader.new(@stderr)
+    def open(timeout)
+      timeout_connection(timeout) do
+        start_heartbeat
+        @stdout = @server_stdout.accept
+        @stderr = @server_stderr.accept
+        @status = @server_status.accept
+        @stdout_reader = StdoutReader.new(@stdout)
+        @stderr_reader = StderrReader.new(@stderr)
+
+        Origen.log.debug 'The simulation monitor has started'
+        Origen.log.debug @status.gets.chomp  # Starting simulator
+        Origen.log.debug @status.gets.chomp  # Simulator has started
+        response = @status.gets.chomp
+        if response =~ /finished/
+          abort_connection
+        else
+          @pid = response.to_i
+        end
+        # That's all status info done until the simulation process ends, start a thread
+        # to wait for that in case it ends before the VPI starts
+        Thread.new do
+          Origen.log.debug @status.gets.chomp  # This will block until something is received
+          abort_connection
+        end
+        Origen.log.debug 'Waiting for Origen VPI to start...'
+
+        # This will block until the VPI extension is invoked and connects to the socket
+        @socket = @server.accept
+
+        @connection_established = true # Cancels timeout_connection
+        if @connection_aborted
+          self.failed_to_start = true
+          log_results
+          exit  # Assume it is not worth trying another pattern in this case, some kind of environment/config issue
+        end
+        Origen.log.debug 'Origen VPI has started'
+      end
+
       @opened = true
     end
 
+    def timeout_connection(wait_in_s)
+      @connection_aborted = false
+      @connection_established = false
+      Thread.new do
+        sleep wait_in_s
+        abort_connection # Will do nothing if a successful connection has been made while we were waiting
+      end
+      yield
+    end
+
+    def abort_connection
+      # If the Verilog process has not established a connection yet, then make one to
+      # release our process and then exit
+      unless @connection_established
+        @connection_aborted = true
+        UNIXSocket.new(socket_id).puts("Time out\n")
+      end
+    end
+
     # Close all communication channels with the simulator
     def close
       return unless @opened

data/lib/origen_sim/simulator.rb

@@ -352,6 +352,7 @@ module OrigenSim
 
     # Starts up the simulator process
     def start
+      Origen.log.level = :verbose if Origen.debugger_enabled?
       @simulation_open = true
       @simulation = Simulation.new(wave_file_basename, view_wave_command)
       simulations << @simulation
@@ -378,16 +379,20 @@ module OrigenSim
           exit!
         end
 
+        status = UNIXSocket.new('#{simulation.socket_id(:status)}')
         stdout_socket = UNIXSocket.new('#{simulation.socket_id(:stdout)}')
         stderr_socket = UNIXSocket.new('#{simulation.socket_id(:stderr)}')
         heartbeat = UNIXSocket.new('#{simulation.socket_id(:heartbeat)}')
 
         begin
 
+          status.puts('Starting the simulator...')
+
           Dir.chdir '#{run_dir}' do
             Open3.popen3('#{cmd}') do |stdin, stdout, stderr, thread|
+              status.puts('The simulator has started')
               pid = stdout.gets.strip.to_i
-              heartbeat.puts(pid.to_s)
+              status.puts(pid.to_s)
 
               # Listen for a heartbeat from the main Origen process every 5 seconds, kill the
               # simulator after two missed heartbeats
@@ -433,27 +438,26 @@ module OrigenSim
             end
           end
 
+          status.puts 'The simulator has finished'
+
         ensure
           # Make sure this process never finishes and leaves the simulator running
           kill_simulation(pid) if pid
         end
       )
 
+      Origen.log.debug 'Starting the simulation monitor...'
+
       simulator_parent_process = spawn("ruby -e \"#{launch_simulator}\"")
       Process.detach(simulator_parent_process)
 
-      timeout_connection(config[:startup_timeout] || 60) do
-        simulation.open # This will block until the simulation process responds
+      simulation.open(config[:startup_timeout] || 60) # This will block until the simulation process has started
 
-        @connection_established = true # Cancels timeout_connection
-        if @connection_timed_out
-          simulation.failed_to_start = true
-          exit  # Assume it is not worth trying another pattern in this case, some kind of environment/config issue
-        end
-      end
+      # The VPI extension will send 'READY!' when it starts, make sure we get it before proceeding
       data = get
       unless data.strip == 'READY!'
         simulation.failed_to_start = true
+        simulation.log_results
         exit  # Assume it is not worth trying another pattern in this case, some kind of environment/config issue
       end
       # Tick the simulation on, this seems to be required since any VPI puts operations before
@@ -479,6 +483,7 @@ module OrigenSim
     # At the start of a test program flow generation/simulation
     def on_flow_start(options)
       if simulation_tester? && options[:top_level]
+        @flow_running = true
         OrigenSim.flow = Origen.interface.flow.name
         start
         @pattern_count = 0
@@ -488,6 +493,8 @@ module OrigenSim
     # At the end of a test program flow generation/simulation
     def on_flow_end(options)
       if simulation_tester? && options[:top_level]
+        @flow_running = false
+        simulation.completed_cleanly = true
         stop
       end
     end
@@ -501,6 +508,7 @@ module OrigenSim
           # When running patterns back-to-back, only want to launch the simulator the first time
           start unless simulation
         else
+          simulation.completed_cleanly = true
           stop
           start
         end
@@ -511,6 +519,8 @@ module OrigenSim
         # each individual pattern has completed
         if @pattern_count > 0 && OrigenSim.flow
           simulation.log_results(true)
+          # Require each pattern to set this upon successful completion
+          simulation.completed_cleanly = false unless @flow_running
         end
         @pattern_count += 1
       end
@@ -520,7 +530,10 @@ module OrigenSim
     # sure the simulator is not running behind before potentially
     # moving onto another pattern
     def pattern_generated(path)
-      sync_up if simulation_tester?
+      if simulation_tester?
+        sync_up
+        simulation.completed_cleanly = true unless @flow_running
+      end
     end
 
     def write_comment(comment)
@@ -717,26 +730,19 @@ module OrigenSim
       @simulation_open = false
       simulation.error_count = error_count
       Origen.listeners_for(:simulation_shutdown).each(&:simulation_shutdown)
-      ended = Time.now
       end_simulation
       # Give the simulator time to shut down
       sleep 0.1 while simulation.running?
       simulation.close
-      simulation.completed_cleanly = true
       simulation.log_results unless Origen.current_command == 'interactive'
+    rescue
+      simulation.completed_cleanly = false
     end
 
     def on_origen_shutdown
       unless simulations.empty?
         failed = false
-        # Stop the current simulation, this is done with the rescue wrapper so that the rest
-        # of the shutdown continues if we got in here via a CTRL-C, in which case the simulator
-        # is probably already dead
-        begin
-          stop if simulation_open?
-        rescue
-          simulation.completed_cleanly = false
-        end
+        stop if simulation_open?
         unless @interactive_mode
           if simulations.size == 1
             failed = simulation.failed?
@@ -784,21 +790,6 @@ module OrigenSim
       (tester && tester.is_a?(OrigenSim::Tester))
     end
 
-    def timeout_connection(wait_in_s)
-      @connection_timed_out = false
-      @connection_established = false
-      t = Thread.new do
-        sleep wait_in_s
-        # If the Verilog process has not established a connection yet, then make one to
-        # release our process and then exit
-        unless @connection_established
-          @connection_timed_out = true
-          UNIXSocket.new(socket_id).puts("Time out\n")
-        end
-      end
-      yield
-    end
-
     def sync
       put('f')
       @sync_active = true

data/lib/origen_sim/stdout_reader.rb

@@ -16,6 +16,9 @@ module OrigenSim
                !OrigenSim.error_string_exceptions.any? { |s| line =~ /#{s}/ }
               @logged_errors = true
               Origen.log.error "(STDOUT): #{line}"
+            elsif OrigenSim.warning_strings.any? { |s| line =~ /#{s}/ } &&
+                  !OrigenSim.warning_string_exceptions.any? { |s| line =~ /#{s}/ }
+              Origen.log.warn line
             else
               if OrigenSim.verbose? ||
                  OrigenSim.log_strings.any? { |s| line =~ /#{s}/ }

data/lib/origen_sim_dev/dut.rb

@@ -24,6 +24,7 @@ module OrigenSimDev
       add_pin :p4, size: 4, force: 0xA
       add_pin :v1, rtl_name: 'nc'
       add_pin :v2, rtl_name: :nc
+      add_pin :not_present
 
       timeset :func do |t|
         # Generate a clock pulse on TCK

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_sim
 version: !ruby/object:Gem::Version
-  version: 0.11.1
+  version: 0.12.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-06-21 00:00:00.000000000 Z
+date: 2018-06-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen