origen_jtag 0.17.2 → 0.18.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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-  data.tar.gz: b85082877fa5445d506fa80b440b82570522c065
+  metadata.gz: f14027c16a759a2b51fa2b30d9f33cd7447f0a8b
+  data.tar.gz: 8e4c8ebb8dbc3fa97c1955a395ba478b4f2f20a1
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+  data.tar.gz: 2af49cdfdc543a9e1fa0a105dbb7b674aba124034aad6bf1398a89393cd8756f58befc8a247b9bca458a0422e85baaa0c56b942a7870412d16dc64df5967c5b2

data/config/commands.rb

@@ -55,6 +55,38 @@ when "examples", "test"
   ARGV = %w(full_reg_ovly_cap -t debug_RH4 -e uflex.rb -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
 
+  # Pattern generator tests -- confirm sub_block instanced jtag gives same results
+  ARGV = %w(jtag_workout -t new_style_RH1 -e v93k -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(jtag_workout -t new_style_RH1 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(jtag_workout -t new_style_RL1 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(jtag_workout -t new_style_RH2.rb -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(jtag_workout -t new_style_RH2_1.rb -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(jtag_workout -t new_style_RH4 -e v93k -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(jtag_workout -t new_style_RH4 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(jtag_workout -t new_style_RL4 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(rww_test -t new_style_RH4 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(global_label_test -t new_style_RH1 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(full_reg_ovly_cap -t new_style_RH4 -e uflex.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
+  ARGV = %w(two_port -t new_2port_RH4 -e j750.rb -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+
   if Origen.app.stats.changed_files == 0 &&
      Origen.app.stats.new_files == 0 &&
      Origen.app.stats.changed_patterns == 0 &&

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenJTAG
   MAJOR = 0
-  MINOR = 17
-  BUGFIX = 2
+  MINOR = 18
+  BUGFIX = 0
   DEV = nil
 
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')

data/lib/origen_jtag/driver.rb

@@ -13,8 +13,9 @@ module OrigenJTAG
   class Driver
     REQUIRED_PINS = [:tclk, :tdi, :tdo, :tms]
 
+    include Origen::Model
     include TAPController
-    include Origen::Registers
+    # include Origen::Registers
 
     # Returns the object that instantiated the JTAG
     attr_reader :owner
@@ -31,8 +32,13 @@ module OrigenJTAG
     attr_accessor :log_state_changes
 
     def initialize(owner, options = {})
-      @owner = owner
-      validate_pins
+      if owner.is_a?(Hash)
+        @owner = parent
+        options = owner
+      else
+        @owner = owner
+      end
+      validate_pins(options)
 
       # The parent can configure JTAG settings by defining this constant
       if defined?(owner.class::JTAG_CONFIG)
@@ -145,27 +151,27 @@ module OrigenJTAG
         # Set up pin actions for bit transaction (tclk cycle)
 
         # TDI
-        owner.pin(:tdi).drive(tdi_reg[i])
+        @tdi_pin.drive(tdi_reg[i])
 
         # TDO
-        owner.pin(:tdo).dont_care                               # default setting
+        @tdo_pin.dont_care                               # default setting
         if tdo_reg[i]
           if tdo_reg[i].is_to_be_stored?                        # store
             store_tdo_this_tclk = true
-            owner.pin(:tdo).dont_care if Origen.tester.j750?
+            @tdo_pin.dont_care if Origen.tester.j750?
           elsif tdo_reg[i].is_to_be_read?                       # compare/assert
-            owner.pin(:tdo).assert(tdo_reg[i])
+            @tdo_pin.assert(tdo_reg[i])
           end
         end
 
         # TMS
-        owner.pin(:tms).drive(0)
+        @tms_pin.drive(0)
 
         # let tester handle overlay if implemented
         overlay_options = {}
         if tester.respond_to?(:source_memory)
           if ovl_reg[i] && ovl_reg[i].has_overlay? && !Origen.mode.simulation?
-            overlay_options[:pins] = owner.pin(:tdi)
+            overlay_options[:pins] = @tdi_pin
             if global_ovl
               overlay_options[:overlay_str] = global_ovl
             else
@@ -179,8 +185,8 @@ module OrigenJTAG
               end
             end
             tester_subr_overlay = !(options[:no_subr] || global_ovl) && tester.overlay_style == :subroutine
-            owner.pin(:tdi).drive(0) if tester_subr_overlay
-            owner.pin(:tdo).assert(tdo_reg[i]) if options[:read] unless tester_subr_overlay
+            @tdi_pin.drive(0) if tester_subr_overlay
+            @tdo_pin.assert(tdo_reg[i]) if options[:read] unless tester_subr_overlay
             # Force the last bit to be shifted from this method if overlay requested on the last bit
             options[:cycle_last] = true if i == size - 1
           end
@@ -193,9 +199,9 @@ module OrigenJTAG
                 $tester.label(ovl_reg[i].overlay_str)
                 last_overlay_label = ovl_reg[i].overlay_str
               end
-              owner.pin(:tdo).assert(tdo_reg[i]) if options[:read]
+              @tdo_pin.assert(tdo_reg[i]) if options[:read]
             else
-              owner.pin(:tdi).drive(0)
+              @tdi_pin.drive(0)
               call_subroutine = ovl_reg[i].overlay_str
             end
           end
@@ -219,13 +225,13 @@ module OrigenJTAG
           if i != size - 1 || options[:cycle_last]
             if i == size - 1 && options[:includes_last_bit]
               unless tester_subr_overlay
-                owner.pin(:tms).drive(1)
+                @tms_pin.drive(1)
                 @last_data_vector_shifted = true
               end
             end
             tclk_cycle do
               if store_tdo_this_tclk && @next_data_vector_to_be_stored
-                Origen.tester.store_next_cycle(owner.pin(:tdo))
+                Origen.tester.store_next_cycle(@tdo_pin)
               end
               if overlay_options[:pins].nil?
                 Origen.tester.cycle
@@ -234,7 +240,7 @@ module OrigenJTAG
                 overlay_options[:change_data] = false			# data change only on first cycle if overlay
               end
             end
-            owner.pin(:tdo).dont_care
+            @tdo_pin.dont_care
           else
             @deferred_compare = true
             @deferred_store = true if store_tdo_this_tclk
@@ -272,11 +278,11 @@ module OrigenJTAG
                         ((@tclk_format == :rh) && (@tdo_strobe == :tclk_low) && (@tclk_multiple > 1))
 
       # determine whether TDO is set to capture for this TCLK cycle
-      tdo_to_be_captured = owner.pin(:tdo).to_be_captured?
+      tdo_to_be_captured = @tdo_pin.to_be_captured?
 
       # If TDO is already suspended (by an application) then don't do the
       # suspends below since the resume will clear the application's suspend
-      tdo_already_suspended = owner.pin(:tdo).suspended? && !@tdo_suspended_by_driver
+      tdo_already_suspended = @tdo_pin.suspended? && !@tdo_suspended_by_driver
 
       @tclk_multiple.times do |i|
         # 50% duty cycle if @tclk_multiple is even, otherwise slightly off
@@ -285,29 +291,29 @@ module OrigenJTAG
 
         if i < (@tclk_multiple + 1) / 2
           # first half of cycle
-          owner.pin(:tclk).drive(tclk_val)
+          @tck_pin.drive(tclk_val)
           unless tdo_already_suspended
             unless tdo_to_be_captured
               if mask_tdo_half0
                 @tdo_suspended_by_driver = true
-                owner.pin(:tdo).suspend
+                @tdo_pin.suspend
               else
                 @tdo_suspended_by_driver = false
-                owner.pin(:tdo).resume
+                @tdo_pin.resume
               end
             end
           end
         else
           # second half of cycle
-          owner.pin(:tclk).drive(1 - tclk_val)
+          @tck_pin.drive(1 - tclk_val)
           unless tdo_already_suspended
             unless tdo_to_be_captured
               if mask_tdo_half1
                 @tdo_suspended_by_driver = true
-                owner.pin(:tdo).suspend
+                @tdo_pin.suspend
               else
                 @tdo_suspended_by_driver = false
-                owner.pin(:tdo).resume
+                @tdo_pin.resume
               end
             end
           end
@@ -315,7 +321,7 @@ module OrigenJTAG
         yield
       end
       if @tdo_suspended_by_driver
-        owner.pin(:tdo).resume
+        @tdo_pin.resume
         @tdo_suspended_by_driver = false
       end
     end
@@ -328,7 +334,7 @@ module OrigenJTAG
       if @deferred_compare
         @deferred_compare = nil
       else
-        owner.pin(:tdo).dont_care
+        @tdo_pin.dont_care
       end
 
       if @deferred_store
@@ -341,9 +347,9 @@ module OrigenJTAG
 
       tclk_cycle do
         if store_tdo_this_tclk && @next_data_vector_to_be_stored
-          Origen.tester.store_next_cycle(owner.pin(:tdo))
+          Origen.tester.store_next_cycle(@tdo_pin)
         end
-        owner.pin(:tms).drive!(val)
+        @tms_pin.drive!(val)
       end
     end
 
@@ -585,15 +591,24 @@ module OrigenJTAG
 
     # Validates that the parent object (the owner) has defined the necessary
     # pins to implement the JTAG
-    def validate_pins
-      REQUIRED_PINS.each do |name|
-        owner.pin(name)
-      end
+    def validate_pins(options)
+      @tck_pin = options[:tck_pin] if options[:tck_pin]
+      @tdi_pin = options[:tdi_pin] if options[:tdi_pin]
+      @tdo_pin = options[:tdo_pin] if options[:tdo_pin]
+      @tms_pin = options[:tms_pin] if options[:tms_pin]
+
+      @tck_pin = @owner.pin(:tclk) if @tck_pin.nil?
+      @tdi_pin = @owner.pin(:tdi) if @tdi_pin.nil?
+      @tdo_pin = @owner.pin(:tdo) if @tdo_pin.nil?
+      @tms_pin = @owner.pin(:tms) if @tms_pin.nil?
     rescue
       puts 'Missing JTAG pins!'
-      puts "In order to use the JTAG driver your #{owner.class} class must define"
+      puts "In order to use the JTAG driver your #{owner.class} class must either define"
       puts 'the following pins (an alias is fine):'
       puts REQUIRED_PINS
+      puts '-- or --'
+      puts 'Pass the pins in the initialization options:'
+      puts "sub_block :jtag, class_name: 'OrigenJTAG::Driver', tck_pin: dut.pin(:tclk), tdi_pin: dut.pin(:tdi), tdo_pin: dut.pin(:tdo), tms_pin: dut.pin(:tms)"
       raise 'JTAG driver error!'
     end
   end

data/lib/origen_jtag_dev/new_style.rb

@@ -0,0 +1,107 @@
+module OrigenJTAGDev
+  # This is a dummy DUT model which is used
+  # to instantiate and test the JTAG locally
+  # during development.
+  #
+  # It is not included when this library is imported.
+  class NewStyle
+    include Origen::TopLevel
+
+    attr_reader :jtag_config
+
+    def initialize(options = {})
+      @jtag_config = {
+        verbose:         true,
+        tclk_format:     :rh,
+        tclk_multiple:   1,
+        tdo_strobe:      :tclk_high,
+        tdo_store_cycle: 0,
+        init_state:      :unknown
+      }
+      @jtag_config[:tclk_format] = options[:tclk_format] if options[:tclk_format]
+      @jtag_config[:tclk_multiple] = options[:tclk_multiple] if options[:tclk_multiple]
+      @jtag_config[:tdo_strobe] = options[:tdo_strobe] if options[:tdo_strobe]
+      @jtag_config[:tdo_store_cycle] = options[:tdo_store_cycle] if options[:tdo_store_cycle]
+      @jtag_config[:init_state] = options[:init_state] if options[:init_state]
+
+      instantiate_registers(options)
+      instantiate_pins(options)
+      sub_block :jtag, { class_name: 'OrigenJTAG::Driver' }.merge(@jtag_config)
+      if options[:extra_port]
+        sub_block :jtag2, { class_name: 'OrigenJTAG::Driver', tck_pin: pin(:tck_2), tdi_pin: pin(:tdi_2), tdo_pin: pin(:tdo_2), tms_pin: pin(:tms_2) }.merge(@jtag_config)
+      end
+    end
+
+    def instantiate_registers(options = {})
+      reg :test16, 0x0012, size: 16 do |reg|
+        reg.bit 15..8, :bus
+        reg.bit 0, :bit
+      end
+
+      reg :test32, 0x0014, size: 32 do |reg|
+        reg.bit 31..16, :bus
+        reg.bit 0, :bit
+      end
+
+      reg :full16, 0x0012, size: 16 do |reg|
+        reg.bit 15..0, :data
+      end
+    end
+
+    def instantiate_pins(options = {})
+      if options[:invalid_pins]
+        add_pin :tck
+      else
+        add_pin :tclk
+      end
+      add_pin :tdi
+      add_pin :tdo
+      add_pin :tms
+
+      if options[:extra_port]
+        add_pin :tck_2
+        add_pin :tdi_2
+        add_pin :tdo_2
+        add_pin :tms_2
+      end
+    end
+
+    def startup(options = {})
+      tester.set_timeset('nvmbist', 40)
+    end
+
+    # Getter for top-level tclk_format setting
+    def tclk_format
+      @jtag_config[:tclk_format]
+    end
+
+    # Getter for top-level tclk_multiple setting
+    def tclk_multiple
+      @jtag_config[:tclk_multiple]
+    end
+
+    # Getter for top-level tdo_strobe setting
+    def tdo_strobe
+      @jtag_config[:tdo_strobe]
+    end
+
+    # Getter for top-level tdo_store_cycle setting
+    def tdo_store_cycle
+      @jtag_config[:tdo_store_cycle]
+    end
+
+    # Getter for top-level init_state setting
+    def init_state
+      @jtag_config[:init_state]
+    end
+
+    # Wouldn't want to do this in reality, but allows some flexibility duing gem testing
+    def update_jtag_config(cfg, val)
+      if @jtag_config.key?(cfg)
+        @jtag_config[cfg] = val
+      else
+        fail "#{cfg} not a part of @jtag_config"
+      end
+    end
+  end
+end

data/pattern/two_port.rb

@@ -0,0 +1,49 @@
+
+Pattern.create(options = { name: 'two_port' }) do
+
+  ss 'test using first jtag port'
+  jtag = $dut.jtag
+  reg = $dut.reg(:full16)
+
+  cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
+  jtag.write_dr 0xFFFF, size: 16, shift_out_data: 0xA5A5
+
+  cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
+  reg.write(0xFFFF)
+  reg.bits[0..7].read
+  jtag.write_dr 0xFFFF, size: 16, shift_out_data: reg
+
+
+  cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
+  reg.write(0xFFFF)
+  jtag.write_dr reg, shift_out_data: 0xA5A5
+
+  cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
+  reg.write(0xFFFF)
+  reg2 = reg.dup
+  reg2.bits[0..7].read
+  jtag.write_dr reg, size: 16, shift_out_data: reg2
+
+  
+  ss 'test using second jtag port'
+  jtag = $dut.jtag2
+
+  cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
+  jtag.write_dr 0xFFFF, size: 16, shift_out_data: 0xA5A5
+
+  cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
+  reg.write(0xFFFF)
+  reg.bits[0..7].read
+  jtag.write_dr 0xFFFF, size: 16, shift_out_data: reg
+
+
+  cc 'TDO should be HLHL_LHLH_HLHL_LHLH'
+  reg.write(0xFFFF)
+  jtag.write_dr reg, shift_out_data: 0xA5A5
+
+  cc 'TDO should be XXXX_XXXX_HHHH_HHHH'
+  reg.write(0xFFFF)
+  reg2 = reg.dup
+  reg2.bits[0..7].read
+  jtag.write_dr reg, size: 16, shift_out_data: reg2
+end

data/templates/web/index.md.erb

@@ -30,6 +30,66 @@ __NOTE:__ You will also need to include <code>require 'origen_jtag'</code> somew
 
 ### How To Use
 
+#### New Style Example
+
+The driver no longer requires specific pin names (or aliases), supports sub_block instantiation and DUTs with multiple JTAG ports.
+ You are no longer required to include "OrigenJTAG" in your DUT class.
+
+Here is an example integration:
+
+~~~ruby
+class Pioneer
+
+  include Origen::TopLevel
+
+  def initialize
+    add_pin :tclk
+    add_pin :tdi
+    add_pin :tdo
+    add_pin :tms
+
+    add_pin :tck2
+    add_pin :tdi2
+    add_pin :tdo2
+    add_pin :tms2
+
+
+    # In this first instance TCK covers 4 tester cycles,
+    # 2 high then 2 low for each effective TCK pulse.
+    # Strobe TDO only when TCK high.  Only store TDO on last cycle (3)
+
+    # several pluggins use dut.jtag, your default port driver should be named jtag for compatibility
+    sub_block :jtag, class_name: 'OrigenJTAG::Driver',
+                     tclk_format:       :rl,
+                     tclk_multiple:     4,
+                     tdo_strobe:        :tclk_high,
+                     tdo_store_cycle:   3,
+                     tck_pin:           pin(:tclk),
+                     tdi_pin:           pin(:tdi),
+                     tdo_pin:           pin(:tdo),
+                     tms_pin:           pin(:tms)
+
+    # create a driver for a 2nd port like this
+    # note different configuration settings can be used
+    sub_block :jtag_port2, class_name: 'OrigenJTAG::Driver',
+                     tclk_format:       :rh,
+                     tclk_multiple:     2,
+                     tdo_strobe:        :tclk_high,
+                     tdo_store_cycle:   1,
+                     tck_pin:           pin(:tck2),
+                     tdi_pin:           pin(:tdi2),
+                     tdo_pin:           pin(:tdo2),
+                     tms_pin:           pin(:tms2)
+  end
+
+end
+
+dut.jtag                # => jtag driver for the first port (tclk, tdi, tdo, tms)
+dut.jtag_port2          # => jtag driver for the second port (tck2, tdi2, tdo2, tms2)
+~~~
+
+#### Legacy Example
+
 Include the <code>OrigenJTAG</code> module to add a JTAG driver to your class and
 define the required pins.
 Normally the pins would be an alias to existing DUT pins and therefore the
@@ -75,6 +135,8 @@ end
 Pioneer.new.jtag  # => An instance of OrigenJTAG::Driver
 ~~~
 
+#### APIs
+
 Two APIs are provided, the primary one provides canned methods to read and
 write to the IR and DR registers.
 

data/templates/web/index.md.erb~

@@ -0,0 +1,233 @@
+% render "layouts/basic.html" do
+
+%# HTML tags can be embedded in mark down files if you want to do specific custom
+%# formatting like this, but in most cases that is not required.
+<h1><%= Origen.app.namespace %> <span style="font-size: 14px">(<%= Origen.app.version %>)</span></h1>
+
+### Purpose
+
+This plugin provides an ATE driver for an IEEE 1149.1 compliant JTAG interface.
+
+It makes no assumptions about the instruction or data register attributes or higher
+level protocol concerns. For use at DUT model level this plugin would be normally be wrapped in
+a higher level protocol such as [Nexus](http://origen-sdk.org/nexus/).
+
+### How To Import
+
+In your Gemfile add:
+
+~~~ruby
+gem "origen_jtag", ">= <%= Origen.app.version %>"
+~~~
+
+or if your application is a plugin add this to your <code>.gemspec</code>
+
+~~~ruby
+spec.add_development_dependency "origen_jtag", ">= <%= Origen.app.version %>"
+~~~
+
+__NOTE:__ You will also need to include <code>require 'origen_jtag'</code> somewhere in your environment.  This can be done in <code>config/environment.rb</code> for example.
+
+### How To Use
+
+#### New Style Example
+
+The driver no longer requires specific pin names (or aliases), supports sub_block instantiation and DUTs with multiple JTAG ports.
+ You are no longer required to include "OrigenJTAG" in your DUT class.
+
+Here is an example integration:
+
+~~~ruby
+class Pioneer
+
+  include Origen::TopLevel
+
+  # TCK covers 4 tester cycles, 2 high then 2 low for each effective TCK pulse
+  # Strobe TDO only when TCK high.  Only store TDO on last cycle (3)
+  JTAG_CONFIG = {
+    :tclk_format => :rl,
+    :tclk_multiple => 4,
+    :tdo_strobe => :tclk_high,
+    :tdo_store_cycle => 3,
+  }
+
+  def initialize
+    add_pin :tclk
+    add_pin :tdi
+    add_pin :tdo
+    add_pin :tms
+
+    add_pin :tck2
+    add_pin :tdi2
+    add_pin :tdo2
+    add_pin :tms2
+
+
+    # In this first instance TCK covers 4 tester cycles,
+    # 2 high then 2 low for each effective TCK pulse.
+    # Strobe TDO only when TCK high.  Only store TDO on last cycle (3)
+
+    # several pluggins use dut.jtag, your default port driver should be named jtag for compatibility
+    sub_block :jtag, class_name: 'OrigenJTAG::Driver',
+                     tclk_format:       :rl,
+                     tclk_multiple:     4,
+                     tdo_strobe:        :tclk_high,
+                     tdo_store_cycle:   3,
+                     tck_pin:           pin(:tclk),
+                     tdi_pin:           pin(:tdi),
+                     tdo_pin:           pin(:tdo),
+                     tms_pin:           pin(:tms)
+
+    # create a driver for a 2nd port like this
+    # note different configuration settings can be used
+    sub_block :jtag_port2, class_name: 'OrigenJTAG::Driver',
+                     tclk_format:       :rh,
+                     tclk_multiple:     2,
+                     tdo_strobe:        :tclk_high,
+                     tdo_store_cycle:   1,
+                     tck_pin:           pin(:tck2),
+                     tdi_pin:           pin(:tdi2),
+                     tdo_pin:           pin(:tdo2),
+                     tms_pin:           pin(:tms2)
+  end
+
+end
+
+dut.jtag                # => jtag driver for the first port (tclk, tdi, tdo, tms)
+dut.jtag_port2          # => jtag driver for the second port (tck2, tdi2, tdo2, tms2)
+~~~
+
+#### Legacy Example
+
+Include the <code>OrigenJTAG</code> module to add a JTAG driver to your class and
+define the required pins.
+Normally the pins would be an alias to existing DUT pins and therefore the
+JTAG driver module cannot assume them.
+
+Including the module adds a <code>jtag</code> method which will return an instance of
+[<code>OrigenJTAG::Driver</code>](<%= path "api/OrigenJTAG/Driver.html" %>).
+
+The following attributes can be customized by defining a <code>JTAG_CONFIG</code>
+hash:
+
+* **tclk_format** - TCLK timing format,  Return High (:rh) or Return Low (:rl). Default is :rh.
+* **tclk_multiple** - Number of cycles for a single TCLK pulse to cover, to support cases where TCLK needs to be a fraction of another clock period. Assumes 50% duty cycle, specify only even numbers if > 1. Default is :r1.
+* **tdo_strobe** - When using multiple cycles for TCK, which state of TCK to strobe for TDO, :tclk_high or :tclk_low or :tclk_all. Default :tclk_high.
+* **tdo_store_cycle** - When using multiple cycles for TCK, which cycle of TCK to store for TDO if store requested (0 to number of tclk_multiple-1). Default 0
+
+Here is an example integration:
+
+~~~ruby
+class Pioneer
+
+  include OrigenJTAG
+  include Origen::Pins
+
+  # TCK covers 4 tester cycles, 2 high then 2 low for each effective TCK pulse
+  # Strobe TDO only when TCK high.  Only store TDO on last cycle (3)
+  JTAG_CONFIG = {
+    :tclk_format => :rl,
+    :tclk_multiple => 4,
+    :tdo_strobe => :tclk_high,
+    :tdo_store_cycle => 3,
+  }
+
+  def initialize
+    add_pin :tclk
+    add_pin :tdi
+    add_pin :tdo
+    add_pin :tms
+  end
+
+end
+
+Pioneer.new.jtag  # => An instance of OrigenJTAG::Driver
+~~~
+
+#### APIs
+
+Two APIs are provided, the primary one provides canned methods to read and
+write to the IR and DR registers.
+
+These accept either an absolute data value or an Origen register/bit collection.
+
+~~~ruby
+jtag.write_dr 0x1234, :size => 16
+
+# The size option is not required when a register is supplied
+jtag.write_dr $dut.reg(:clkdiv)
+
+# Although it can still be added if the register is not the full data width
+jtag.write_dr $dut.reg(:clkdiv), :size => 32
+
+# A rich read method is available which supports bit-level read, store and overlay operations
+$dut.reg(:clkdiv).bits(:div).read(0x55)
+jtag.read $dut.reg(:clkdiv)
+
+# In cases where both shift in (TDI) and shift out data (TDO) are critical, (e.g. compare shift
+#  out data on a write, or shfit in specific data on a read) the shift_in_data and 
+#  shift_out_data options can be specified.  By default, TDO will be dont care on writes
+#  and TDI will be 0 on reads.
+jtag.write_dr $dut.reg(:clkdiv), :shift_out_data => 0x4321
+jtag.read_dr $udt.reg(:clkdiv), :shift_in_data => 0x5678
+
+# Similar methods exist for the instruction register
+jtag.write_ir 0x1F, :size => 5
+jtag.read_ir 0x1F, :size => 5
+~~~
+
+A secondary API provides low level control of the TAP Controller state machine.
+
+~~~ruby
+jtag.pause_dr do
+  jtag.shift_dr do
+    # The shift method accepts the same arguments as the canned read/write methods
+    jtag.shift 0x55, :size => 32
+  end
+end
+~~~
+
+See the [<code>OrigenJTAG::Driver</code>](<%= path "api/OrigenJTAG/Driver.html" %>) and
+[<code>OrigenJTAG::TAPController</code>](<%= path "api/OrigenJTAG/TAPController.html" %>)
+APIs for more details about the available driver methods.
+
+Any model/controller within a target runtime environment can listen out for JTAG state
+changes by implementing the following callback handler:
+
+~~~ruby
+def on_jtag_state_change(new_state)
+  if new_state == :update_dr
+    # Do something every time we enter this state
+  end
+end
+~~~
+
+
+### How To Setup a Development Environment
+
+[Clone the repository from Github](https://github.com/Origen-SDK/origen_jtag).
+
+An instance of the OrigenJTAG driver is hooked up to a dummy DUT
+object for use in the console:
+
+~~~
+origen i
+
+> $dut.jtag
+=> #<OrigenJTAG::Driver:0x0000001ee48e78>
+~~~
+
+Follow the instructions here if you want to make a 3rd party app
+workspace use your development copy of the OrigenJTAG plugin:
+[Setting up a Plugin Development Environment](http://origen-sdk.org/origen/latest/guides/plugins)
+
+This plugin also contains a test suite, makes sure this passes before committing
+any changes!
+
+~~~
+origen examples
+~~~
+
+<%= disqus_comments %>
+
+% end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_jtag
 version: !ruby/object:Gem::Version
-  version: 0.17.2
+  version: 0.18.0
 platform: ruby
 authors:
 - Stephen McGinty
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2018-03-14 00:00:00.000000000 Z
+date: 2018-04-19 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -59,12 +59,15 @@ files:
 - lib/origen_jtag.rb
 - lib/origen_jtag/driver.rb
 - lib/origen_jtag/tap_controller.rb
+- lib/origen_jtag_dev/new_style.rb
 - lib/origen_jtag_dev/top_level.rb
 - pattern/full_reg_ovly_cap.rb
 - pattern/global_label_test.rb
 - pattern/jtag_workout.rb
 - pattern/rww_test.rb
+- pattern/two_port.rb
 - templates/web/index.md.erb
+- templates/web/index.md.erb~
 - templates/web/layouts/_basic.html.erb
 - templates/web/partials/_navbar.html.erb
 - templates/web/release_notes.md.erb