origen_arm_debug 1.2.0 → 1.3.0
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- checksums.yaml +4 -4
- data/config/commands.rb +2 -0
- data/config/version.rb +1 -1
- data/lib/origen_arm_debug/dap.rb +5 -1
- data/lib/origen_arm_debug/dp_controller_v6.rb +17 -0
- data/lib/origen_arm_debug/jtag_dp_v6.rb +86 -0
- data/lib/origen_arm_debug/jtag_dp_v6_controller.rb +168 -0
- data/lib/origen_arm_debug.rb +3 -0
- data/lib/origen_arm_debug_dev/dut_jtag_axi.rb +15 -0
- data/pattern/v6_workout.rb +114 -0
- data/pattern/workout.rb +5 -1
- data/templates/web/index.md.erb +15 -0
- metadata +6 -2
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
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---
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SHA256:
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-
metadata.gz:
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data.tar.gz:
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metadata.gz: 45cc30ad35c5f7785831b3fa516ce4784e43170ccc21229d5d6744adaa7f08fb
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data.tar.gz: 3962dec63e6fcdc94de242557b36a34472f152ded5d95a1354e16e61fc04af10
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SHA512:
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metadata.gz:
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data.tar.gz:
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metadata.gz: a2060517cd1db17b6ef02d89355c0816f9ebe422b03277dc5a7783bb2cb4bca0ebb6aa795e8e6926800bdbd524ec5d9cc1565ded06ed75626ee4fb130dfe991f
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7
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data.tar.gz: 78a07d7c55c782ee78b025c20b3caf30956f8a550229479c53b53e6b0049f1fe1cb32525e8fbafd44d69ba691ff7d05e7c87d0e5f0747b786af6268394cf3a2e
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data/config/commands.rb
CHANGED
@@ -30,6 +30,8 @@ when "examples", "test"
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load "#{Origen.top}/lib/origen/commands/generate.rb"
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31
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ARGV = %w(workout -t jtag_axi.rb -e j750 -r approved)
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load "#{Origen.top}/lib/origen/commands/generate.rb"
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33
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+
ARGV = %w(v6_workout -t jtag_axi.rb -e j750 -r approved)
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+
load "#{Origen.top}/lib/origen/commands/generate.rb"
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ARGV = %w(workout -t swd -e j750 -r approved)
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load "#{Origen.top}/lib/origen/commands/generate.rb"
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ARGV = %w(workout -t dual_dp -e j750 -r approved)
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data/config/version.rb
CHANGED
data/lib/origen_arm_debug/dap.rb
CHANGED
@@ -20,7 +20,11 @@ module OrigenARMDebug
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20
20
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end
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22
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if options[:jtag] || parent.respond_to?(:jtag)
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23
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-
options[:
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23
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+
if options[:dapv6]
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24
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options[:class_name] = 'JTAG_DPV6'
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else
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26
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options[:class_name] = 'JTAG_DP'
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end
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dps << sub_block(:jtag_dp, options)
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end
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30
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@@ -0,0 +1,17 @@
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module OrigenARMDebug
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# Common methods shared between the SW and JTAG DP controllers
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3
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module DPControllerV6
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# Alias for the ctrlstat register
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5
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def ctrl_stat
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ctrlstat
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7
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end
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8
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# @api private
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def select_ap_reg(reg)
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address = (reg.address & 0xFFFF_FFF0) >> 4
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12
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address1 = (reg.address & 0xFFFF_FFFF_0000_0000) >> 32
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model.select1.write! address1 if model.select1.data != address1
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model.select.bits(:addr).write! address if model.select.bits(:addr).data != address
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end
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end
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end
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@@ -0,0 +1,86 @@
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module OrigenARMDebug
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2
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class JTAG_DPV6
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include Origen::Model
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attr_reader :dpacc_select, :apacc_select
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def initialize(options = {})
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options = {
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ir_size: 4,
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idcode_select: 0b1110,
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11
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abort_select: 0b1000,
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12
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dpacc_select: 0b1010,
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apacc_select: 0b1011
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}.merge(options)
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@dpacc_select = options[:dpacc_select]
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@apacc_select = options[:apacc_select]
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add_reg :ir, 0, size: options[:ir_size]
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# Virtual reg used to represent all of the various 35-bit scan chains
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reg :dr, 0, size: 35 do |reg|
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reg.bit 34..3, :data
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22
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reg.bit 2..1, :a
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23
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reg.bit 0, :rnw
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end
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reg :idcode, options[:idcode_select], access: :ro do |reg|
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27
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reg.bit 31..28, :version
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28
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reg.bit 27..12, :partno
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reg.bit 11..1, :designer
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reg.bit 0, :bit0, reset: 1
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31
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end
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32
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33
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reg :ctrlstat, 0x4, dpbanksel: 0 do |reg|
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34
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reg.bit 31, :csyspwrupack
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35
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reg.bit 30, :csyspwrupreq
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36
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reg.bit 29, :cdbgpwrupack
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37
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reg.bit 28, :cdbgpwrupreq
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38
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reg.bit 27, :cdbgrstack
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39
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reg.bit 26, :cdbgrstreq
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40
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reg.bit 23..12, :trncnt
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41
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reg.bit 11..8, :masklane
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42
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reg.bit 7, :wdataerr
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43
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reg.bit 6, :readok
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44
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reg.bit 5, :stickyerr
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45
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reg.bit 4, :stickycmp
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46
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reg.bit 3..2, :trnmode
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47
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reg.bit 1, :stickyorun
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48
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reg.bit 0, :orundetect
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49
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end
|
50
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|
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reg :select, 0x8 do |reg|
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reg.bit 31..4, :addr
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53
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reg.bit 3..0, :dpbanksel
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54
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end
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55
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56
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reg :select1, 0x4, dpbanksel: 5 do |reg|
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reg.bit 31..0, :addr
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58
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end
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59
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60
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select.write options[:dp_select_reset] if options[:dp_select_reset]
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61
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+
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add_reg :rdbuff, 0xC, access: :ro, reset: 0
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63
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+
|
64
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reg :abort, options[:abort_select], access: :wo do |reg|
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65
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reg.bit 0, :dapabort
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66
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end
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67
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end
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def select
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reg(:select)
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end
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72
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73
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def abort
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74
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reg(:abort)
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75
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end
|
76
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|
77
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def is_jtag?
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78
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true
|
79
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end
|
80
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+
|
81
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def is_swd?
|
82
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false
|
83
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+
end
|
84
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+
alias_method :is_sw?, :is_swd?
|
85
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+
end
|
86
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+
end
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@@ -0,0 +1,168 @@
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1
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module OrigenARMDebug
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2
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class JTAG_DPV6Controller
|
3
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include Origen::Controller
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4
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include Helpers
|
5
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include DPControllerV6
|
6
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+
|
7
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+
def write_register(reg, options = {})
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8
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+
unless reg.writable?
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9
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fail "The :#{reg.name} register is not writeable!"
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10
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end
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11
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+
|
12
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# DP register write
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13
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if reg.owner == model
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14
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# Don't log this one, not really a DP reg and will be included
|
15
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+
# in the JTAG driver log anyway
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16
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if reg.name == :ir
|
17
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+
dut.jtag.write_ir(reg)
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18
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+
else
|
19
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+
|
20
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log "Write JTAG-DP register #{reg.name.to_s.upcase}: #{reg.data.to_hex}" do
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21
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+
if reg.name == :abort
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22
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+
ir.write!(reg.offset)
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23
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+
dr.reset
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24
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+
dr.overlay(nil)
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25
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+
dr[2..0].write(0)
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26
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+
dr[34..3].copy_all(reg)
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27
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+
dut.jtag.write_dr(dr)
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28
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+
|
29
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+
# DPACC
|
30
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+
elsif reg.name == :select
|
31
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+
dp_write(reg)
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32
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+
|
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+
# Some other debug register
|
34
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+
elsif reg.meta.include?(:dpbanksel)
|
35
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+
if model.reg(:select).bits(:dpbanksel).data != reg.meta[:dpbanksel]
|
36
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+
model.reg(:select).bits(:dpbanksel).write! reg.meta[:dpbanksel]
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37
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+
end
|
38
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+
dp_write(reg)
|
39
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+
|
40
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+
else
|
41
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+
fail "Can't write #{reg.name}"
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42
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+
end
|
43
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+
end
|
44
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+
end
|
45
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+
|
46
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+
# AP register write
|
47
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+
else
|
48
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+
|
49
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+
unless reg.owner.is_a?(AP)
|
50
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+
fail 'The JTAG-DP can only write to DP or AP registers!'
|
51
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+
end
|
52
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+
|
53
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+
select_ap_reg(reg)
|
54
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+
dr.reset
|
55
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+
dr.overlay(nil)
|
56
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+
dr[0].write(0)
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57
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+
dr[2..1].write(reg.offset >> 2)
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58
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+
dr[34..3].copy_all(reg)
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59
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+
ir.write!(apacc_select)
|
60
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+
dut.jtag.write_dr(dr, options)
|
61
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+
end
|
62
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+
end
|
63
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+
|
64
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+
def read_register(reg, options = {})
|
65
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+
unless reg.readable?
|
66
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+
fail "The :#{reg.name} register is not readable!"
|
67
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+
end
|
68
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+
|
69
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+
if reg.owner == model
|
70
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+
# Don't log this one, not really a DP reg and will be included
|
71
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+
# in the JTAG driver log anyway
|
72
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+
if reg.name == :ir
|
73
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+
dut.jtag.read_ir(reg)
|
74
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+
else
|
75
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+
|
76
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+
log "Read JTAG-DP register #{reg.name.to_s.upcase}: #{Origen::Utility.read_hex(reg)}" do
|
77
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+
if reg.name == :idcode
|
78
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+
ir.write!(reg.offset)
|
79
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+
dut.jtag.read_dr(reg)
|
80
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+
|
81
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+
# DPACC
|
82
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+
elsif reg.name == :select || reg.name == :rdbuff
|
83
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dp_read(reg, options)
|
84
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+
|
85
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+
# Some other register
|
86
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+
elsif reg.meta.include?(:dpbanksel)
|
87
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+
# Part 1 - Set dpbanksel if required
|
88
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+
if model.reg(:select).bits(:dpbanksel).data != reg.meta[:dpbanksel]
|
89
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+
model.reg(:select).bits(:dpbanksel).write! reg.meta[:dpbanksel]
|
90
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+
end
|
91
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+
|
92
|
+
dp_read(reg, options)
|
93
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+
|
94
|
+
else
|
95
|
+
fail "Can't read #{reg.name}"
|
96
|
+
end
|
97
|
+
end
|
98
|
+
end
|
99
|
+
|
100
|
+
# AP register read
|
101
|
+
else
|
102
|
+
unless reg.owner.is_a?(AP)
|
103
|
+
fail 'The JTAG-DP can only write to DP or AP registers!'
|
104
|
+
end
|
105
|
+
|
106
|
+
# Part 1 - Request read from AP-Register by writing to APACC with RnW=1
|
107
|
+
select_ap_reg(reg)
|
108
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+
dr.reset
|
109
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+
dr.overlay(nil)
|
110
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+
dr[0].write(1)
|
111
|
+
dr[2..1].write(reg.offset >> 2)
|
112
|
+
dr[34..3].write(0)
|
113
|
+
ir.write!(apacc_select)
|
114
|
+
dut.jtag.write_dr(dr)
|
115
|
+
|
116
|
+
# Calling AP should provide any delay parameter for wait states between AP read request
|
117
|
+
# and when the data is available at the RDBUFF DP-Reg
|
118
|
+
if options[:apacc_wait_states]
|
119
|
+
options[:apacc_wait_states].cycles
|
120
|
+
end
|
121
|
+
|
122
|
+
# Part 2 - Now read real data from RDBUFF (DP-Reg)
|
123
|
+
dr.reset
|
124
|
+
dr.overlay(nil)
|
125
|
+
dr[0].write(1)
|
126
|
+
dr[2..1].write(rdbuff.offset >> 2)
|
127
|
+
dr[34..3].copy_all(reg)
|
128
|
+
options[:mask] = options[:mask] << 3 unless options[:mask].nil?
|
129
|
+
ir.write!(dpacc_select)
|
130
|
+
dut.jtag.read_dr(dr, options)
|
131
|
+
end
|
132
|
+
end
|
133
|
+
|
134
|
+
def dp_read(reg, options = {})
|
135
|
+
# Part 1 - Request read from DP-Register by writing to DPACC with RnW=1
|
136
|
+
dr.reset
|
137
|
+
dr.overlay(nil)
|
138
|
+
dr[0].write(1)
|
139
|
+
dr[2..1].write(reg.offset >> 2)
|
140
|
+
dr[34..3].write(0)
|
141
|
+
ir.write!(dpacc_select)
|
142
|
+
dut.jtag.write_dr(dr)
|
143
|
+
|
144
|
+
# Part 2 - Now read real data from RDBUFF (DP-Reg)
|
145
|
+
dr.reset
|
146
|
+
dr.overlay(nil)
|
147
|
+
dr[0].write(1)
|
148
|
+
dr[2..1].write(rdbuff.offset >> 2)
|
149
|
+
dr[34..3].copy_all(reg)
|
150
|
+
options[:mask] = options[:mask] << 3 unless options[:mask].nil?
|
151
|
+
dut.jtag.read_dr(dr, options)
|
152
|
+
end
|
153
|
+
|
154
|
+
def dp_write(reg)
|
155
|
+
dr.reset
|
156
|
+
dr.overlay(nil)
|
157
|
+
dr[0].write(0)
|
158
|
+
dr[2..1].write(reg.offset >> 2)
|
159
|
+
dr[34..3].copy_all(reg)
|
160
|
+
ir.write!(dpacc_select)
|
161
|
+
dut.jtag.write_dr(dr)
|
162
|
+
end
|
163
|
+
|
164
|
+
def base_address
|
165
|
+
model.base_address
|
166
|
+
end
|
167
|
+
end
|
168
|
+
end
|
data/lib/origen_arm_debug.rb
CHANGED
@@ -8,8 +8,11 @@ module OrigenARMDebug
|
|
8
8
|
require 'origen_arm_debug/dap'
|
9
9
|
require 'origen_arm_debug/dap_controller'
|
10
10
|
require 'origen_arm_debug/dp_controller'
|
11
|
+
require 'origen_arm_debug/dp_controller_v6'
|
11
12
|
require 'origen_arm_debug/jtag_dp'
|
12
13
|
require 'origen_arm_debug/jtag_dp_controller'
|
14
|
+
require 'origen_arm_debug/jtag_dp_v6'
|
15
|
+
require 'origen_arm_debug/jtag_dp_v6_controller'
|
13
16
|
require 'origen_arm_debug/sw_dp'
|
14
17
|
require 'origen_arm_debug/sw_dp_controller'
|
15
18
|
require 'origen_arm_debug/ap'
|
@@ -30,6 +30,21 @@ module OrigenARMDebugDev
|
|
30
30
|
options[:dp_select_reset] = 0xC2_0D00
|
31
31
|
# Specify (customize) ARM Debug implementation details
|
32
32
|
sub_block :arm_debug, options
|
33
|
+
|
34
|
+
options[:dapv6] = true
|
35
|
+
options[:class_name] = 'OrigenARMDebug::DAP'
|
36
|
+
options[:mem_aps] = {
|
37
|
+
mem_ap: {
|
38
|
+
base_address: 0x00C2_0000,
|
39
|
+
latency: 16,
|
40
|
+
apreg_access_wait: 8,
|
41
|
+
apmem_access_wait: 8,
|
42
|
+
is_axi: true,
|
43
|
+
csw_reset: 0x1080_6002
|
44
|
+
},
|
45
|
+
mdm_ap: 0x00C3_0000
|
46
|
+
}
|
47
|
+
sub_block :arm_debugv6, options
|
33
48
|
end
|
34
49
|
end
|
35
50
|
end
|
@@ -0,0 +1,114 @@
|
|
1
|
+
pattern_name = "v6_workout_#{dut.arm_debugv6.dp.name}"
|
2
|
+
|
3
|
+
Pattern.create name: pattern_name do
|
4
|
+
|
5
|
+
ss "Tests of direct DP API"
|
6
|
+
dp = dut.arm_debugv6.dp
|
7
|
+
|
8
|
+
dp.idcode.partno.read!(0x12)
|
9
|
+
|
10
|
+
dp.ctrlstat.write!(0x50000000)
|
11
|
+
dp.ctrlstat.read!(0xF0000000)
|
12
|
+
|
13
|
+
dp.select.bits(:addr).write!(0xF)
|
14
|
+
dp.select.read!
|
15
|
+
dp.select1.write! 4
|
16
|
+
dp.select1.read! 4
|
17
|
+
|
18
|
+
dp.abort.dapabort.write!(1)
|
19
|
+
|
20
|
+
ss "Tests of direct AP API"
|
21
|
+
ap = dut.arm_debugv6.mem_ap
|
22
|
+
|
23
|
+
ap.tar.write!(0x1234_0000)
|
24
|
+
|
25
|
+
ap.tar.read!
|
26
|
+
|
27
|
+
ss "Tests of high-level register API"
|
28
|
+
|
29
|
+
ss "Test write register, should write value 0xFF01"
|
30
|
+
dut.reg(:test).write!(0x0000FF01)
|
31
|
+
|
32
|
+
ss "Test write register with overlay, no subroutine"
|
33
|
+
dut.reg(:test).overlay('write_overlay')
|
34
|
+
dut.reg(:test).write!(0x0000FF01, no_subr: true)
|
35
|
+
dut.reg(:test).overlay(nil)
|
36
|
+
|
37
|
+
ss "Test write register with overlay, use subroutine if available"
|
38
|
+
dut.reg(:test).overlay('write_overlay_subr')
|
39
|
+
dut.reg(:test).write!(0x0000FF01)
|
40
|
+
dut.reg(:test).overlay(nil)
|
41
|
+
|
42
|
+
ss "Test read register, should read value 0x0000FF01"
|
43
|
+
dut.reg(:test).read!
|
44
|
+
|
45
|
+
ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
|
46
|
+
dut.reg(:test).overlay('read_overlay')
|
47
|
+
dut.reg(:test).read!(no_subr: true)
|
48
|
+
dut.reg(:test).overlay(nil)
|
49
|
+
|
50
|
+
ss "Test read register, with overlay, use subroutine if available"
|
51
|
+
dut.reg(:test).overlay('read_overlay_subr')
|
52
|
+
dut.reg(:test).read!
|
53
|
+
dut.reg(:test).overlay(nil)
|
54
|
+
|
55
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
56
|
+
dut.reg(:test).read!(mask: 0x0000_000F)
|
57
|
+
|
58
|
+
ss "Test read register with store"
|
59
|
+
dut.reg(:test).store!
|
60
|
+
|
61
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
62
|
+
dut.reg(:test).reset
|
63
|
+
dut.reg(:test).data = 0x0000FF01
|
64
|
+
dut.reg(:test)[0].read!
|
65
|
+
|
66
|
+
if Origen.app.target.name == 'dual_dp'
|
67
|
+
ss "SWITCHING DP"
|
68
|
+
dut.arm_debugv6.set_dp(:jtag)
|
69
|
+
|
70
|
+
ss "Test write register, should write value 0xFF01"
|
71
|
+
dut.reg(:test).write!(0x0000FF01)
|
72
|
+
|
73
|
+
ss "Test write register with overlay, no subroutine"
|
74
|
+
dut.reg(:test).overlay('write_overlay')
|
75
|
+
dut.reg(:test).write!(0x0000FF01, no_subr: true)
|
76
|
+
dut.reg(:test).overlay(nil)
|
77
|
+
|
78
|
+
ss "Test write register with overlay, use subroutine if available"
|
79
|
+
dut.reg(:test).overlay('write_overlay_subr')
|
80
|
+
dut.reg(:test).write!(0x0000FF01)
|
81
|
+
dut.reg(:test).overlay(nil)
|
82
|
+
|
83
|
+
ss "Test read register, should read value 0x0000FF01"
|
84
|
+
dut.reg(:test).read!
|
85
|
+
|
86
|
+
ss "Test read register, with overlay, no subroutine, should read value 0x0000FF01"
|
87
|
+
dut.reg(:test).overlay('read_overlay')
|
88
|
+
dut.reg(:test).read!(no_subr: true)
|
89
|
+
dut.reg(:test).overlay(nil)
|
90
|
+
|
91
|
+
ss "Test read register, with overlay, use subroutine if available"
|
92
|
+
dut.reg(:test).overlay('read_overlay_subr')
|
93
|
+
dut.reg(:test).read!
|
94
|
+
dut.reg(:test).overlay(nil)
|
95
|
+
|
96
|
+
ss "Test read register with mask, should read value 0xXXXxxx1"
|
97
|
+
dut.reg(:test).read!(mask: 0x0000_000F)
|
98
|
+
|
99
|
+
ss "Test read register with store"
|
100
|
+
dut.reg(:test).store!
|
101
|
+
|
102
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
103
|
+
dut.reg(:test).reset
|
104
|
+
dut.reg(:test).data = 0x0000FF01
|
105
|
+
dut.reg(:test)[0].read!
|
106
|
+
|
107
|
+
ss "RESETTING DP (to default)"
|
108
|
+
dut.arm_debugv6.reset_dp
|
109
|
+
ss "Test bit level read, should read value 0xXXXxxx1"
|
110
|
+
dut.reg(:test).reset
|
111
|
+
dut.reg(:test).data = 0x0000FF01
|
112
|
+
dut.reg(:test)[0].read!
|
113
|
+
end
|
114
|
+
end
|
data/pattern/workout.rb
CHANGED
@@ -16,7 +16,11 @@ Pattern.create name: pattern_name do
|
|
16
16
|
dp.ctrlstat.write!(0x50000000)
|
17
17
|
dp.ctrlstat.read!(0xF0000000)
|
18
18
|
|
19
|
-
dp.select.apbanksel
|
19
|
+
if dp.select.has_bits?(:apbanksel)
|
20
|
+
dp.select.apbanksel.write!(0xF)
|
21
|
+
else
|
22
|
+
dp.select.bits(31..24).write!(0xF)
|
23
|
+
end
|
20
24
|
|
21
25
|
dp.abort.dapabort.write!(1)
|
22
26
|
|
data/templates/web/index.md.erb
CHANGED
@@ -138,6 +138,21 @@ instantiation_options[:dp_select_reset] = 0xC2_0D00
|
|
138
138
|
sub_block :arm_debug, instantiation_options
|
139
139
|
~~~
|
140
140
|
|
141
|
+
DAP Version 6 instantiation example:
|
142
|
+
|
143
|
+
~~~ruby
|
144
|
+
mem_aps = {
|
145
|
+
mem_ap: { base_address: 0x001C_1000 }
|
146
|
+
mem2_ap: { base_address: 0x001C_2000 }
|
147
|
+
}
|
148
|
+
instantiation_options[:class_name] = 'OrigenARMDebug::DAP'
|
149
|
+
instantiation_options[:mem_aps] = mem_aps
|
150
|
+
|
151
|
+
instantiation_options[:dapv6] = true
|
152
|
+
|
153
|
+
sub_block :arm_debug, instantiation_options
|
154
|
+
~~~
|
155
|
+
|
141
156
|
### Company Customization
|
142
157
|
|
143
158
|
It may be the case that your application needs additional, customized Access Ports (AP) which are allowed but
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: origen_arm_debug
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 1.
|
4
|
+
version: 1.3.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Ronnie Lajaunie
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2022-
|
11
|
+
date: 2022-02-28 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: origen
|
@@ -87,11 +87,14 @@ files:
|
|
87
87
|
- lib/origen_arm_debug/dap.rb
|
88
88
|
- lib/origen_arm_debug/dap_controller.rb
|
89
89
|
- lib/origen_arm_debug/dp_controller.rb
|
90
|
+
- lib/origen_arm_debug/dp_controller_v6.rb
|
90
91
|
- lib/origen_arm_debug/helpers.rb
|
91
92
|
- lib/origen_arm_debug/jtag_ap.rb
|
92
93
|
- lib/origen_arm_debug/jtag_ap_controller.rb
|
93
94
|
- lib/origen_arm_debug/jtag_dp.rb
|
94
95
|
- lib/origen_arm_debug/jtag_dp_controller.rb
|
96
|
+
- lib/origen_arm_debug/jtag_dp_v6.rb
|
97
|
+
- lib/origen_arm_debug/jtag_dp_v6_controller.rb
|
95
98
|
- lib/origen_arm_debug/mem_ap.rb
|
96
99
|
- lib/origen_arm_debug/mem_ap_controller.rb
|
97
100
|
- lib/origen_arm_debug/sw_dp.rb
|
@@ -101,6 +104,7 @@ files:
|
|
101
104
|
- lib/origen_arm_debug_dev/dut_jtag.rb
|
102
105
|
- lib/origen_arm_debug_dev/dut_jtag_axi.rb
|
103
106
|
- lib/origen_arm_debug_dev/dut_swd.rb
|
107
|
+
- pattern/v6_workout.rb
|
104
108
|
- pattern/workout.rb
|
105
109
|
- templates/web/index.md.erb
|
106
110
|
- templates/web/layouts/_basic.html.erb
|