origen_arm_debug 1.1.4 → 1.2.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
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-  data.tar.gz: d605f5cf618b53f2eff53ed0af3eab442d6bfe0a4292abd37895e51ddd1436bc
+  metadata.gz: 292e4be7741df68524ba13a6af2058a9ca209688ddf12ca19c63a1e2e795135c
+  data.tar.gz: 58fd3ee8010c9cba1bd4675896fd8a5aa0d9e579113aaeac7ceb30c5039467ac
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+  metadata.gz: 880aef44c21b1a5030223b9d7a0155f0284109c9dcc8c711bdab5e95e0dc8f347a4920d93cfb993dcc51e7104fa91b740699c504a3d797a7c3e12252739357e8
+  data.tar.gz: 15f565c00daa931914a1b9be94894810a2bdccbd19e1553a013dc1234d1cb01b76484e2bc7e47697cb5ee3307fd03ff7e7484577171120579c35aa37e5e392b5

data/config/boot.rb

@@ -4,3 +4,4 @@ require "origen_arm_debug_dev/dut"
 require "origen_arm_debug_dev/dut_jtag"
 require "origen_arm_debug_dev/dut_swd"
 require "origen_arm_debug_dev/dut_dual_dp"
+require "origen_arm_debug_dev/dut_jtag_axi"

data/config/commands.rb

@@ -26,7 +26,9 @@ when "examples", "test"
   status = 0
   
   # Pattern generator tests
-  ARGV = %w(workout -t jtag -e j750 -r approved)
+  ARGV = %w(workout -t jtag.rb -e j750 -r approved)
+  load "#{Origen.top}/lib/origen/commands/generate.rb"
+  ARGV = %w(workout -t jtag_axi.rb -e j750 -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"
   ARGV = %w(workout -t swd -e j750 -r approved)
   load "#{Origen.top}/lib/origen/commands/generate.rb"

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenARMDebug
   MAJOR = 1
-  MINOR = 1
-  BUGFIX = 4
+  MINOR = 2
+  BUGFIX = 0
   DEV = nil
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/lib/origen_arm_debug/dap.rb

@@ -70,11 +70,13 @@ module OrigenARMDebug
     #
     def add_ap(name, options)
       domain name.to_sym
+      # class name is deleted from options in sub_block call
+      class_name = options[:class_name]
       ap = sub_block(name.to_sym, options)
 
-      if options[:class_name] == 'MemAP'
+      if class_name == 'MemAP'
         mem_aps << ap
-      elsif options[:class_name] == 'JTAGAP'
+      elsif class_name == 'JTAGAP'
         jtag_aps << ap
       else
         ext_aps << ap

data/lib/origen_arm_debug/dp_controller.rb

@@ -9,8 +9,14 @@ module OrigenARMDebug
     # @api private
     def select_ap_reg(reg)
       address = reg.address & 0xFFFF_FFF0
-      if model.select.data != address
-        model.select.write!(address)
+      apsel = (reg.address & 0xFF00_0000) >> 24
+      apbanksel = (reg.address & 0xF0) >> 4
+      # if model.select.data != address
+      if model.select.apsel.data != apsel || model.select.apbanksel.data != apbanksel
+        model.select.write! do |r|
+          r.apsel.write apsel
+          r.apbanksel.write apbanksel
+        end
       end
     end
   end

data/lib/origen_arm_debug/jtag_dp.rb

@@ -48,9 +48,12 @@ module OrigenARMDebug
 
       reg :select, 0x8 do |reg|
         reg.bit 31..24, :apsel
+        reg.bit 23..8,  :reserved
         reg.bit 7..4, :apbanksel
       end
 
+      select.write options[:dp_select_reset] if options[:dp_select_reset]
+
       add_reg :rdbuff, 0xC, access: :ro, reset: 0
 
       reg :abort, options[:abort_select], access: :wo do |reg|

data/lib/origen_arm_debug/mem_ap.rb

@@ -14,21 +14,52 @@ module OrigenARMDebug
     #   For SWD, this is the wait states in between setting the AP, initiating and completing a dummy read, and beginning the actual read transaction.
     attr_accessor :apacc_wait_states
 
+    # Boolean value indicating whether this is an AXI-AP
+    attr_accessor :is_axi
+
+    # Value to be read from DP CSW for interleaved status checks (debug feature)
+    attr_accessor :csw_status_check
+
+    # Boolean value indicating whether to interleave status checks during transactions (debug feature)
+    attr_accessor :interleave_status_check
+
     def initialize(options = {})
       super
 
+      @is_axi = options[:is_axi]
+      @csw_status_check = options[:csw_status_check]
+      @interleave_status_check = options[:interleave_status_check]
+
       @latency = options[:latency] || 0
       @apmem_access_wait = options[:apmem_access_wait] || 0
 
-      reg :csw, 0x0 do |reg|
-        reg.bit 31,     :dbg_sw_enable
-        reg.bit 30..24, :prot
-        reg.bit 23,     :spiden
-        reg.bit 11..8,  :mode
-        reg.bit 7,      :tr_in_prog
-        reg.bit 6,      :device_en
-        reg.bit 5..4,   :addr_inc
-        reg.bit 2..0,   :size
+      if @is_axi
+        reg :csw, 0x0 do |reg|
+          reg.bit 31,     :reserved
+          reg.bit 30..28, :prot, res: 3
+          reg.bit 27..24, :cache
+          reg.bit 23,     :spiden
+          reg.bit 22..15, :reserved2
+          reg.bit 14..13, :domain, res: 3
+          reg.bit 12,     :ace_enable
+          reg.bit 11..8,  :mode
+          reg.bit 7,      :tr_in_prog
+          reg.bit 6,      :dbg_status, res: 1
+          reg.bit 5..4,   :addr_inc
+          reg.bit 3,      :reserved3
+          reg.bit 2..0,   :size, res: 2
+        end
+      else
+        reg :csw, 0x0 do |reg|
+          reg.bit 31,     :dbg_sw_enable
+          reg.bit 30..24, :prot
+          reg.bit 23,     :spiden
+          reg.bit 11..8,  :mode
+          reg.bit 7,      :tr_in_prog
+          reg.bit 6,      :device_en
+          reg.bit 5..4,   :addr_inc
+          reg.bit 2..0,   :size
+        end
       end
       reg(:csw).write(options[:csw_reset]) if options[:csw_reset]
 

data/lib/origen_arm_debug/mem_ap_controller.rb

@@ -18,11 +18,13 @@ module OrigenARMDebug
         log "Write MEM-AP (#{model.name}) address #{addr.to_hex}: #{data.to_hex}" do
           csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
           tar.write!(addr) unless tar.data == addr
+          parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
           drw.reset
           drw.overlay(nil)
           drw.copy_all(reg_or_val)
           drw.write!(options)
           latency.cycles
+          parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
         end
         increment_addr
       end
@@ -43,11 +45,13 @@ module OrigenARMDebug
           csw.bits(:size).write!(0b010) if csw.bits(:size).data != 0b010
           unless tar.data == addr
             tar.write!(addr)
+            parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
           end
           drw.reset
           drw.overlay(nil)
           drw.copy_all(reg_or_val)
           parent.dp.read_register(drw, options.merge(apacc_wait_states: (apmem_access_wait + apreg_access_wait)))
+          parent.dp.ctrlstat.read! model.csw_status_check if model.interleave_status_check
         end
         increment_addr
       end

data/lib/origen_arm_debug_dev/dut_jtag_axi.rb

@@ -0,0 +1,35 @@
+module OrigenARMDebugDev
+  # Simple JTAG-specific dut model that inherits from protocol-agnostic DUT model
+  class JTAG_AXI_DUT < DUT
+    include OrigenJTAG
+
+    # Adds jtag-required pins to the simple dut model
+    # Returns nothing.
+    def initialize(options = {})
+      super
+      add_pin :tclk
+      add_pin :tdi
+      add_pin :tdo
+      add_pin :tms
+      add_pin :trst
+      add_pin :swd_clk
+      add_pin :swd_dio
+
+      options[:class_name] = 'OrigenARMDebug::DAP'
+      options[:mem_aps] = {
+        mem_ap: {
+          base_address:      0x00000000,
+          latency:           16,
+          apreg_access_wait: 8,
+          apmem_access_wait: 8,
+          is_axi:            true,
+          csw_reset:         0x1080_6002
+        },
+        mdm_ap: 0x01000000
+      }
+      options[:dp_select_reset] = 0xC2_0D00
+      # Specify (customize) ARM Debug implementation details
+      sub_block :arm_debug, options
+    end
+  end
+end

data/pattern/workout.rb

@@ -1,5 +1,7 @@
 if Origen.app.target.name == 'dual_dp'
   pattern_name = 'workout_dual_dp'
+elsif Origen.app.target.name == 'jtag_axi'
+  pattern_name = 'workout_jtag_axi'
 else
   pattern_name = "workout_#{dut.arm_debug.dp.name}"
 end

data/templates/web/index.md.erb

@@ -52,7 +52,7 @@ class DUT
     
     # Simple example using default wait-states and latency:
     #   mem_ap:  APSEL = 0x00 (base_address[31:24])
-    #   mem2_ap: APSEL = 0x01 (base_address[31:24])
+    #   mem2_ap: APSEL = 0x01 (base_address[31:24], is_axi: true)	# is_axi: true for AXI-AP
     mem_aps = {
       mem_ap: { base_address: 0x00000000 },
       mem2_ap: { base_address: 0x10000000 }
@@ -133,6 +133,7 @@ instantiation_options[:idcode_select] = 0xFE
 instantiation_options[:abort_select] = 0xF8
 instantiation_options[:dpacc_select] = 0xFA
 instantiation_options[:apacc_select] = 0xFB
+instantiation_options[:dp_select_reset] = 0xC2_0D00
 
 sub_block :arm_debug, instantiation_options
 ~~~

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_arm_debug
 version: !ruby/object:Gem::Version
-  version: 1.1.4
+  version: 1.2.0
 platform: ruby
 authors:
 - Ronnie Lajaunie
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-05-14 00:00:00.000000000 Z
+date: 2022-01-28 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -99,6 +99,7 @@ files:
 - lib/origen_arm_debug_dev/dut.rb
 - lib/origen_arm_debug_dev/dut_dual_dp.rb
 - lib/origen_arm_debug_dev/dut_jtag.rb
+- lib/origen_arm_debug_dev/dut_jtag_axi.rb
 - lib/origen_arm_debug_dev/dut_swd.rb
 - pattern/workout.rb
 - templates/web/index.md.erb
@@ -124,8 +125,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: 1.8.11
 requirements: []
-rubyforge_project: 
-rubygems_version: 2.7.7
+rubygems_version: 3.1.4
 signing_key: 
 specification_version: 4
 summary: Provides an Origen API to perform register read and write operations via