origen_arm 0.1.1 → 0.1.2

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: e94c021eca23399846f9247e568c125e30ec67bb7c08b710111a34f6cf78eeec
-  data.tar.gz: eebec830498c20852c7a7a8582d89caebfde420d18b599b2300ddf93736eff49
+  metadata.gz: e02b7063e59e3d22c23a64cbf1f2e2b025ea210b2b93791adc2a3c4fb7f5a2e7
+  data.tar.gz: 44be8fba43e62006369332839ed1080c49bcdc0860adc9ec77389fb392b1087d
 SHA512:
-  metadata.gz: 88e77a2be08addf1f9473821c9a937f7a888c048f13a9c1498cf7acb70fb738668aa528efee852ea739536134fbd2065955d4af8f445734afb8901a22c35ff2e
-  data.tar.gz: 0d1b6a98450c087fd9bee342a5bb2899ba1e91e0ebacf1d2ebf4d659982c2210fb4dfbfcb2ebf14ed86a1ec774a3ef243f91bb41e9d8fadc7a116e7e63e48e8e
+  metadata.gz: 88f734f3318c999a3515ccca81a04218a048f348d144dcfd7f7ec490bf6a3317430212553a585d101a7555fa46efa9d7042ac2f7490b52d72d5f0eec482fc124
+  data.tar.gz: b115dfa55c6640c4454316a5a7d986228c805f337074cc07e82973045451337bb7d8b75f3aeb6c53f7a5a129353f49327cadc1a04d683c4262f9c6067ba4834e

data/config/version.rb

@@ -1,7 +1,7 @@
 module OrigenARM
   MAJOR = 0
   MINOR = 1
-  BUGFIX = 1
+  BUGFIX = 2
   DEV = nil
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/lib/origen_arm/cores/base_core/core.rb

@@ -2,8 +2,10 @@ module OrigenARM
   module Cores
     class Base
       include Origen::Model
+      attr_reader :cpu_wait_release
 
       def initialize(options = {})
+        @cpu_wait_release = options[:cpu_wait_release]
       end
 
       #

data/lib/origen_arm/cores/cortexa/ca35/ca35.rb

@@ -16,25 +16,32 @@ module OrigenARM
         CTI_BASE = 0x0042_0000
         DBG_BASE = 0x0041_0000
 
+        attr_reader :core_num, :reg_base_core_num_offset
+        attr_reader :halt_channel, :release_channel
+
         def initialize(options = {})
+          @core_num = options[:core_num] || 0
+          @reg_base_core_num_offset = options[:reg_base_core_num_offset] || (0x10_0000 * core_num)
+          @halt_channel = options[:halt_channel] || (1 << core_num)
+          @release_channel = options[:release_channel] || (4 << core_num)
           super
           instantiate_registers(options)
         end
 
         def instantiate_registers(options)
-          add_reg(:trace_dbg_edprsr, DBG_BASE + TRACE_DBG_EDPRSR_OFFSET, size: 32)
-          add_reg(:trace_dbg_editr, DBG_BASE + TRACE_DBG_EDITR_OFFSET, size: 32)
-          add_reg(:trace_dbg_edscr, DBG_BASE + TRACE_DBG_EDSCR_OFFSET, size: 32)
-          add_reg(:trace_dbg_dtrtx, DBG_BASE + TRACE_DBG_DTRTX_OFFSET, size: 32)
-          add_reg(:trace_dbg_dtrrx, DBG_BASE + TRACE_DBG_DTRRX_OFFSET, size: 32)
-          add_reg(:trace_dbg_lar, DBG_BASE + TRACE_LAR_OFFSET, size: 32)
-          add_reg(:trace_dbg_oslar, DBG_BASE + TRACE_OSLAR_OFFSET, size: 32)
-          add_reg(:trace_cti_ctrl, CTI_BASE + TRACE_CTI_CTRL_OFFSET, size: 32)
-          add_reg(:trace_cti_outen0, CTI_BASE + TRACE_CTI_OUTEN0_OFFSET, size: 32)
-          add_reg(:trace_cti_outen1, CTI_BASE + TRACE_CTI_OUTEN0_OFFSET + 0x4, size: 32)
-          add_reg(:trace_cti_apppulse, CTI_BASE + TRACE_CTI_APPPULSE_OFFSET, size: 32)
-          add_reg(:trace_cti_intack, CTI_BASE + TRACE_CTI_INTACK_OFFSET, size: 32)
-          add_reg(:trace_cti_lar, CTI_BASE + TRACE_LAR_OFFSET, size: 32)
+          add_reg(:trace_dbg_edprsr, DBG_BASE + reg_base_core_num_offset + TRACE_DBG_EDPRSR_OFFSET, size: 32)
+          add_reg(:trace_dbg_editr, DBG_BASE + reg_base_core_num_offset + TRACE_DBG_EDITR_OFFSET, size: 32)
+          add_reg(:trace_dbg_edscr, DBG_BASE + reg_base_core_num_offset + TRACE_DBG_EDSCR_OFFSET, size: 32)
+          add_reg(:trace_dbg_dtrtx, DBG_BASE + reg_base_core_num_offset + TRACE_DBG_DTRTX_OFFSET, size: 32)
+          add_reg(:trace_dbg_dtrrx, DBG_BASE + reg_base_core_num_offset + TRACE_DBG_DTRRX_OFFSET, size: 32)
+          add_reg(:trace_dbg_lar, DBG_BASE + reg_base_core_num_offset + TRACE_LAR_OFFSET, size: 32)
+          add_reg(:trace_dbg_oslar, DBG_BASE + reg_base_core_num_offset + TRACE_OSLAR_OFFSET, size: 32)
+          add_reg(:trace_cti_ctrl, CTI_BASE + reg_base_core_num_offset + TRACE_CTI_CTRL_OFFSET, size: 32)
+          add_reg(:trace_cti_outen0, CTI_BASE + reg_base_core_num_offset + TRACE_CTI_OUTEN0_OFFSET, size: 32)
+          add_reg(:trace_cti_outen1, CTI_BASE + reg_base_core_num_offset + TRACE_CTI_OUTEN0_OFFSET + 0x4, size: 32)
+          add_reg(:trace_cti_apppulse, CTI_BASE + reg_base_core_num_offset + TRACE_CTI_APPPULSE_OFFSET, size: 32)
+          add_reg(:trace_cti_intack, CTI_BASE + reg_base_core_num_offset + TRACE_CTI_INTACK_OFFSET, size: 32)
+          add_reg(:trace_cti_lar, CTI_BASE + reg_base_core_num_offset + TRACE_LAR_OFFSET, size: 32)
         end
       end
     end

data/lib/origen_arm/cores/cortexa/ca35/ca35_controller.rb

@@ -2,7 +2,7 @@ module OrigenARM
   module Cores
     module CortexA
       class CA35Controller < OrigenARM::Cores::BaseController
-        def initialize_core(pc:, release_core: false, **options)
+        def initialize_core(pc:, sp: nil, release_core: false, **options)
           halt_core!
           set_pc!(pc)
 
@@ -15,8 +15,8 @@ module OrigenARM
           ss 'Halt core - channel 0'
           reg(:trace_cti_lar).write!(0xC5AC_CE55)
           reg(:trace_cti_ctrl).write!(0x1)
-          reg(:trace_cti_outen0).write!(0x1)
-          reg(:trace_cti_apppulse).write!(0x1)
+          reg(:trace_cti_outen0).write!(halt_channel)
+          reg(:trace_cti_apppulse).write!(halt_channel)
           tester.cycle(repeat: 10_000)
 
           ss 'Check that the core is halted'
@@ -27,7 +27,7 @@ module OrigenARM
           tester.cycle(repeat: 100)
 
           reg(:trace_dbg_lar).write!(0xC5AC_CE55)
-          reg(:trace_dbg_oslar).write!(0xABCD_1234)
+          reg(:trace_dbg_oslar).write!(0)
           tester.cycle(repeat: 100)
         end
 
@@ -35,8 +35,8 @@ module OrigenARM
           ss 'Release core - channel 2'
           reg(:trace_cti_lar).write!(0xC5AC_CE55)
           reg(:trace_cti_ctrl).write!(0x1)
-          reg(:trace_cti_outen1).write!(0x4)
-          reg(:trace_cti_apppulse).write!(0x4)
+          reg(:trace_cti_outen1).write!(release_channel) # 0x4)
+          reg(:trace_cti_apppulse).write!(release_channel) # (0x4)
           tester.cycle(repeat: 100)
           ss 'Check that the core has been released'
           reg(:trace_dbg_edprsr).read!(0x0, mask: 0x0000_0010)

data/lib/origen_arm/cores/cortexm/base_cortexm/cortexm_registers.rb

@@ -74,7 +74,7 @@ module OrigenARM
             # XPSR
             # Note: This register also seems mostly stable across the entire
             # CortexM family, but may need to be revisited as more cores are added.
-            dut.add_reg(:xpsr, 0x0, size: 32, description: 'Combined Program Status Register. Combination of APSR, EPSR, and IPSR Registers on Other ARM Cores.') do |r|
+            dut.add_reg(:xpsr, 0x10, size: 32, description: 'Combined Program Status Register. Combination of APSR, EPSR, and IPSR Registers on Other ARM Cores.') do |r|
               r.bits 31, :n, description: 'Negative flag. Reads or writes the current value of APSR.N.'
               r.bits 30, :z, description: 'Zero flag. Reads or writes the current value of APSR.Z.'
               r.bits 29, :c, description: 'Carry flag. Reads or writes the current value of APSR.C.'

data/lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb

@@ -14,8 +14,9 @@ module OrigenARM
         # @param sp_lower_limit [Fixnum] Sets stack pointer's lower limit.
         # @param sp_upper_limit [Fixnum] Sets stack pointer's upper limit.
         # @todo Implement lower and upper stack pointer limit setting.
-        def initialize_core(pc:, sp:, release_core: false, sp_lower_limit: nil, sp_upper_limit: nil)
-          enter_debug_mode
+        # rubocop:disable Metrics/ParameterLists
+        def initialize_core(pc:, sp:, release_core: false, sp_lower_limit: nil, sp_upper_limit: nil, release_cpu_wait: true)
+          enter_debug_mode(release_cpu_wait: release_cpu_wait)
 
           # clear_state
           # clear_state
@@ -38,13 +39,14 @@ module OrigenARM
           # reg(:aircr).bits(:sysresetreq).write(1)
           # reg(:aircr).write!
         end
+        # rubocop:enable Metrics/ParameterLists
         alias_method :initialize_for_lre, :initialize_core
 
         # Enters the core's debug mode.
         # @param halt_core [true, false] Indicates whether the core should be held when entering debug mode.
         #   Some functionality may not work correctly if the core is not halted,
         #   but a halted core is not a requirement for debug mode.
-        def enter_debug_mode(halt_core: true)
+        def enter_debug_mode(halt_core: true, release_cpu_wait: true)
           pp('Entering Debug Mode...') do
             reg(:dhcsr).bits(:dbgkey).write(OrigenARM::Cores::CortexM::CM33::Registers::DHCSR_DBGKEY)
             reg(:dhcsr).bits(:c_debugen).write(1)
@@ -59,6 +61,12 @@ module OrigenARM
               reg(:dhcsr).write!
               enter_debug_mode_delay!
             end
+
+            if release_cpu_wait
+              if cpu_wait_release
+                cpu_wait_release.call(self)
+              end
+            end
           end
         end
 

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_arm
 version: !ruby/object:Gem::Version
-  version: 0.1.1
+  version: 0.1.2
 platform: ruby
 authors:
 - Corey Engelken
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2020-08-08 00:00:00.000000000 Z
+date: 2022-05-14 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -86,8 +86,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
     - !ruby/object:Gem::Version
       version: 1.8.11
 requirements: []
-rubyforge_project: 
-rubygems_version: 2.7.6
+rubygems_version: 3.1.4
 signing_key: 
 specification_version: 4
 summary: Origen subblocks modeling ARM cores.