origen_arm 0.1.0 → 0.1.1

checksums.yaml

@@ -1,7 +1,7 @@
 ---
 SHA256:
-  metadata.gz: aac2a9ad38cd6455af8072078ce1323050ffa8ccd807a309aa162f7a495a1d04
-  data.tar.gz: 40fcc38125de73c08bccb499ffda8e60815ccb46b44b0e96abe50e4e5f8dc2d5
+  metadata.gz: e94c021eca23399846f9247e568c125e30ec67bb7c08b710111a34f6cf78eeec
+  data.tar.gz: eebec830498c20852c7a7a8582d89caebfde420d18b599b2300ddf93736eff49
 SHA512:
-  metadata.gz: d558d399e03bd7da9209cf3872801c3d975424682982bdeb5744649ad06a916bacc2e203c9a816c06b9c3d25c57bb3d34d647f196f9799e07789f037c03fdb4d
-  data.tar.gz: 5271ac914b8d3df3e8e5fd9f0c0a2f9c2fec65166e5c235c66f73187ecb14bf85b6aa17c248f25c5ab8fd34a3c4611c5319eb7e782a2ffa25df08ecb0d74a371
+  metadata.gz: 88e77a2be08addf1f9473821c9a937f7a888c048f13a9c1498cf7acb70fb738668aa528efee852ea739536134fbd2065955d4af8f445734afb8901a22c35ff2e
+  data.tar.gz: 0d1b6a98450c087fd9bee342a5bb2899ba1e91e0ebacf1d2ebf4d659982c2210fb4dfbfcb2ebf14ed86a1ec774a3ef243f91bb41e9d8fadc7a116e7e63e48e8e

data/config/version.rb

@@ -1,8 +1,7 @@
 module OrigenARM
   MAJOR = 0
   MINOR = 1
-  BUGFIX = 0
+  BUGFIX = 1
   DEV = nil
-
   VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
 end

data/lib/origen_arm/cores/base_core/core.rb

@@ -1,8 +1,17 @@
 module OrigenARM
   module Cores
     class Base
+      include Origen::Model
+
       def initialize(options = {})
       end
+
+      #
+      #       def mpu?
+      #       end
+      #
+      #       def mcu?
+      #       end
     end
   end
 end

data/lib/origen_arm/cores/base_core/core_controller.rb

@@ -1,8 +1,27 @@
 module OrigenARM
   module Cores
     class BaseController
+      include Origen::Controller
+
       def initialize(options = {})
       end
+      #       def halt!(options={})
+      #       end
+      #
+      #       def release!(options={})
+      #       end
+      #
+      #       def set_pc!(pc, options={})
+      #       end
+      #
+      #       def set_sp!(sp, options={})
+      #       end
+      #
+      #       def with_debug_mode(options={}, &block)
+      #       end
+      #
+      #       def initialize_core(pc: nil, sp: nil, **options)
+      #       end
     end
   end
 end

data/lib/origen_arm/cores/cortexa/ca35/ca35.rb

@@ -0,0 +1,42 @@
+module OrigenARM
+  module Cores
+    module CortexA
+      class CA35 < OrigenARM::Cores::Base
+        TRACE_DBG_EDPRSR_OFFSET = 0x314
+        TRACE_LAR_OFFSET = 0xFB0
+        TRACE_OSLAR_OFFSET = 0x300
+        TRACE_CTI_CTRL_OFFSET = 0x000
+        TRACE_CTI_OUTEN0_OFFSET = 0x0A0
+        TRACE_CTI_APPPULSE_OFFSET = 0x01C
+        TRACE_CTI_INTACK_OFFSET = 0x010
+        TRACE_DBG_EDITR_OFFSET = 0x84
+        TRACE_DBG_EDSCR_OFFSET = 0x88
+        TRACE_DBG_DTRTX_OFFSET = 0x8C
+        TRACE_DBG_DTRRX_OFFSET = 0x80
+        CTI_BASE = 0x0042_0000
+        DBG_BASE = 0x0041_0000
+
+        def initialize(options = {})
+          super
+          instantiate_registers(options)
+        end
+
+        def instantiate_registers(options)
+          add_reg(:trace_dbg_edprsr, DBG_BASE + TRACE_DBG_EDPRSR_OFFSET, size: 32)
+          add_reg(:trace_dbg_editr, DBG_BASE + TRACE_DBG_EDITR_OFFSET, size: 32)
+          add_reg(:trace_dbg_edscr, DBG_BASE + TRACE_DBG_EDSCR_OFFSET, size: 32)
+          add_reg(:trace_dbg_dtrtx, DBG_BASE + TRACE_DBG_DTRTX_OFFSET, size: 32)
+          add_reg(:trace_dbg_dtrrx, DBG_BASE + TRACE_DBG_DTRRX_OFFSET, size: 32)
+          add_reg(:trace_dbg_lar, DBG_BASE + TRACE_LAR_OFFSET, size: 32)
+          add_reg(:trace_dbg_oslar, DBG_BASE + TRACE_OSLAR_OFFSET, size: 32)
+          add_reg(:trace_cti_ctrl, CTI_BASE + TRACE_CTI_CTRL_OFFSET, size: 32)
+          add_reg(:trace_cti_outen0, CTI_BASE + TRACE_CTI_OUTEN0_OFFSET, size: 32)
+          add_reg(:trace_cti_outen1, CTI_BASE + TRACE_CTI_OUTEN0_OFFSET + 0x4, size: 32)
+          add_reg(:trace_cti_apppulse, CTI_BASE + TRACE_CTI_APPPULSE_OFFSET, size: 32)
+          add_reg(:trace_cti_intack, CTI_BASE + TRACE_CTI_INTACK_OFFSET, size: 32)
+          add_reg(:trace_cti_lar, CTI_BASE + TRACE_LAR_OFFSET, size: 32)
+        end
+      end
+    end
+  end
+end

data/lib/origen_arm/cores/cortexa/ca35/ca35_controller.rb

@@ -0,0 +1,57 @@
+module OrigenARM
+  module Cores
+    module CortexA
+      class CA35Controller < OrigenARM::Cores::BaseController
+        def initialize_core(pc:, release_core: false, **options)
+          halt_core!
+          set_pc!(pc)
+
+          if release_core
+            release_core!
+          end
+        end
+
+        def halt_core!
+          ss 'Halt core - channel 0'
+          reg(:trace_cti_lar).write!(0xC5AC_CE55)
+          reg(:trace_cti_ctrl).write!(0x1)
+          reg(:trace_cti_outen0).write!(0x1)
+          reg(:trace_cti_apppulse).write!(0x1)
+          tester.cycle(repeat: 10_000)
+
+          ss 'Check that the core is halted'
+          reg(:trace_dbg_edprsr).read!(0x10, mask: 0x0000_0010)
+
+          ss 'Acknowledge'
+          reg(:trace_cti_intack).write!(0x1)
+          tester.cycle(repeat: 100)
+
+          reg(:trace_dbg_lar).write!(0xC5AC_CE55)
+          reg(:trace_dbg_oslar).write!(0xABCD_1234)
+          tester.cycle(repeat: 100)
+        end
+
+        def release_core!
+          ss 'Release core - channel 2'
+          reg(:trace_cti_lar).write!(0xC5AC_CE55)
+          reg(:trace_cti_ctrl).write!(0x1)
+          reg(:trace_cti_outen1).write!(0x4)
+          reg(:trace_cti_apppulse).write!(0x4)
+          tester.cycle(repeat: 100)
+          ss 'Check that the core has been released'
+          reg(:trace_dbg_edprsr).read!(0x0, mask: 0x0000_0010)
+        end
+
+        def set_pc!(pc)
+          ss 'Move the PC'
+          reg(:trace_dbg_dtrtx).write!((pc >> 32) & 0xFFFF_FFFF)
+          reg(:trace_dbg_dtrrx).write!(pc & 0xFFFF_FFFF)
+          reg(:trace_dbg_editr).write!(0xD533_0401)
+          tester.cycle(repeat: 100)
+          reg(:trace_dbg_editr).write!(0xD51B_4521)
+          tester.cycle(repeat: 100)
+        end
+      end
+    end
+  end
+end

data/lib/origen_arm/cores/cortexm/cm33/cm33_controller.rb

@@ -16,10 +16,27 @@ module OrigenARM
         # @todo Implement lower and upper stack pointer limit setting.
         def initialize_core(pc:, sp:, release_core: false, sp_lower_limit: nil, sp_upper_limit: nil)
           enter_debug_mode
+
+          # clear_state
+          # clear_state
+
+          # ss 'Disable the MPU and the SAU'
+          # mem(0xE000_ED94).write!(0x0, force_arm_debug: true)
+          # mem(0xE000_EDD0).write!(0x0, force_arm_debug: true)
+
+          # ss 'Move the stack pointer limits'
+          # mem(0xE000_EDF8).write!(0x1400_6800, force_arm_debug: true)
+          # mem(0xE000_EDF4).write!(0x0001_0000 + 0x1C, force_arm_debug: true)
+
           set_sp(sp)
           set_pc(pc)
+
           # set_stack_limits(sp_lower_limit, sp_upper_limit) if (sp_lower_limit || sp_upper_limit)
           exit_debug_mode(release_core: release_core)
+
+          # reg(:aircr).bits(:vectkey).write(CM33::Registers::AIRCR_WRITE_KEY)
+          # reg(:aircr).bits(:sysresetreq).write(1)
+          # reg(:aircr).write!
         end
         alias_method :initialize_for_lre, :initialize_core
 
@@ -88,6 +105,17 @@ module OrigenARM
           end
         end
 
+        # def clear_state
+        #  pp("Clear the core's current state") do
+        #    reg(:aircr).bits(:vectkey).write(CM33::Registers::AIRCR_WRITE_KEY)
+        #    reg(:aircr).bits(:sysresetreq).write(1)
+        #    #reg(:aircr).bits(:vectclractive).write(1)
+        #    reg(:aircr).write!
+        #
+        #    tester.cycle(repeat: 1000)
+        #  end
+        # end
+
         # def set_stack_limits(lower_limit, upper_limits, stack: :msp, **options)
         # end
       end

metadata

@@ -1,14 +1,14 @@
 --- !ruby/object:Gem::Specification
 name: origen_arm
 version: !ruby/object:Gem::Version
-  version: 0.1.0
+  version: 0.1.1
 platform: ruby
 authors:
 - Corey Engelken
 autorequire: 
 bindir: bin
 cert_chain: []
-date: 2019-01-11 00:00:00.000000000 Z
+date: 2020-08-08 00:00:00.000000000 Z
 dependencies:
 - !ruby/object:Gem::Dependency
   name: origen
@@ -53,6 +53,8 @@ files:
 - lib/origen_arm/cores/base_core/core.rb
 - lib/origen_arm/cores/base_core/core_controller.rb
 - lib/origen_arm/cores/base_core/core_registers.rb
+- lib/origen_arm/cores/cortexa/ca35/ca35.rb
+- lib/origen_arm/cores/cortexa/ca35/ca35_controller.rb
 - lib/origen_arm/cores/cortexm/base_cortexm/cortexm.rb
 - lib/origen_arm/cores/cortexm/base_cortexm/cortexm_controller.rb
 - lib/origen_arm/cores/cortexm/base_cortexm/cortexm_registers.rb
@@ -85,7 +87,7 @@ required_rubygems_version: !ruby/object:Gem::Requirement
       version: 1.8.11
 requirements: []
 rubyforge_project: 
-rubygems_version: 2.7.7
+rubygems_version: 2.7.6
 signing_key: 
 specification_version: 4
 summary: Origen subblocks modeling ARM cores.