origen_ahb 0.2.0 → 0.2.1
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- checksums.yaml +4 -4
- data/config/version.rb +1 -1
- data/lib/origen_ahb_dev/block.rb +9 -11
- data/lib/origen_ahb_dev/dut.rb +35 -37
- data/lib/origen_ahb_dev/dut_controller.rb +111 -113
- metadata +1 -1
checksums.yaml
CHANGED
@@ -1,7 +1,7 @@
|
|
1
1
|
---
|
2
2
|
SHA1:
|
3
|
-
metadata.gz:
|
4
|
-
data.tar.gz:
|
3
|
+
metadata.gz: a4515cf6397b5d0bf520a4dcad7d07167151e727
|
4
|
+
data.tar.gz: d25cb4157e46aec01ac9fb62b0571ba20b4ab444
|
5
5
|
SHA512:
|
6
|
-
metadata.gz:
|
7
|
-
data.tar.gz:
|
6
|
+
metadata.gz: 022a0c856fadf02472d7d3c7a47d21b5a074cc3998959f39254a842ecf0fa44877ab6d7bee1ee70bbafdcdb03f6f3de96367429e3e3abb42e3781063832c64ab
|
7
|
+
data.tar.gz: 3b09984387e3aa68943c088bdd78882e79905e40567514ca7035d08c0041e3db492811e2b38fe139277955d0b147617f97aa0a921aba76956a8de8bd4bd6ef46
|
data/config/version.rb
CHANGED
data/lib/origen_ahb_dev/block.rb
CHANGED
@@ -1,16 +1,14 @@
|
|
1
|
-
module
|
2
|
-
|
3
|
-
|
4
|
-
include Origen::Model
|
1
|
+
module OrigenAhbDev
|
2
|
+
class BLOCK
|
3
|
+
include Origen::Model
|
5
4
|
|
6
|
-
|
7
|
-
|
8
|
-
|
5
|
+
def initialize(options = {})
|
6
|
+
instantiate_registers(options)
|
7
|
+
end
|
9
8
|
|
10
|
-
|
11
|
-
|
12
|
-
|
13
|
-
end
|
9
|
+
def instantiate_registers(options = {})
|
10
|
+
add_reg :control, 0x00, 32, data: { pos: 0, bits: 32 }
|
11
|
+
add_reg :status, 0x04, 32, data: { pos: 0, bits: 32 }
|
14
12
|
end
|
15
13
|
end
|
16
14
|
end
|
data/lib/origen_ahb_dev/dut.rb
CHANGED
@@ -1,46 +1,44 @@
|
|
1
|
-
module
|
2
|
-
|
3
|
-
|
4
|
-
|
5
|
-
include OrigenAhb
|
1
|
+
module OrigenAhbDev
|
2
|
+
class DUT
|
3
|
+
include Origen::TopLevel
|
4
|
+
include OrigenAhb
|
6
5
|
|
7
|
-
|
8
|
-
|
9
|
-
|
10
|
-
|
11
|
-
|
6
|
+
def initialize(options = {})
|
7
|
+
instantiate_pins(options)
|
8
|
+
instantiate_registers(options)
|
9
|
+
instantiate_sub_blocks(options)
|
10
|
+
end
|
12
11
|
|
13
|
-
|
14
|
-
|
15
|
-
|
16
|
-
|
17
|
-
|
18
|
-
|
19
|
-
|
12
|
+
def instantiate_pins(options = {})
|
13
|
+
# Standard DUT pins
|
14
|
+
add_pin :tclk
|
15
|
+
add_pin :tdi
|
16
|
+
add_pin :tdo
|
17
|
+
add_pin :tms
|
18
|
+
add_pin :resetb
|
20
19
|
|
21
|
-
|
22
|
-
|
23
|
-
|
24
|
-
|
25
|
-
|
26
|
-
|
27
|
-
|
28
|
-
|
29
|
-
|
20
|
+
# AHB Control Signals
|
21
|
+
add_pin :hclk
|
22
|
+
add_pin :hready
|
23
|
+
add_pin :hwrite
|
24
|
+
add_pin :htrans, size: 2
|
25
|
+
add_pin :hburst, size: 3
|
26
|
+
add_pin :hmastlock
|
27
|
+
add_pin :hsize, size: 3
|
28
|
+
add_pin :hprot, size: 3
|
30
29
|
|
31
|
-
|
32
|
-
|
33
|
-
|
34
|
-
|
35
|
-
|
30
|
+
# AHB Data Signals
|
31
|
+
add_pin :haddr, size: 32
|
32
|
+
add_pin :hwdata, size: 32
|
33
|
+
add_pin :hrdata, size: 32
|
34
|
+
end
|
36
35
|
|
37
|
-
|
38
|
-
|
39
|
-
|
36
|
+
def instantiate_registers(options = {})
|
37
|
+
add_reg :top_reg, 0x20000000, 32, data: { pos: 0, bits: 32 }
|
38
|
+
end
|
40
39
|
|
41
|
-
|
42
|
-
|
43
|
-
end
|
40
|
+
def instantiate_sub_blocks(options = {})
|
41
|
+
sub_block :block, class_name: 'OrigenAhbDev::BLOCK', base_address: 0x2200_0000
|
44
42
|
end
|
45
43
|
end
|
46
44
|
end
|
@@ -1,116 +1,114 @@
|
|
1
|
-
module
|
2
|
-
|
3
|
-
|
4
|
-
|
5
|
-
|
6
|
-
|
7
|
-
|
8
|
-
|
9
|
-
|
10
|
-
|
11
|
-
|
12
|
-
|
13
|
-
|
14
|
-
|
15
|
-
|
16
|
-
|
17
|
-
|
18
|
-
|
19
|
-
|
20
|
-
|
21
|
-
|
22
|
-
|
23
|
-
|
24
|
-
|
25
|
-
|
26
|
-
|
27
|
-
|
28
|
-
|
29
|
-
|
30
|
-
|
31
|
-
|
32
|
-
|
33
|
-
|
34
|
-
|
35
|
-
|
36
|
-
|
37
|
-
|
38
|
-
|
39
|
-
|
40
|
-
|
41
|
-
|
42
|
-
|
43
|
-
|
44
|
-
|
45
|
-
|
46
|
-
|
47
|
-
|
48
|
-
|
49
|
-
|
50
|
-
|
51
|
-
|
52
|
-
|
53
|
-
|
54
|
-
|
55
|
-
|
56
|
-
|
57
|
-
|
58
|
-
|
59
|
-
|
60
|
-
|
61
|
-
|
62
|
-
|
63
|
-
|
64
|
-
|
65
|
-
|
66
|
-
|
67
|
-
|
68
|
-
|
69
|
-
|
70
|
-
|
71
|
-
|
72
|
-
|
73
|
-
|
74
|
-
|
75
|
-
|
76
|
-
|
77
|
-
|
78
|
-
|
79
|
-
|
80
|
-
|
81
|
-
|
82
|
-
|
83
|
-
|
84
|
-
|
85
|
-
|
86
|
-
|
87
|
-
|
88
|
-
|
89
|
-
|
90
|
-
|
91
|
-
|
92
|
-
|
93
|
-
|
94
|
-
|
95
|
-
|
96
|
-
|
97
|
-
|
98
|
-
|
99
|
-
|
100
|
-
|
101
|
-
|
102
|
-
|
103
|
-
|
104
|
-
|
105
|
-
|
106
|
-
|
107
|
-
|
108
|
-
|
109
|
-
|
110
|
-
|
111
|
-
|
112
|
-
tester.cycle
|
113
|
-
end
|
1
|
+
module OrigenAhbDev
|
2
|
+
class DUTController
|
3
|
+
include Origen::Controller
|
4
|
+
|
5
|
+
def startup(options = {})
|
6
|
+
tester.set_timeset('ahb', 40)
|
7
|
+
|
8
|
+
init_pins # Give pattern a known start up
|
9
|
+
|
10
|
+
# Do some startup stuff here
|
11
|
+
pin(:resetb).drive(0)
|
12
|
+
tester.wait time_in_ns: 250
|
13
|
+
pin(:resetb).drive(1)
|
14
|
+
end
|
15
|
+
|
16
|
+
def shutdown(options = {})
|
17
|
+
# Shut everything down
|
18
|
+
tester.wait time_in_ns: 250
|
19
|
+
pin(:resetb).drive(0)
|
20
|
+
|
21
|
+
cleanup_pins # Give patterns a known exit condition
|
22
|
+
end
|
23
|
+
|
24
|
+
def init_pins
|
25
|
+
pin(:resetb).drive(0)
|
26
|
+
pin(:tclk).drive(0)
|
27
|
+
pin(:tdi).drive(0)
|
28
|
+
pin(:tms).drive(0)
|
29
|
+
pin(:tdo).dont_care
|
30
|
+
end
|
31
|
+
|
32
|
+
def cleanup_pins
|
33
|
+
pin(:resetb).drive(0)
|
34
|
+
pin(:tclk).drive(0)
|
35
|
+
pin(:tdi).drive(0)
|
36
|
+
pin(:tms).drive(0)
|
37
|
+
pin(:tdo).dont_care
|
38
|
+
end
|
39
|
+
|
40
|
+
def write_register(reg, options = {})
|
41
|
+
ahb.write_register(reg, options)
|
42
|
+
end
|
43
|
+
|
44
|
+
def read_register(reg, options = {})
|
45
|
+
ahb.read_register(reg, options)
|
46
|
+
end
|
47
|
+
|
48
|
+
def ahb_trans(options = {})
|
49
|
+
pin(:hclk).drive(0)
|
50
|
+
pins(:htrans).drive(0)
|
51
|
+
pin(:hwrite).drive(0)
|
52
|
+
pin(:hsize).drive(0)
|
53
|
+
pin(:hburst).drive(0)
|
54
|
+
pin(:hmastlock).drive(0)
|
55
|
+
pin(:hprot).drive(0)
|
56
|
+
pin(:hready).dont_care
|
57
|
+
pins(:haddr).dont_care
|
58
|
+
pins(:hwdata).dont_care
|
59
|
+
pins(:hrdata).dont_care
|
60
|
+
tester.cycle
|
61
|
+
|
62
|
+
# Address Phase
|
63
|
+
#
|
64
|
+
# Master drives the address and control signals onto bus after the rising edge of HCLK
|
65
|
+
pin(:hclk).drive(1)
|
66
|
+
tester.cycle
|
67
|
+
|
68
|
+
pin(:htrans).drive(0b00)
|
69
|
+
pin(:hwrite).drive(options[:hwrite])
|
70
|
+
pin(:hsize).drive(options[:hsize])
|
71
|
+
pin(:hburst).drive(options[:hburst])
|
72
|
+
pin(:hmastlock).drive(options[:hmastlock])
|
73
|
+
pin(:hprot).drive(options[:hprot])
|
74
|
+
pins(:haddr).drive(options[:haddr])
|
75
|
+
|
76
|
+
pin(:hclk).drive(0)
|
77
|
+
tester.cycle
|
78
|
+
|
79
|
+
# Data Phase
|
80
|
+
#
|
81
|
+
# Slave samples the address and control information on the next rising edge of HCLK
|
82
|
+
pin(:hclk).drive(1)
|
83
|
+
tester.cycle
|
84
|
+
|
85
|
+
pin(:hclk).drive(0)
|
86
|
+
pin(:hready).compare(1)
|
87
|
+
pins(:hwdata).drive(options[:hdata]) if options[:hwrite] == 1
|
88
|
+
tester.cycle
|
89
|
+
|
90
|
+
pin(:hclk).drive(1)
|
91
|
+
pins(:hrdata).assert(options[:hdata]) if options[:hwrite] == 0
|
92
|
+
tester.cycle
|
93
|
+
|
94
|
+
pin(:hclk).drive(0)
|
95
|
+
tester.cycle
|
96
|
+
|
97
|
+
pin(:hclk).drive(1)
|
98
|
+
pins(:htrans).drive(0)
|
99
|
+
pin(:hwrite).drive(0)
|
100
|
+
pin(:hsize).drive(0)
|
101
|
+
pin(:hburst).drive(0)
|
102
|
+
pin(:hmastlock).drive(0)
|
103
|
+
pin(:hprot).drive(0)
|
104
|
+
pin(:hready).dont_care
|
105
|
+
pins(:haddr).dont_care
|
106
|
+
pins(:hwdata).dont_care
|
107
|
+
pins(:hrdata).dont_care
|
108
|
+
tester.cycle
|
109
|
+
|
110
|
+
pin(:hclk).drive(0)
|
111
|
+
tester.cycle
|
114
112
|
end
|
115
113
|
end
|
116
114
|
end
|