origen_ahb 0.2.0 → 0.2.1

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data/config/version.rb CHANGED
@@ -1,7 +1,7 @@
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  module OrigenAhb
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  MAJOR = 0
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  MINOR = 2
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- BUGFIX = 0
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+ BUGFIX = 1
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  DEV = nil
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  VERSION = [MAJOR, MINOR, BUGFIX].join(".") + (DEV ? ".pre#{DEV}" : '')
@@ -1,16 +1,14 @@
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- module OrigenAhb
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- module Test
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- class BLOCK
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- include Origen::Model
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+ module OrigenAhbDev
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+ class BLOCK
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+ include Origen::Model
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- def initialize(options = {})
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- instantiate_registers(options)
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- end
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+ def initialize(options = {})
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+ instantiate_registers(options)
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+ end
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- def instantiate_registers(options = {})
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- add_reg :control, 0x00, 32, data: { pos: 0, bits: 32 }
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- add_reg :status, 0x04, 32, data: { pos: 0, bits: 32 }
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- end
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+ def instantiate_registers(options = {})
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+ add_reg :control, 0x00, 32, data: { pos: 0, bits: 32 }
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+ add_reg :status, 0x04, 32, data: { pos: 0, bits: 32 }
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  end
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  end
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  end
@@ -1,46 +1,44 @@
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- module OrigenAhb
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- module Test
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- class DUT
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- include Origen::TopLevel
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- include OrigenAhb
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+ module OrigenAhbDev
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+ class DUT
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+ include Origen::TopLevel
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+ include OrigenAhb
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- def initialize(options = {})
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- instantiate_pins(options)
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- instantiate_registers(options)
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- instantiate_sub_blocks(options)
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- end
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+ def initialize(options = {})
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+ instantiate_pins(options)
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+ instantiate_registers(options)
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+ instantiate_sub_blocks(options)
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+ end
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- def instantiate_pins(options = {})
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- # Standard DUT pins
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- add_pin :tclk
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- add_pin :tdi
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- add_pin :tdo
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- add_pin :tms
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- add_pin :resetb
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+ def instantiate_pins(options = {})
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+ # Standard DUT pins
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+ add_pin :tclk
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+ add_pin :tdi
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+ add_pin :tdo
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+ add_pin :tms
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+ add_pin :resetb
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- # AHB Control Signals
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- add_pin :hclk
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- add_pin :hready
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- add_pin :hwrite
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- add_pin :htrans, size: 2
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- add_pin :hburst, size: 3
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- add_pin :hmastlock
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- add_pin :hsize, size: 3
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- add_pin :hprot, size: 3
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+ # AHB Control Signals
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+ add_pin :hclk
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+ add_pin :hready
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+ add_pin :hwrite
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+ add_pin :htrans, size: 2
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+ add_pin :hburst, size: 3
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+ add_pin :hmastlock
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+ add_pin :hsize, size: 3
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+ add_pin :hprot, size: 3
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- # AHB Data Signals
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- add_pin :haddr, size: 32
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- add_pin :hwdata, size: 32
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- add_pin :hrdata, size: 32
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- end
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+ # AHB Data Signals
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+ add_pin :haddr, size: 32
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+ add_pin :hwdata, size: 32
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+ add_pin :hrdata, size: 32
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+ end
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- def instantiate_registers(options = {})
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- add_reg :top_reg, 0x20000000, 32, data: { pos: 0, bits: 32 }
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- end
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+ def instantiate_registers(options = {})
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+ add_reg :top_reg, 0x20000000, 32, data: { pos: 0, bits: 32 }
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+ end
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- def instantiate_sub_blocks(options = {})
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- sub_block :block, class_name: 'OrigenAhb::Test::BLOCK', base_address: 0x2200_0000
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- end
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+ def instantiate_sub_blocks(options = {})
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+ sub_block :block, class_name: 'OrigenAhbDev::BLOCK', base_address: 0x2200_0000
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  end
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  end
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  end
@@ -1,116 +1,114 @@
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- module OrigenAhb
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- module Test
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- class DUTController
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- include Origen::Controller
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-
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- def startup(options = {})
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- tester.set_timeset('ahb', 40)
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-
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- init_pins # Give pattern a known start up
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-
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- # Do some startup stuff here
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- pin(:resetb).drive(0)
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- tester.wait time_in_ns: 250
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- pin(:resetb).drive(1)
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- end
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-
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- def shutdown(options = {})
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- # Shut everything down
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- tester.wait time_in_ns: 250
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- pin(:resetb).drive(0)
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-
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- cleanup_pins # Give patterns a known exit condition
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- end
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-
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- def init_pins
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- pin(:resetb).drive(0)
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- pin(:tclk).drive(0)
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- pin(:tdi).drive(0)
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- pin(:tms).drive(0)
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- pin(:tdo).dont_care
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- end
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-
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- def cleanup_pins
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- pin(:resetb).drive(0)
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- pin(:tclk).drive(0)
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- pin(:tdi).drive(0)
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- pin(:tms).drive(0)
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- pin(:tdo).dont_care
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- end
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-
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- def write_register(reg, options = {})
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- ahb.write_register(reg, options)
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- end
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-
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- def read_register(reg, options = {})
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- ahb.read_register(reg, options)
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- end
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-
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- def ahb_trans(options = {})
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- pin(:hclk).drive(0)
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- pins(:htrans).drive(0)
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- pin(:hwrite).drive(0)
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- pin(:hsize).drive(0)
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- pin(:hburst).drive(0)
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- pin(:hmastlock).drive(0)
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- pin(:hprot).drive(0)
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- pin(:hready).dont_care
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- pins(:haddr).dont_care
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- pins(:hwdata).dont_care
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- pins(:hrdata).dont_care
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- tester.cycle
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-
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- # Address Phase
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- #
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- # Master drives the address and control signals onto bus after the rising edge of HCLK
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- pin(:hclk).drive(1)
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- tester.cycle
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-
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- pin(:htrans).drive(0b00)
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- pin(:hwrite).drive(options[:hwrite])
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- pin(:hsize).drive(options[:hsize])
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- pin(:hburst).drive(options[:hburst])
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- pin(:hmastlock).drive(options[:hmastlock])
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- pin(:hprot).drive(options[:hprot])
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- pins(:haddr).drive(options[:haddr])
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-
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- pin(:hclk).drive(0)
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- tester.cycle
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-
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- # Data Phase
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- #
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- # Slave samples the address and control information on the next rising edge of HCLK
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- pin(:hclk).drive(1)
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- tester.cycle
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-
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- pin(:hclk).drive(0)
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- pin(:hready).compare(1)
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- pins(:hwdata).drive(options[:hdata]) if options[:hwrite] == 1
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- tester.cycle
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-
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- pin(:hclk).drive(1)
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- pins(:hrdata).assert(options[:hdata]) if options[:hwrite] == 0
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- tester.cycle
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-
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- pin(:hclk).drive(0)
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- tester.cycle
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-
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- pin(:hclk).drive(1)
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- pins(:htrans).drive(0)
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- pin(:hwrite).drive(0)
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- pin(:hsize).drive(0)
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- pin(:hburst).drive(0)
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- pin(:hmastlock).drive(0)
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- pin(:hprot).drive(0)
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- pin(:hready).dont_care
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- pins(:haddr).dont_care
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- pins(:hwdata).dont_care
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- pins(:hrdata).dont_care
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- tester.cycle
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-
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- pin(:hclk).drive(0)
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- tester.cycle
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- end
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+ module OrigenAhbDev
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+ class DUTController
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+ include Origen::Controller
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+
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+ def startup(options = {})
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+ tester.set_timeset('ahb', 40)
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+
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+ init_pins # Give pattern a known start up
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+
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+ # Do some startup stuff here
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+ pin(:resetb).drive(0)
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+ tester.wait time_in_ns: 250
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+ pin(:resetb).drive(1)
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+ end
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+
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+ def shutdown(options = {})
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+ # Shut everything down
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+ tester.wait time_in_ns: 250
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+ pin(:resetb).drive(0)
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+
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+ cleanup_pins # Give patterns a known exit condition
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+ end
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+
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+ def init_pins
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+ pin(:resetb).drive(0)
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+ pin(:tclk).drive(0)
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+ pin(:tdi).drive(0)
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+ pin(:tms).drive(0)
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+ pin(:tdo).dont_care
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+ end
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+
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+ def cleanup_pins
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+ pin(:resetb).drive(0)
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+ pin(:tclk).drive(0)
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+ pin(:tdi).drive(0)
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+ pin(:tms).drive(0)
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+ pin(:tdo).dont_care
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+ end
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+
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+ def write_register(reg, options = {})
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+ ahb.write_register(reg, options)
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+ end
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+
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+ def read_register(reg, options = {})
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+ ahb.read_register(reg, options)
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+ end
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+
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+ def ahb_trans(options = {})
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+ pin(:hclk).drive(0)
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+ pins(:htrans).drive(0)
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+ pin(:hwrite).drive(0)
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+ pin(:hsize).drive(0)
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+ pin(:hburst).drive(0)
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+ pin(:hmastlock).drive(0)
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+ pin(:hprot).drive(0)
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+ pin(:hready).dont_care
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+ pins(:haddr).dont_care
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+ pins(:hwdata).dont_care
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+ pins(:hrdata).dont_care
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+ tester.cycle
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+
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+ # Address Phase
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+ #
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+ # Master drives the address and control signals onto bus after the rising edge of HCLK
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+ pin(:hclk).drive(1)
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+ tester.cycle
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+
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+ pin(:htrans).drive(0b00)
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+ pin(:hwrite).drive(options[:hwrite])
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+ pin(:hsize).drive(options[:hsize])
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+ pin(:hburst).drive(options[:hburst])
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+ pin(:hmastlock).drive(options[:hmastlock])
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+ pin(:hprot).drive(options[:hprot])
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+ pins(:haddr).drive(options[:haddr])
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+
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+ pin(:hclk).drive(0)
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+ tester.cycle
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+
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+ # Data Phase
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+ #
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+ # Slave samples the address and control information on the next rising edge of HCLK
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+ pin(:hclk).drive(1)
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+ tester.cycle
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+
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+ pin(:hclk).drive(0)
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+ pin(:hready).compare(1)
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+ pins(:hwdata).drive(options[:hdata]) if options[:hwrite] == 1
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+ tester.cycle
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+
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+ pin(:hclk).drive(1)
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+ pins(:hrdata).assert(options[:hdata]) if options[:hwrite] == 0
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+ tester.cycle
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+
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+ pin(:hclk).drive(0)
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+ tester.cycle
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+
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+ pin(:hclk).drive(1)
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+ pins(:htrans).drive(0)
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+ pin(:hwrite).drive(0)
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+ pin(:hsize).drive(0)
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+ pin(:hburst).drive(0)
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+ pin(:hmastlock).drive(0)
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+ pin(:hprot).drive(0)
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+ pin(:hready).dont_care
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+ pins(:haddr).dont_care
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+ pins(:hwdata).dont_care
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+ pins(:hrdata).dont_care
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+ tester.cycle
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+
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+ pin(:hclk).drive(0)
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+ tester.cycle
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  end
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  end
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  end
metadata CHANGED
@@ -1,7 +1,7 @@
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  --- !ruby/object:Gem::Specification
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  name: origen_ahb
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  version: !ruby/object:Gem::Version
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- version: 0.2.0
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+ version: 0.2.1
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  platform: ruby
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  authors:
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  - Chris P Nappi