logicuit 0.1.5 → 0.2.0

checksums.yaml

@@ -1,7 +1,7 @@
 ---
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data/.rubocop.yml

@@ -8,6 +8,17 @@ Style/StringLiterals:
 Style/StringLiteralsInInterpolation:
   EnforcedStyle: double_quotes
 
-require:
+Layout/LineLength:
+  Enabled: false
+
+Style/NumericPredicate:
+  Enabled: false
+
+Metrics:
+  Enabled: false
+
+plugins:
   - rubocop-minitest
+
+require:
   - rubocop-rake

data/README.md

@@ -23,7 +23,7 @@ This is the code to create a Multiplexer with 2 inputs and 1 output:
 ```
 require 'logicuit'
 
-class Multiplexer2To1 < Logicuit::Base
+class Multiplexer2to1 < Logicuit::Base
   tag :MY_MUX
 
   diagram <<~DIAGRAM

data/lib/logicuit/base.rb

@@ -3,7 +3,7 @@
 # Logicuit module
 module Logicuit
   # base class for all gates and circuits
-  class Base # rubocop:disable Metrics/ClassLength
+  class Base
     def self.tag(*tags)
       tags.each do |tag|
         registry[tag] = self
@@ -20,21 +20,26 @@ module Logicuit
       @input_targets = []
       @output_targets = []
       @clock = false
+      @components = []
       define_inputs(*args) if respond_to?(:define_inputs)
       define_outputs if respond_to?(:define_outputs)
       assembling if respond_to?(:assembling)
       evaluate if respond_to?(:evaluate)
     end
 
-    attr_reader :input_targets, :output_targets, :clock
+    def evaluate(*args); end
 
-    def self.define_inputs(*args, **kwargs) # rubocop:disable Metrics/MethodLength,Metrics/AbcSize
+    attr_reader :input_targets, :output_targets, :clock, :components
+
+    def self.define_inputs(*args, **kwargs)
+      # define getter methods for inputs
       args.each do |input|
         define_method(input) do
           instance_variable_get("@#{input}")
         end
       end
 
+      # define initializer for inputs
       define_method(:define_inputs) do |*instance_method_args|
         instance_variable_set("@clock", true) if kwargs&.key?(:clock)
         args.each_with_index do |input, index|
@@ -45,15 +50,31 @@ module Logicuit
         end
         Signals::Clock.on_tick << self if clock
       end
+
+      # define bulk_setter for inputs
+      define_method(:bulk_set) do |str|
+        args.zip(str.gsub(/\s/, "").split("")).each do |input, value|
+          next if value.nil?
+
+          signal = send(input)
+          if value == "1"
+            signal.on
+          else
+            signal.off
+          end
+        end
+      end
     end
 
-    def self.define_outputs(*args, **kwargs) # rubocop:disable Metrics/MethodLength,Metrics/AbcSize
+    def self.define_outputs(*args, **kwargs)
+      # define getter methods for outputs
       (args + kwargs.keys).each do |output|
         define_method(output) do
           instance_variable_get("@#{output}")
         end
       end
 
+      # define initializer for outputs
       define_method(:define_outputs) do
         (args + kwargs.keys).each do |output|
           instance_variable_set("@#{output}", Signals::Signal.new(false))
@@ -61,12 +82,20 @@ module Logicuit
         end
       end
 
-      define_method(:evaluate) do
+      # define evaluate method
+      return if kwargs.empty?
+
+      define_method(:evaluate) do |*override_args|
         kwargs.each do |output, evaluator|
           signal = instance_variable_get("@#{output}")
-          if evaluator.call(*@input_targets.map do |input|
-            instance_variable_get("@#{input}").current
-          end)
+          e_args = if override_args.empty?
+                     @input_targets.map do |input|
+                       instance_variable_get("@#{input}").current
+                     end
+                   else
+                     override_args
+                   end
+          if evaluator.call(*e_args)
             signal.on
           else
             signal.off
@@ -77,21 +106,28 @@ module Logicuit
 
     def self.assembling
       define_method(:assembling) do
-        yield(*(@input_targets + @output_targets).map { |target| instance_variable_get("@#{target}") })
+        (yield(*(@input_targets + @output_targets).map do |target|
+          instance_variable_get("@#{target}")
+        end) || []).each do |component|
+          @components << component
+        end
       end
     end
 
     def self.diagram(source)
       define_method(:to_s) do
-        (@input_targets + @output_targets).reduce(source) do |result, input|
+        source_ = @input_targets.reduce(source) do |result, input|
           result.gsub(/\(#{input}\)/i, "(#{instance_variable_get("@#{input}")})#{"-" * (input.size - 1)}")
         end
+        @output_targets.reduce(source_) do |result, output|
+          result.gsub(/\(#{output}\)/i, "#{"-" * (output.size - 1)}(#{instance_variable_get("@#{output}")})")
+        end
       end
     end
 
-    def self.truth_table(source) # rubocop:disable Metrics/AbcSize,Metrics/CyclomaticComplexity,Metrics/MethodLength,Metrics/PerceivedComplexity
-      define_method(:truth_table) do # rubocop:disable Metrics/AbcSize,Metrics/CyclomaticComplexity,Metrics/MethodLength,Metrics/PerceivedComplexity,Metrics/BlockLength
-        rows = source.strip.split("\n")
+    def self.truth_table(source)
+      define_method(:truth_table) do
+        rows = source.strip.split("\n").map { |row| row.gsub(/#.*$/, "") }
         headers = rows.shift.split("|").map(&:strip).reject(&:empty?).map(&:downcase).map(&:to_sym)
         rows.shift # devide line
         table = rows.map do |row|
@@ -106,15 +142,17 @@ module Logicuit
             when "0"
               false
             else
-              raise "Invalid value in truth table: #{v}"
+              raise "Invalid value in truth table: #{v}" unless headers.include?(v.to_sym)
+
+              [:ref, v.to_sym]
             end
           end
         end.select do |values| # rubocop:disable Style/MultilineBlockChain
           headers.size == values.size
         end.map do |values| # rubocop:disable Style/MultilineBlockChain
           array = [values]
-          while array.any? { |values| values.any? { |v| v == :any } }
-            target_index = array.find_index { |values| values.any? { |v| v == :any } }
+          while array.any? { it.any? { |v| v == :any } }
+            target_index = array.find_index { it.any? { |v| v == :any } }
             target = array[target_index]
             prop_index = target.find_index { |v| v == :any }
             array.delete_at(target_index)
@@ -133,22 +171,26 @@ module Logicuit
     end
   end
 
-  def self.run(sym) # rubocop:disable Metrics/AbcSize,Metrics/MethodLength,Metrics/PerceivedComplexity
+  def self.run(sym, hz: 1, noclear: false) # rubocop:disable Naming/MethodParameterName
     circuit = Base.registry[sym.upcase.to_sym].new
 
     render = lambda {
-      system("clear")
+      system("clear") unless noclear
       puts circuit
       puts
       puts "tick: #{Signals::Clock.tick_count}" if circuit.clock
-      puts "input: #{circuit.input_targets.join ","}?" if circuit.input_targets.any?
+      if circuit.respond_to?(:instructions)
+        puts "instructions: #{circuit.instructions.join "|"}"
+      elsif circuit.input_targets.any?
+        puts "input: #{circuit.input_targets.join ","}?"
+      end
     }
 
-    if circuit.clock
+    if circuit.clock && hz.nonzero?
       Thread.new do
         loop do
           render.call
-          sleep 1
+          sleep 1.0 / hz
           Signals::Clock.tick
         end
       end
@@ -156,17 +198,28 @@ module Logicuit
       render.call
     end
 
-    while (input = gets)
-      key = input.chomp.to_sym
-      next unless circuit.respond_to? key
-
-      signal = circuit.send(key)
-      if signal.current
-        signal.off
+    while (input = gets.chomp)
+      if circuit.respond_to?(:execute) && circuit.execute(input)
+        Signals::Clock.tick
+        render.call # rubocop:disable Style/IdenticalConditionalBranches
       else
-        signal.on
+        key = input.to_sym
+        unless circuit.respond_to? key
+          if circuit.clock && hz.zero?
+            Signals::Clock.tick
+            render.call
+          end
+          next
+        end
+
+        signal = circuit.send(key)
+        if signal.current
+          signal.off
+        else
+          signal.on
+        end
+        render.call # rubocop:disable Style/IdenticalConditionalBranches
       end
-      render.call
     end
   end
 end

data/lib/logicuit/circuits/combinational/decoder.rb

@@ -0,0 +1,39 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # Decoder class
+      class Decoder < Base
+        tag :DEC
+
+        define_inputs :op3, :op2, :op1, :op0, :c_flag
+
+        define_outputs sel_b: ->(_, _, op1, _, _) { op1 },
+                       sel_a: ->(op3, _, _, op0, _) { op3 || op0 },
+                       ld0: ->(op3, op2, _, _, _) { op3 || op2 },
+                       ld1: ->(op3, op2, _, _, _) { op3 || !op2 },
+                       ld2: ->(op3, op2, _, _, _) { !op3 || op2 },
+                       ld3: ->(op3, op2, _, op0, c_flag) { !op3 || !op2 || (!op0 && c_flag) }
+
+        truth_table <<~TRUTH_TABLE
+          | OP3 | OP2 | OP1 | OP0 | C_FLAG | SEL_B | SEL_A | LD0 | LD1 | LD2 | LD3 |
+          | --- | --- | --- | --- | ------ | ----- | ----- | --- | --- | --- | --- |
+          |   0 |   0 |   0 |   0 |      x |     0 |     0 |   0 |   1 |   1 |   1 | # ADD A,Im
+          |   0 |   0 |   0 |   1 |      x |     0 |     1 |   0 |   1 |   1 |   1 | # MOV A,B
+          |   0 |   0 |   1 |   0 |      x |     1 |     0 |   0 |   1 |   1 |   1 | # IN  A
+          |   0 |   0 |   1 |   1 |      x |     1 |     1 |   0 |   1 |   1 |   1 | # MOV A,Im
+          |   0 |   1 |   0 |   0 |      x |     0 |     0 |   1 |   0 |   1 |   1 | # MOV B,A
+          |   0 |   1 |   0 |   1 |      x |     0 |     1 |   1 |   0 |   1 |   1 | # ADD B,Im
+          |   0 |   1 |   1 |   0 |      x |     1 |     0 |   1 |   0 |   1 |   1 | # IN  B
+          |   0 |   1 |   1 |   1 |      x |     1 |     1 |   1 |   0 |   1 |   1 | # MOV B,Im
+          |   1 |   0 |   0 |   1 |      x |     0 |     1 |   1 |   1 |   0 |   1 | # OUT B
+          |   1 |   0 |   1 |   1 |      x |     1 |     1 |   1 |   1 |   0 |   1 | # OUT Im
+          |   1 |   1 |   1 |   0 |      0 |     1 |     1 |   1 |   1 |   1 |   0 | # JNC(C=0)
+          |   1 |   1 |   1 |   0 |      1 |     1 |     1 |   1 |   1 |   1 |   1 | # JNC(C=1)
+          |   1 |   1 |   1 |   1 |      x |     1 |     1 |   1 |   1 |   1 |   0 | # JMP
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/combinational/full_adder.rb

@@ -0,0 +1,68 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # FullAdder class
+      class FullAdder < Base
+        tag :FADD
+
+        diagram <<~DIAGRAM
+          (Cin)---+-|NOT|-----+
+                  |           |
+          (A)---+---|NOT|---+ |
+                | |         | |
+          (B)-+-----|NOT|-+ | +-|
+              | | |       | +---|AND|---+
+              +-----------------|       |
+              | | |       | | |         +-|
+              | | |       | | +-|         |
+              | +---------------|AND|-----|
+              | | |       +-----|         |
+              | | |       | | |           |OR|-(S)
+              | | +-------------|         |
+              | | |       | +---|AND|-----|
+              | | |       +-----|         |
+              | | |       | | |         +-|
+              | | +-------------|       |
+              | +---------------|AND|---+
+              +-----------------|
+              | | |       | | |
+              | | |       | | +-|
+              | +---------------|AND|---+
+              +-----------------|       |
+              | | |       | |           +-|
+              | | +-------------|         |
+              | | |       | +---|AND|-----|
+              +-----------------|         |
+              | | |       |               |OR|-(C)
+              | | +-------------|         |
+              | +---------------|AND|-----|
+              | | |       +-----|         |
+              | | |                     +-|
+              | | +-------------|       |
+              | +---------------|AND|---+
+              +-----------------|
+        DIAGRAM
+
+        define_inputs :cin, :a, :b
+
+        define_outputs s: ->(cin, a, b) { (!cin && !a && b) || (!cin && a && !b) || (cin && !a && !b) || (cin && a && b) },
+                       c: ->(cin, a, b) { (!cin && a && b) || (cin && !a && b) || (cin && a && !b) || (cin && a && b) }
+
+        truth_table <<~TRUTH_TABLE
+          | Cin | A | B | C | S |
+          | --- | - | - | - | - |
+          |   0 | 0 | 0 | 0 | 0 |
+          |   0 | 0 | 1 | 0 | 1 |
+          |   0 | 1 | 0 | 0 | 1 |
+          |   0 | 1 | 1 | 1 | 0 |
+          |   1 | 0 | 0 | 0 | 1 |
+          |   1 | 0 | 1 | 1 | 0 |
+          |   1 | 1 | 0 | 1 | 0 |
+          |   1 | 1 | 1 | 1 | 1 |
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/combinational/full_adder_4bit.rb

@@ -0,0 +1,53 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Combinational
+      # FullAdder class
+      class FullAdder4bit < Base
+        tag :FADD4
+
+        diagram <<~DIAGRAM
+          (Cin)-|    |--(S0)
+          (A0)--|FADD|
+          (B0)--|    |--+
+                        |
+             +----------+
+             |
+             +--|    |--(S1)
+          (A1)--|FADD|
+          (B1)--|    |--+
+                        |
+             +----------+
+             |
+             +--|    |--(S2)
+          (A2)--|FADD|
+          (B2)--|    |--+
+                        |
+             +----------+
+             |
+             +--|    |--(S3)
+          (A3)--|FADD|
+          (B3)--|    |---(C)
+
+        DIAGRAM
+
+        define_inputs :cin, :a0, :b0, :a1, :b1, :a2, :b2, :a3, :b3
+
+        define_outputs :s0, :s1, :s2, :s3, :c
+
+        assembling do |cin, a0, b0, a1, b1, a2, b2, a3, b3, s0, s1, s2, s3, cout|
+          [[a0, b0, s0], [a1, b1, s1], [a2, b2, s2], [a3, b3, s3]].reduce(cin) do |c, sigs|
+            a, b, s = sigs
+            full_addr = Combinational::FullAdder.new
+            c >> full_addr.cin
+            a >> full_addr.a
+            b >> full_addr.b
+            full_addr.s >> s
+            full_addr.c
+          end >> cout
+        end
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/combinational/half_adder.rb

@@ -10,7 +10,7 @@ module Logicuit
         diagram <<~DIAGRAM
           (A)---+-|
                 | |XOR|-(S)
-          (B)-+---+
+          (B)-+---|
               | |
               | +-|
               |   |AND|-(C)

data/lib/logicuit/circuits/combinational/{multiplexer2to1.rb → multiplexer_2to1.rb}

@@ -4,7 +4,7 @@ module Logicuit
   module Circuits
     module Combinational
       # A Multiplexer with 2 inputs and 1 output
-      class Multiplexer2To1 < Base
+      class Multiplexer2to1 < Base
         tag :MUX, :MUX2, :MUX2to1
 
         diagram <<~DIAGRAM

data/lib/logicuit/circuits/combinational/{multiplexer4to1.rb → multiplexer_4to1.rb}

@@ -4,7 +4,7 @@ module Logicuit
   module Circuits
     module Combinational
       # A Multiplexer with 4 inputs and 1 output
-      class Multiplexer4To1 < Base
+      class Multiplexer4to1 < Base
         tag :MUX4, :MUX4TO1
 
         diagram <<~DIAGRAM

data/lib/logicuit/circuits/rom/timer.rb

@@ -0,0 +1,59 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Rom
+      # TImer
+      class Timer < Base
+        define_inputs :a3, :a2, :a1, :a0
+
+        define_outputs :d7, :d6, :d5, :d4, :d3, :d2, :d1, :d0
+
+        def evaluate
+          output = case "#{a3}#{a2}#{a1}#{a0}"
+                   in "0000" then "10110111"
+                   in "0001" then "00000001"
+                   in "0010" then "11100001"
+                   in "0011" then "00000001"
+                   in "0100" then "11100011"
+                   in "0101" then "10110110"
+                   in "0110" then "00000001"
+                   in "0111" then "11100110"
+                   in "1000" then "00000001"
+                   in "1001" then "11101000"
+                   in "1010" then "10110000"
+                   in "1011" then "10110100"
+                   in "1100" then "00000001"
+                   in "1101" then "11101010"
+                   in "1110" then "10111000"
+                   in "1111" then "11111111"
+                   end
+          output.split("").zip([d7, d6, d5, d4, d3, d2, d1, d0]).each do |v, o|
+            v == "1" ? o.on : o.off
+          end
+        end
+
+        truth_table <<~TRUTH_TABLE
+          | A3 | A2 | A1 | A0 | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
+          | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- | -- |
+          |  0 |  0 |  0 |  0 |  1 |  0 |  1 |  1 |  0 |  1 |  1 |  1 | # OUT 0111
+          |  0 |  0 |  0 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  0 |  0 |  1 |  0 |  1 |  1 |  1 |  0 |  0 |  0 |  0 |  1 | # JNC 0001
+          |  0 |  0 |  1 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  0 |  1 |  0 |  0 |  1 |  1 |  1 |  0 |  0 |  0 |  1 |  1 | # JNC 0011
+          |  0 |  1 |  0 |  1 |  1 |  0 |  1 |  1 |  0 |  1 |  1 |  0 | # OUT 0110
+          |  0 |  1 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  0 |  1 |  1 |  1 |  1 |  1 |  1 |  0 |  0 |  1 |  1 |  0 | # JNC 0110
+          |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  1 |  0 |  0 |  1 |  1 |  1 |  1 |  0 |  1 |  0 |  0 |  0 | # JNC 1000
+          |  1 |  0 |  1 |  0 |  1 |  0 |  1 |  1 |  0 |  0 |  0 |  0 | # OUT 0000
+          |  1 |  0 |  1 |  1 |  1 |  0 |  1 |  1 |  0 |  1 |  0 |  0 | # OUT 0100
+          |  1 |  1 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  0 |  1 | # ADD A,0001
+          |  1 |  1 |  0 |  1 |  1 |  1 |  1 |  0 |  1 |  0 |  1 |  0 | # JNC 1010
+          |  1 |  1 |  1 |  0 |  1 |  0 |  1 |  1 |  1 |  0 |  0 |  0 | # OUT 1000
+          |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 |  1 | # JMP 1111
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/sequential/program_counter.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # Program Counter
+      class ProgramCounter < Base
+        tag :PC
+
+        diagram <<~DIAGRAM
+          (A)---|  |---(QA)
+          (B)---|  |---(QB)
+          (C)---|PC|---(QC)
+          (D)---|  |---(QD)
+          (LD)--|
+        DIAGRAM
+
+        define_inputs :a, :b, :c, :d, :ld, clock: :ck
+
+        define_outputs :qa, :qb, :qc, :qd
+
+        assembling do |a, b, c, d, ld, qa, qb, qc, qd|
+          # define_inputs :cin, :a0, :b0, :a1, :b1, :a2, :b2, :a3, :b3
+          fadd = Combinational::FullAdder4bit.new(0, 0, 1, 0, 0, 0, 0, 0, 0)
+
+          [[a, qa, :a0, :s0], [b, qb, :a1, :s1], [c, qc, :a2, :s2],
+           [d, qd, :a3, :s3]].each do |input, output, fadd_in, fadd_out|
+            dff = Sequential::DFlipFlop.new
+            mux = Combinational::Multiplexer2to1.new
+            input >> mux.c0
+            dff.q >> fadd.send(fadd_in)
+            fadd.send(fadd_out) >> mux.c1
+            ld    >> mux.a
+            mux.y >> dff.d
+            dff.q >> output
+          end
+        end
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/sequential/register_4bit.rb

@@ -0,0 +1,58 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module Sequential
+      # 4 bit register
+      class Register4bit < Base
+        tag :REG4
+
+        diagram <<~DIAGRAM
+                  +---------------------+
+                  +-|                   |
+          (A)-------|MUX|-------|DFF|---+---(QA)
+                +---|       +---|
+                |           |
+                | +---------------------+
+                | +-|       |           |
+          (B)-------|MUX|-------|DFF|---+---(QB)
+                +---|       +---|
+                |           |
+                | +---------------------+
+                | +-|       |           |
+          (C)-------|MUX|-------|DFF|---+---(QC)
+                +---|       +---|
+                |           |
+                | +---------------------+
+                | +-|       |           |
+          (D)-------|MUX|-------|DFF|---+---(QD)
+                +---|       +---|
+          (LD)--+     (CK)--+
+        DIAGRAM
+
+        define_inputs :a, :b, :c, :d, :ld, clock: :ck
+
+        define_outputs :qa, :qb, :qc, :qd
+
+        assembling do |a, b, c, d, ld, qa, qb, qc, qd|
+          [[a, qa], [b, qb], [c, qc], [d, qd]].each do |input, output|
+            dff = Sequential::DFlipFlop.new
+            mux = Combinational::Multiplexer2to1.new
+            input >> mux.c0
+            dff.q >> mux.c1
+            ld    >> mux.a
+            mux.y >> dff.d
+            dff.q >> output
+          end
+        end
+
+        truth_table <<~TRUTH_TABLE
+          | CK | A | B | C | D | LD | QA | QB | QC | QD |
+          | -- | - | - | - | - | -- | -- | -- | -- | -- |
+          |  ^ | x | x | x | x |  0 |  A |  B |  C |  D |
+          |  ^ | x | x | x | x |  1 | QA | QB | QC | QD |
+        TRUTH_TABLE
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/system_level/cpu_td4.rb

@@ -0,0 +1,120 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module SystemLevel
+      # TD4
+      class CpuTd4 < Base
+        tag :TD4
+
+        define_inputs :in0, :in1, :in2, :in3, clock: :ck
+
+        define_outputs :led1, :led2, :led3, :led4
+
+        assembling do |in0, in1, in2, in3, led1, led2, led3, led4|
+          register_a = Sequential::Register4bit.new
+          register_b = Sequential::Register4bit.new
+          register_c = Sequential::Register4bit.new
+          pc = Sequential::ProgramCounter.new
+          rom = Rom::Timer.new
+          dec = Combinational::Decoder.new
+          mux0 = Combinational::Multiplexer4to1.new
+          mux1 = Combinational::Multiplexer4to1.new
+          mux2 = Combinational::Multiplexer4to1.new
+          mux3 = Combinational::Multiplexer4to1.new
+          alu = Combinational::FullAdder4bit.new
+          dff = Sequential::DFlipFlop.new
+
+          [%i[s0 a], %i[s1 b], %i[s2 c], %i[s3 d]].each do |sel, reg|
+            alu.send(sel) >> register_a.send(reg)
+            alu.send(sel) >> register_b.send(reg)
+            alu.send(sel) >> register_c.send(reg)
+            alu.send(sel) >> pc.send(reg)
+          end
+          alu.c >> dff.d
+
+          [[:qa, in0, mux0, :a0], [:qb, in1, mux1, :a1], [:qc, in2, mux2, :a2], [:qd, in3, mux3, :a3]].each do |reg_out, in_port, mux, alu_in|
+            register_a.send(reg_out) >> mux.c0
+            register_b.send(reg_out) >> mux.c1
+            in_port >> mux.c2
+            Signals::Signal.new.off >> mux.c3
+            dec.sel_a >> mux.a
+            dec.sel_b >> mux.b
+            mux.y >> alu.send(alu_in)
+          end
+
+          register_c.qa >> led4
+          register_c.qb >> led3
+          register_c.qc >> led2
+          register_c.qd >> led1
+
+          pc.qa >> rom.a0
+          pc.qb >> rom.a1
+          pc.qc >> rom.a2
+          pc.qd >> rom.a3
+          rom.d0 >> alu.b0
+          rom.d1 >> alu.b1
+          rom.d2 >> alu.b2
+          rom.d3 >> alu.b3
+          rom.d4 >> dec.op0
+          rom.d5 >> dec.op1
+          rom.d6 >> dec.op2
+          rom.d7 >> dec.op3
+          dec.ld0 >> register_a.ld
+          dec.ld1 >> register_b.ld
+          dec.ld2 >> register_c.ld
+          dec.ld3 >> pc.ld
+          dff.q >> dec.c_flag
+
+          [register_a, register_b, pc, rom, dec]
+        end
+
+        def to_s
+          p_a = "(#{@a || "0000"})"
+          p_b = "(#{@b || "0000"})"
+
+          register_a, register_b, pc, rom, dec = components
+          @a = a = "#{register_a.qd}#{register_a.qc}#{register_a.qb}#{register_a.qa}"
+          @b = b = "#{register_b.qd}#{register_b.qc}#{register_b.qb}#{register_b.qa}"
+          p = "#{pc.qd}#{pc.qc}#{pc.qb}#{pc.qa}"
+          o = "#{led1}#{led2}#{led3}#{led4}"
+          i = "#{in3}#{in2}#{in1}#{in0}"
+          m = "#{rom.d3}#{rom.d2}#{rom.d1}#{rom.d0}"
+          c = "-(#{dec.c_flag})"
+          loc = p.to_i(2)
+
+          l1 = led1.current ? "*" : " "
+          l2 = led2.current ? "*" : " "
+          l3 = led3.current ? "*" : " "
+          l4 = led4.current ? "*" : " "
+
+          <<~OUTPUT
+
+              #{l1 * 7}#{" " * 7}#{l2 * 7}#{" " * 7}#{l3 * 7}#{" " * 7}#{l4 * 7}
+             #{l1 * 9}#{" " * 5}#{l2 * 9}#{" " * 5}#{l3 * 9}#{" " * 5}#{l4 * 9}
+            #{l1 * 11}#{" " * 3}#{l2 * 11}#{" " * 3}#{l3 * 11}#{" " * 3}#{l4 * 11}
+             #{l1 * 9}#{" " * 5}#{l2 * 9}#{" " * 5}#{l3 * 9}#{" " * 5}#{l4 * 9}
+              #{l1 * 7}#{" " * 7}#{l2 * 7}#{" " * 7}#{l3 * 7}#{" " * 7}#{l4 * 7}
+
+            +-----------------------------------------------+     #{loc ==  0 ? ">" : " "} OUT 0111
+            |                                               |     #{loc ==  1 ? ">" : " "} ADD A,0001
+            +--->|rg_a|#{p_a}----->|   |                    |     #{loc ==  2 ? ">" : " "} JNC 0001
+            |    |#{a}|            |   |                    |     #{loc ==  3 ? ">" : " "} ADD A,0001
+            |                      |   |                    |     #{loc ==  4 ? ">" : " "} JNC 0011
+            +--->|rg_b|#{p_b}----->|   |----------->|   |---+     #{loc ==  5 ? ">" : " "} OUT 0110
+            |    |#{b}|            |   |            |   |         #{loc ==  6 ? ">" : " "} ADD A,0001
+            |                      |SEL|            |ALU|         #{loc ==  7 ? ">" : " "} JNC 0110
+            +--->| out|  |  in|--->|   |            |   |         #{loc ==  8 ? ">" : " "} ADD A,0001
+            |    |#{o}|  |#{i}|    |   |  |  im|--->|   |-#{c}    #{loc ==  9 ? ">" : " "} JNC 1000
+            |                      |   |  |#{m}|                  #{loc == 10 ? ">" : " "} OUT 0000
+            +--->|  pc|  (0000)--->|   |                          #{loc == 11 ? ">" : " "} OUT 0100
+                 |#{p}|                                           #{loc == 12 ? ">" : " "} ADD A,0001
+                                                                  #{loc == 13 ? ">" : " "} JNC 1010
+                                                                  #{loc == 14 ? ">" : " "} OUT 1000
+                                                                  #{loc == 15 ? ">" : " "} JMP 1111
+          OUTPUT
+        end
+      end
+    end
+  end
+end

data/lib/logicuit/circuits/system_level/one_bit_cpu2.rb

@@ -0,0 +1,41 @@
+# frozen_string_literal: true
+
+module Logicuit
+  module Circuits
+    module SystemLevel
+      # 1 bit CPU with a Multiplexer
+      # Input A is H, MOV A,A
+      # Input A is L, NOT A
+      class OneBitCpu2 < Base
+        tag :ONE_BIT_CPU2
+
+        diagram <<~DIAGRAM
+          +------------------------+
+          |              +-------------(Y)
+          +----|   |-+---+---|     |
+               |DFF| |       |     |
+          (CK)-|>  | +-|NOT|-|MUX|-+
+                             |
+                       (A)---|
+        DIAGRAM
+
+        define_inputs :a, clock: :ck
+
+        define_outputs :y
+
+        assembling do |a, y|
+          dff = Sequential::DFlipFlop.new
+          not_gate = Gates::Not.new
+          mux = Combinational::Multiplexer2to1.new
+
+          dff.q >> y
+          dff.q >> mux.c0
+          dff.q >> not_gate.a
+          not_gate.y >> mux.c1
+          a >> mux.a
+          mux.y >> dff.d
+        end
+      end
+    end
+  end
+end

data/lib/logicuit/signals/clock.rb

@@ -13,7 +13,12 @@ module Logicuit
 
       def tick
         @tick_count += 1
-        @on_tick.each(&:evaluate)
+        # Call the `evaluate` method for all components.
+        # However, the input argument values should be bound to the values at the time `on_tick` is called.
+        @on_tick.map do |component|
+          args = component.input_targets.map { |input| component.instance_variable_get("@#{input}").current }
+          -> { component.evaluate(*args) }
+        end.each(&:call)
       end
 
       def self.instance

data/lib/logicuit/signals/signal.rb

@@ -17,12 +17,14 @@ module Logicuit
         changed = @current.!
         @current = true
         @on_change.each(&:evaluate) if changed
+        self
       end
 
       def off
         changed = @current
         @current = false
         @on_change.each(&:evaluate) if changed
+        self
       end
 
       def toggle

data/lib/logicuit/version.rb

@@ -1,5 +1,5 @@
 # frozen_string_literal: true
 
 module Logicuit
-  VERSION = "0.1.5"
+  VERSION = "0.2.0"
 end

data/lib/logicuit.rb

@@ -9,8 +9,16 @@ require_relative "logicuit/gates/nand"
 require_relative "logicuit/gates/xor"
 require_relative "logicuit/signals/signal"
 require_relative "logicuit/signals/clock"
-require_relative "logicuit/circuits/sequential/d_flip_flop"
-require_relative "logicuit/circuits/combinational/multiplexer2to1"
-require_relative "logicuit/circuits/combinational/multiplexer4to1"
+require_relative "logicuit/circuits/combinational/multiplexer_2to1"
+require_relative "logicuit/circuits/combinational/multiplexer_4to1"
 require_relative "logicuit/circuits/combinational/half_adder"
+require_relative "logicuit/circuits/combinational/full_adder"
+require_relative "logicuit/circuits/combinational/full_adder_4bit"
+require_relative "logicuit/circuits/combinational/decoder"
+require_relative "logicuit/circuits/rom/timer"
+require_relative "logicuit/circuits/sequential/d_flip_flop"
+require_relative "logicuit/circuits/sequential/register_4bit"
+require_relative "logicuit/circuits/sequential/program_counter"
 require_relative "logicuit/circuits/system_level/one_bit_cpu"
+require_relative "logicuit/circuits/system_level/one_bit_cpu2"
+require_relative "logicuit/circuits/system_level/cpu_td4"

metadata

@@ -1,13 +1,13 @@
 --- !ruby/object:Gem::Specification
 name: logicuit
 version: !ruby/object:Gem::Version
-  version: 0.1.5
+  version: 0.2.0
 platform: ruby
 authors:
 - Koji NAKAMURA
 bindir: exe
 cert_chain: []
-date: 2025-03-15 00:00:00.000000000 Z
+date: 2025-04-10 00:00:00.000000000 Z
 dependencies: []
 description: logi(c cir)cuit -> logicuit
 email:
@@ -22,11 +22,19 @@ files:
 - Rakefile
 - lib/logicuit.rb
 - lib/logicuit/base.rb
+- lib/logicuit/circuits/combinational/decoder.rb
+- lib/logicuit/circuits/combinational/full_adder.rb
+- lib/logicuit/circuits/combinational/full_adder_4bit.rb
 - lib/logicuit/circuits/combinational/half_adder.rb
-- lib/logicuit/circuits/combinational/multiplexer2to1.rb
-- lib/logicuit/circuits/combinational/multiplexer4to1.rb
+- lib/logicuit/circuits/combinational/multiplexer_2to1.rb
+- lib/logicuit/circuits/combinational/multiplexer_4to1.rb
+- lib/logicuit/circuits/rom/timer.rb
 - lib/logicuit/circuits/sequential/d_flip_flop.rb
+- lib/logicuit/circuits/sequential/program_counter.rb
+- lib/logicuit/circuits/sequential/register_4bit.rb
+- lib/logicuit/circuits/system_level/cpu_td4.rb
 - lib/logicuit/circuits/system_level/one_bit_cpu.rb
+- lib/logicuit/circuits/system_level/one_bit_cpu2.rb
 - lib/logicuit/gates/and.rb
 - lib/logicuit/gates/nand.rb
 - lib/logicuit/gates/not.rb