ecic 0.0.1

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data/Gemfile

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+source 'https://rubygems.org'
+
+# Specify your gem's dependencies in ecic.gemspec
+gemspec
+
+gem 'thor'

data/Gemfile.lock

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+PATH
+  remote: .
+  specs:
+    ecic (0.1.4)
+
+GEM
+  remote: https://rubygems.org/
+  specs:
+    diff-lcs (1.3)
+    rake (10.5.0)
+    rspec (3.8.0)
+      rspec-core (~> 3.8.0)
+      rspec-expectations (~> 3.8.0)
+      rspec-mocks (~> 3.8.0)
+    rspec-core (3.8.0)
+      rspec-support (~> 3.8.0)
+    rspec-expectations (3.8.1)
+      diff-lcs (>= 1.2.0, < 2.0)
+      rspec-support (~> 3.8.0)
+    rspec-mocks (3.8.0)
+      diff-lcs (>= 1.2.0, < 2.0)
+      rspec-support (~> 3.8.0)
+    rspec-support (3.8.0)
+    thor (0.20.0)
+
+PLATFORMS
+  ruby
+
+DEPENDENCIES
+  bundler (~> 1.13)
+  ecic!
+  rake (~> 10.0)
+  rspec (~> 3.0)
+  thor
+
+BUNDLED WITH
+   1.13.5

data/README.md

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+# Easy IC : open-source, cross-platform framework for developing digital ASIC and FPGA designs
+
+## NOTE: this project has just been started. Hence, the description below is what will come in the future, but none of the features have been implemented yet.
+
+ECIC is pronounced '`Easy IC`' and is an open-source, cross-platform framework for developing digital ASIC and FPGA designs. It enables you to quickly start a new IC project that is independent of both IC tool vendors and technology (FPGA/ASIC). ECIC creates a suitable project folder/file structure and provides a user friendly flow for configuring the project, fast compilation of RTL files etc.. It also provides generators for generating eg. new RTL files, libraries and testbenches for both VHDL, SystemVerilog and UVM.
+
+One of the mantras for ECIC is `Convention Over Configuration` (inspired by the [https://rubyonrails.org/](RubyOnRails) web framework), which ensures a consistent structure across all projects using this framework - and a minimum of required configuration.
+
+**The main highlights are:**
+
+  * Free and open-source
+  * Cross-platform (Windows, Linux)
+  * Scaffolding of projects and sub components
+  * IC tool vendor independent flow
+  * IC technology independent flow
+  * Convention over configuration
+  * Fast, parallel compilation of RTL files
+  * Automatic GNU Make dependency graph generation for VHDL files
+  * Easily extendable with custom features
+
+## Installation
+
+To install the framework, simply use the `gem` command:
+
+    $ gem install ecic
+
+If the `gem` command is not available on your computer, you can get it through the RubyGems package available at [rubygems.org](https://rubygems.org).
+
+## Usage
+
+The `ecic new` command creates a new ECIC project with a default directory structure and configuration at the path you specify. To create a new project in a folder called `./my_project`, run:
+
+    $ ecic new my_project
+
+If you already have an existing project and you want the project to use the ECIC framework, please follow the steps described in the 'Migrating an existing project to use ECIC' section below.
+
+### Create new RTL library
+
+Each RTL file in your project must belong to a given VHDL/Verilog library. When creating or adding RTL files to you project, a library can be created on the fly, but you can also create libraries manually using the `ecic generate library` command.
+
+To create a library called `my_lib`, enter the project folder and run the `generate library` command, eg.:
+
+    $ cd my_project
+    $ ecic generate library my_lib
+
+This will create a folder called `my_lib` in the `./src/design` folder and add the library to the project (by adding it to the `./src/config/libraries.rb` file).
+
+You can create multiple libraries with one command by specifying a list of libraries, eg.:
+
+    $ ecic generate library my_lib1 my_lib2
+
+<!--
+By default, the `ecic generate library` command will also create an RTL design (VHDL component + entity + architecture or Verilog module) with the same name as the library. 
+The RTL design is automatically added to the library by adding it to the `sources.rb` file, which will be created at the root of each library folder.
+-->
+A `sources.rb` file will be created at the root of each library folder, which defines the RTL files that must be associated with the given library.
+
+To see the full list of options for the `ecic generate library` command, run `ecic generate help library`.
+
+### Create new RTL file
+
+Creating a **new** RTL design can be done with the `ecic generate design` command. For VHDL designs, this command will generate both the component, entity and architecture and for SystemVerilog it will create a module. If you already have existing RTL design files you wish to add to the project, you should use the `ecic add design` command instead, see the 'Add existing RTL files' section.
+
+The type of RTL design (VHDL or Verilog) to create is controlled by a `--type=vhdl|verilog` option and defaults to the value defined by the `config.generator.library.type.default` setting in the `./src/config/ecic.rb` configuratinon file.
+
+The `ecic generate design` command can be called from any directory within your project. To see the full list of options for the `ecic generate design` command, run `ecic generate help design`.
+
+#### Create new VHDL design(s)
+
+To create a new VHDL design called `my_design1` and associate it with a library called `my_lib`, run:
+
+    $ ecic generate design --type=vhdl --lib=my_lib my_design1
+
+If you specify a library that does not exist, you will be asked to confirm the creation of the new library.
+
+When creating a new VHDL design, you will be given the option to also create and include a `types and constants` package definition file.
+
+The following VHDL files will be created (relative to the project root folder):
+
+    ./src/design/my_lib/my_design1-pkg-comp.vhd    # Component definition
+    ./src/design/my_lib/my_design1-ent.vhd         # Entity definition
+    ./src/design/my_lib/my_design1-arc-rtl.vhd     # RTL architecture
+    ./src/design/my_lib/my_design1-pkg-types.vhd   # Types and constants definition package (optional)                                                     
+
+Placing each component, entity and architecture in separate files allows a projects to be recompiled very fast when only a few files have been modified, since eg. an update that is isolated to a single RTL architecture only requires that one file to be recompiled. Splitting the entity and architecture into separate files also allows you to have multiple architectures for the save entity and choose between the architecture files at compile time without having to use `VHDL configuration` constructs.
+
+Should you still wish to combine eg. the entity and architecture files into one file, you can configure `ECIC` to do this by default by setting `config.generator.design.vhdl.combine` option in `./src/config/ecic.rb`:
+
+    config.generator.design.vhdl.combine = 'entity + architecture'
+
+##### Create multiple VHDL design for the same library
+
+You can create multiple designs at the same time, and designs can be placed in subfolders within a library. For example, to create a new VHDL design called `my_design2` at the root of a library called `my_lib` and create another VHDL design called `my_design3` in a subfolder called `my_subblock`, run:
+
+    $ ecic generate design --type=vhdl --types-package --lib=my_lib my_design2 my_subblock/my_design3
+
+This will create the following VHDL files (relative to the project root folder):
+
+    ./src/design/my_lib/my_design2-comp.pkg.vhd                # Component definition
+    ./src/design/my_lib/my_design2-ent.vhd                     # Entity definition
+    ./src/design/my_lib/my_design2-rtl_arc.vhd                 # RTL architecture
+    ./src/design/my_lib/my_design2-pkg-types.vhd               # Types and constants definition package (optional)                                                     
+    ./src/design/my_lib/my_subblock/my_design3-comp-pkg.vhd    # Component definition
+    ./src/design/my_lib/my_subblock/my_design3-ent.vhd         # Entity definition
+    ./src/design/my_lib/my_subblock/my_design3-rtl_arc.vhd     # RTL architecture
+    ./src/design/my_lib/my_subblock/my_design3-pkg-types.vhd   # Types and constants definition package (optional)                                                     
+
+In this example the `--types-package` option is used to automatically include the `*-pkg-types.vhd` files without prompting the user with the option.
+ 
+All generated VHDL files will be added to the `sources.rb` file in the given library.
+
+#### Create new SystemVerilog file(s)
+
+The procedure for creating SystemVerilog files is the same as for generating VHDL files, except that the `--type` option must be set to `sv`.
+
+For example, to create two SystemVerilog modules called `my_design1` and `my_design2` and place them in separate subfolders within a library called `my_lib`, run:
+
+    $ ecic generate design --type=sv --lib=my_lib my_design1 my_design2
+
+This will create the following SystemVerilog files (relative to the project root folder):
+
+    ./src/design/my_lib/my_design1.sv    # SystemVerilog module
+    ./src/design/my_lib/my_design2.sv    # SystemVerilog module
+
+All generated SystemVerilog files will be added to the `sources.rb` file in the given library.
+
+#### Omitting the --lib option
+
+If the `ecic generate design` command is called from within a library folder (or subfolder), the `--lib` option can be omitted, in which case the new designs will be created for that library. The files will be placed relative to the current working directory.
+
+Example:
+
+    $ cd ./src/design/queue_system/arbitor
+    $ ecic generate design --type=vhdl statemachine
+
+That will generate the files as:
+
+    ./src/design/queue_system/arbitor/statemachine-*.vhd      #Path is relative to the project root folder
+
+## Migrating an existing project to use ECIC
+
+If you already have an existing project and you want the project to use the ECIC framework, simply specify the path to that project folder (after making sure you have a backup, of course) eg.:
+
+    ecic new ~/my_existing_project
+
+If the folder contains files that will normally be overwritten by the framework, you will be asked whether to overwrite them. If you want to keep any conflicting files, then choose `n` (no, do not overwrite) for each conflicting file. You can then move or rename the original, conflicting files and run the `ecic new PATH` command again.
+
+### Add existing RTL files
+
+To add an existing RTL file to the project, go to the project folder and use the `ecic add design` commmand. This will add all the listed files to the given design library. If the library does not already exist, you will be asked to confirm the creation of it.
+
+For example, to add two existing files named `./foo/bar/some_design.sv` and `../toto/kuku.vhd` to a library called `my_lib`, run:
+
+    $ ecic add design my_lib ./foo/bar/some_design.sv ../toto/kuku.vhd
+
+Although all files that belong to a given library should be placed in the folder for that library, you can specify files that are placed anywhere in your file system.
+
+If you have a Unix like terminal and want to eg. add all files in a `./foo` folder that has the extension `.vhd`, you can use the standard Unix `find` command:
+
+    $ ecic add design my_lib `find ./foo -name "*.vhd"`
+
+When adding files to the project, the file extension (eg. vhd) is used to determine the file type. VHDL files are expected to have a .vhd or .vhdl extension and Verilog/SystemVerilog files are expected to have a .sv og .v extension. You can also specify the file type with a `type=vhdl|sv` option, eg.:
+
+    $ ecic add design --type=vhdl my_lib `find ./foo -name "*.*"`
+
+## Compiling and elaborating RTL files
+
+The project is compiled and elaborated with the `ecic compile [SCOPE]` command. The `SCOPE` option is optional and allows you to compile and elaborate different set of RTL files, eg. one set of files for an FPGA, another set of files for ASIC RTL simulations and a third set of files for ASIC gate-level simulations.
+
+To compile and elaborate your project, simply run:
+
+    $ ecic compile [SCOPE]
+
+SystemVerilog files will be compiled in the order they are listed in the sources.rb files and they will be compiled before any VHDL files.
+
+## Development
+
+After checking out the repo, run `bin/setup` to install dependencies. Then, run `rake spec` to run the tests. You can also run `bin/console` for an interactive prompt that will allow you to experiment.
+
+To install the ECIC framework onto your local machine, run `bundle exec rake install`.
+<!--
+ To release a new version, update the version number in `version.rb`, and then run `bundle exec rake release`, which will create a git tag for the version, push git commits and tags, and push the `.gem` file to [rubygems.org](https://rubygems.org).
+-->
+## Contributing
+
+Bug reports and pull requests are welcome on GitHub at https://github.com/ic-factory/ecic.

data/Rakefile

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+require "bundler/gem_tasks"
+require "rspec/core/rake_task"
+
+RSpec::Core::RakeTask.new(:spec)
+
+task :default => :spec

data/bin/console

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+#!/usr/bin/env ruby
+
+require "bundler/setup"
+require "ecic"
+
+# You can add fixtures and/or initialization code here to make experimenting
+# with your gem easier. You can also use a different console, if you like.
+
+# (If you use this, don't forget to add pry to your Gemfile!)
+# require "pry"
+# Pry.start
+
+require "irb"
+IRB.start

data/bin/ecic

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+#!/usr/bin/env ruby
+
+$LOAD_PATH.unshift File.expand_path("../../lib", __FILE__)
+require "ecic"
+
+Ecic::Cli.start(ARGV)

data/bin/setup

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+#!/usr/bin/env bash
+set -euo pipefail
+IFS=$'\n\t'
+set -vx
+
+bundle install

data/config/ecic.yaml

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+ecic:
+  config:
+    generator:
+      library:
+        type:
+         default: vhdl
+      design:
+        vhdl:
+          combine: ''

data/config/locales/help.en.yaml

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+help:
+  new:
+    short: Generate a new project called NAME
+    long:  |
+      Creates a new chip project called NAME.
+   
+      Example: ecic new my_project
+
+      This creates a new project called 'my_project' in ./my_project
+  generate:
+    short: Generate new testbenches, RTL modules, tests etc.!
+  generators:
+    testbench:
+      short: Create a new testbench
+      long: |
+        Create a new VHDL, SystemVerilog or UVM testbench.
+        The testbench type MUST be defined with the --type option.
+
+        Example: ecic generate testbench my_tb --type=uvm --verbose
+
+        This creates a new UVM testbench called 'my_tb' in ./src/testbench/my_tb and prints info along the way
+        
+    library:
+      short: Create a new library
+      long: |
+            Create a new VHDL/SystemVerilog library.
+            
+            Example: ecic generate library lib1 lib2 lib3...
+
+            This creates the given libraries in the ./src/design/ directory of 
+            your project and adds the libraries to ./src/config/libraries.rb

data/ecic.gemspec

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+# coding: utf-8
+lib = File.expand_path('../lib', __FILE__)
+$LOAD_PATH.unshift(lib) unless $LOAD_PATH.include?(lib)
+require 'ecic/version'
+
+Gem::Specification.new do |spec|
+  spec.name          = "ecic"
+  spec.version       = Ecic::VERSION
+  spec.authors       = ["Torben Fox Jacobsen"]
+  spec.email         = ["ecic@ic-factory.com"]
+  spec.licenses       = ['LGPL-3.0']
+  spec.summary       = %q{Easy-IC : provides a framework for ASIC and FPGA projects that favors convention over configuration.}
+  spec.description   = %q{This gem allows you to easily create a new ASIC/FPGA project with a file structure and support tools that ensures consistency between your projects and gets you up to speed in no time. To create a new project simply type 'ecic new PATH'.}
+  spec.homepage      = "https://github.com/ic-factory/ecic"
+
+  spec.files         = `git ls-files -z`.split("\x0").reject do |f|
+    f.match(%r{^(test|spec|features)/})
+  end
+  spec.bindir        = "exe"
+  spec.executables   = spec.files.grep(%r{^exe/}) { |f| File.basename(f) }
+  spec.require_paths = ["lib"]
+
+  spec.add_development_dependency "bundler", "~> 1.13"
+  spec.add_development_dependency "rake", "~> 10.0"
+  spec.add_development_dependency "rspec", "~> 3.0"
+end

data/features_wishlist.md

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+Here is a list of tools and features that we hope will be available in the future. Contributions and suggestions are most welcome.
+
+### Tools:
+
+  * Plugin for various editors that make is easy to eg. create new RTL libraries and designs.
+  * Tool to include external libraries from 3ed parties.
+  * Tool to import a XILINX Vivado project file.
+
+### Features:
+
+  * TBD
+  
+###Observations:
+
+GNU Make commands are not suited as a multiple-level command line. It does not have built-in argument checking for target, in the sence that if you need to provide an argument to the a Make command and you misspell the argument, no built-in warnings will be given.
+
+Example:
+
+    > make some_target some_option=whatever
+    > make some_target something_wrong=whatever
+    > make some_target some_option=whatever
+  
+
+#Requirements
+  * library names must be converted to snake_case before creating a new library.

data/lib/ecic.rb

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+#TBA:
+# 1. Create a generator that creates a new (custom) generator
+# 2. Add project name and version as options to 'new' generator
+# 3. Add option to specify whether separate files must be used (by default) for VHDL entities
+#    and architectures.
+# 4. Make sure the 'new' action calls 'bundle install' in new project.
+# 5. What should the file format be for libraries and source file config files? We want 
+#    to be able to automatically add content to these files.
+#        sources.yaml
+#        sources.yaml.erb
+#        sources.rb <- This might be the best option (and have a convention for what it should contain).
+#        libraries.rb <- This might be the best option.
+# If the user tries to call the 'generate' command outside a project, 
+# an error message must be returned stating that this command can only be called from within a project.
+
+require "ecic/version"
+
+module Ecic
+  require 'yaml'
+  require 'thor'
+  require 'thor/group'
+  require "ecic/project_generator"
+  require "ecic/library_generator"
+
+  def self.help_text
+    YAML.load(File.read(File.expand_path("../../config/locales/help.en.yaml", __FILE__)))['help']
+  end
+
+  #TBA: Make a function that returns the root folder for the project
+  def self.root
+    File.expand_path("./tfj2")
+  end
+
+  class Generate < Thor
+    #--------------------------------------------------------------------------
+    # TESTBENCH generator:
+    #--------------------------------------------------------------------------
+    class_option :verbose, :type => :boolean
+
+    desc "testbench NAME", Ecic::help_text['generators']['testbench']['short']
+    long_desc Ecic::help_text['generators']['testbench']['long']
+    option :type, :banner => 'vhdl|sv|uvm', :required => true, :desc => 'Speficy the testbench type (VHDL, SystemVerilog or UVM)'
+    option :just_print, :type => :boolean, :aliases => '-n', :desc => "Don't actually run any commands; just print them."
+    def testbench(name)
+      puts "Implement a generator for creating a new testbench"
+    end
+
+    desc "library NAME...", Ecic::help_text['generators']['library']['short']
+    long_desc Ecic::help_text['generators']['library']['long']
+    option :just_print, :type => :boolean, :aliases => '-n', :desc => "Don't actually run any commands; just print them."
+#    def library(names)
+    def library(lib_name)
+      generator = LibraryGenerator.new
+      generator.destination_root = Ecic::root
+#      names.each do |lib_name|
+        generator.library_name = lib_name
+        generator.invoke_all
+#      end
+    end
+        
+  end  
+
+  class Cli < Thor
+
+    check_unknown_options!
+
+    #Make sure to return non-zero value if an error is thrown.
+    def self.exit_on_failure?
+      true
+    end
+    
+    class << self
+      def help(shell, subcommand = false)
+        shell.say "Usage: ecic COMMAND [ARGS]"
+        shell.say ""
+        super
+        shell.say "To get more help on a specific command, try 'ecic help [COMMAND]'"
+      end
+    end
+
+    #--------------------------------------------------------------------------
+    # VERSION command:
+    #--------------------------------------------------------------------------
+    desc 'version', 'Display version'
+    map %w[-v --version] => :version
+    def version
+      say "#{VERSION}"
+    end
+
+    #--------------------------------------------------------------------------
+    # NEW command:
+    #--------------------------------------------------------------------------
+    long_desc Ecic::help_text['new']['long']
+    desc "new PATH", Ecic::help_text['new']['short']
+    option :verbose, :type => :boolean
+    def new(path)
+      path = File.expand_path(path)
+      puts "Generating a new project in #{path}"
+      generator = ProjectGenerator.new
+      generator.destination_root = path
+      generator.invoke_all
+      #TBA: invoke installation by eg. calling 'bundler install' from within the generate project folder
+      
+    end
+
+    desc "generate SUBCOMMAND ...ARGS", Ecic::help_text['generate']['short']
+    subcommand "generate", Generate
+
+  end
+  
+end

data/lib/ecic/library_generator.rb

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+module Ecic
+
+  class LibraryGenerator < Thor::Group
+    include Thor::Actions
+    desc 'Generate a new RTL library'
+
+    attr_writer :library_name
+    
+    def self.source_root
+      File.dirname(__FILE__) + '/../../templates'
+    end
+
+#    def create_library_directory
+#      copy_file 'projects/src/design/lib/sources.rb', "src/design/#{@library_name}/sources.rb"
+#    end
+
+    def update_library_list
+      #TBA 'src/config' creation is only temporary fix!
+      libraries_file = File.expand_path("#{destination_root}/src/config/libraries.rb")
+      empty_directory 'src/config' unless File.exist?(File.dirname(libraries_file))      
+      create_file libraries_file unless File.exist?(libraries_file)                  
+      append_to_file 'src/config/libraries.rb', "add library #{@library_name}\n"
+    end
+
+  end
+
+end

data/lib/ecic/project_generator.rb

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+module Ecic
+
+  class ProjectGenerator < Thor::Group
+    include Thor::Actions
+    desc 'Generate a new chip project'
+  
+    def self.source_root
+      File.dirname(__FILE__) + '/../../templates/project'
+    end
+
+    def create_base_files
+      copy_file 'gitignore', '.gitignore'
+      copy_file 'config/project.rb', 'src/config/project.rb'
+      copy_file 'config/libraries.rb', 'src/config/libraries.rb'
+      copy_file 'Gemfile', 'Gemfile'
+    end
+
+    def create_output_directories
+      #TBA: Replace these lines with a call to a TestbenchGenerator class
+      empty_directory 'src/testbench/chip'
+      empty_directory 'src/verification/chip'
+
+      copy_file 'src/packages/README.txt', 'src/packages/README.txt'
+      create_file 'src/design/chip/sources.rb'
+      empty_directory 'src/external_packages'
+    end
+
+    #Replace this function with a call to a 'VHDLComponentGenerator' class
+    def create_top_entity
+      create_file 'src/design/chip/sources.yaml.erb'
+      create_file 'src/design/chip/chip-rtl_arc.vhd'
+      create_file 'src/design/chip/chip-ent.vhd'
+    end
+
+    def git_init
+      run 'git init ' + destination_root
+    end
+  end
+
+end

data/lib/ecic/version.rb

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+module Ecic
+  VERSION = "0.0.1"
+end

data/notes.txt

@@ -0,0 +1,6 @@
+#Syntax for sources.rb
+
+add design   chip, :env => ['asic_rtl', 'asic_gate', 'fpga_rtl']
+add design   [basic_vhdl, chip], :except => {:env => ['asic']}
+#add design chip_tb, :path => '/some/absolute/path'
+#add testbench chip_tb, :path => '/some/absolute/path'

data/templates/project/Gemfile

@@ -0,0 +1,3 @@
+source 'https://rubygems.org'
+ruby '2.1.5'
+gem 'ecic'

data/templates/project/config/libraries.rb

@@ -0,0 +1,9 @@
+#This file lists all libraries in the project.
+
+#Syntax:
+#     add library LIBRARY
+# where LIBRARY is the name of a VHDL/Verilog library that must be placed in a folder of the same name under src/design
+
+#Syntax:
+#     add testbench TESTBENCH
+# where TESTBENCH is the name of a testbench that must be placed in a folder of the same name under src/testbench

data/templates/project/config/project.rb

@@ -0,0 +1,13 @@
+Ecic.project.configure do
+
+  #Select the default type of RTL files you wish to generate:
+  #VHDL or SystemVerilog:
+  config.generator.library.type.default = 'vhdl'
+  # config.generator.library.type.default = 'sv'   
+
+  config.generator.design.vhdl.combine = ''
+#  config.generator.design.vhdl.combine = 'entity + architecture'
+#  config.generator.design.vhdl.combine = 'entity + component'
+#  config.generator.design.vhdl.combine = 'entity + architecture + component'
+
+end

data/templates/project/gitignore

@@ -0,0 +1,2 @@
+obj
+src/external_packages

metadata

@@ -0,0 +1,111 @@
+--- !ruby/object:Gem::Specification
+name: ecic
+version: !ruby/object:Gem::Version
+  version: 0.0.1
+platform: ruby
+authors:
+- Torben Fox Jacobsen
+autorequire: 
+bindir: exe
+cert_chain: []
+date: 2018-10-02 00:00:00.000000000 Z
+dependencies:
+- !ruby/object:Gem::Dependency
+  name: bundler
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '1.13'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '1.13'
+- !ruby/object:Gem::Dependency
+  name: rake
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '10.0'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '10.0'
+- !ruby/object:Gem::Dependency
+  name: rspec
+  requirement: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '3.0'
+  type: :development
+  prerelease: false
+  version_requirements: !ruby/object:Gem::Requirement
+    requirements:
+    - - "~>"
+      - !ruby/object:Gem::Version
+        version: '3.0'
+description: This gem allows you to easily create a new ASIC/FPGA project with a file
+  structure and support tools that ensures consistency between your projects and gets
+  you up to speed in no time. To create a new project simply type 'ecic new PATH'.
+email:
+- ecic@ic-factory.com
+executables: []
+extensions: []
+extra_rdoc_files: []
+files:
+- Gemfile
+- Gemfile.lock
+- README.md
+- Rakefile
+- bin/console
+- bin/ecic
+- bin/setup
+- config/ecic.yaml
+- config/locales/help.en.yaml
+- ecic.gemspec
+- features_wishlist.md
+- lib/ecic.rb
+- lib/ecic/library_generator.rb
+- lib/ecic/project_generator.rb
+- lib/ecic/version.rb
+- notes.txt
+- templates/project/Gemfile
+- templates/project/config/libraries.rb
+- templates/project/config/project.rb
+- templates/project/gitignore
+- templates/project/src/design/lib/sources.rb
+- templates/project/src/packages/README.txt
+homepage: https://github.com/ic-factory/ecic
+licenses:
+- LGPL-3.0
+metadata: {}
+post_install_message: 
+rdoc_options: []
+require_paths:
+- lib
+required_ruby_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+required_rubygems_version: !ruby/object:Gem::Requirement
+  requirements:
+  - - ">="
+    - !ruby/object:Gem::Version
+      version: '0'
+requirements: []
+rubyforge_project: 
+rubygems_version: 2.6.7
+signing_key: 
+specification_version: 4
+summary: 'Easy-IC : provides a framework for ASIC and FPGA projects that favors convention
+  over configuration.'
+test_files: []