circuits 0.10.0 → 0.11.0
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- checksums.yaml +8 -8
- data/lib/circuits/component/and.rb +5 -10
- data/lib/circuits/component/base.rb +46 -13
- data/lib/circuits/component/d.rb +32 -54
- data/lib/circuits/component/nand.rb +5 -10
- data/lib/circuits/component/nor.rb +5 -10
- data/lib/circuits/component/not.rb +5 -11
- data/lib/circuits/component/or.rb +5 -10
- data/lib/circuits/component/sr_nand.rb +20 -47
- data/lib/circuits/component/sr_nor.rb +20 -47
- data/lib/circuits/component/xnor.rb +5 -10
- data/lib/circuits/component/xor.rb +5 -10
- data/lib/circuits/version.rb +1 -1
- data/spec/unit/circuits/component/and_spec.rb +1 -1
- data/spec/unit/circuits/component/base_spec.rb +2 -24
- data/spec/unit/circuits/component/nand_spec.rb +1 -1
- data/spec/unit/circuits/component/nor_spec.rb +1 -1
- data/spec/unit/circuits/component/or_spec.rb +1 -1
- data/spec/unit/circuits/component/xnor_spec.rb +2 -2
- data/spec/unit/circuits/component/xor_spec.rb +2 -2
- metadata +2 -2
checksums.yaml
CHANGED
@@ -1,15 +1,15 @@
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---
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!binary "U0hBMQ==":
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metadata.gz: !binary |-
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-
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+
YTQ4YTRjMjcwYmU5OGRiY2MzMzhkNzkxZDNlNDI5MGQ5NWU5YzYwNg==
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data.tar.gz: !binary |-
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YjgxYmQ4M2E2MzQ1OTI3ZGI2NDBjZjBlZTc3ZDU0MmViNTU3ZjQxYQ==
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SHA512:
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metadata.gz: !binary |-
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NTY0MzBjODYzMzJjNTRkZmJlMjgxYmY1ZGUyNTdlMzM3NGQ1YWQ5ZjU1YjZk
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+
ODQ4MGQwZmE3NjI4MjY5MGZkY2RhYTQxOWUyYzJiOWU5NzJjOWZhMDg4YmU3
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+
MjhjOWQ1NzdjNzFlOGM1ZmJjNzhkODg2M2MwMzQ1NTA4MGViZmI=
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data.tar.gz: !binary |-
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MWVkNTg2Y2E5NDQ1ZDViMjMyMDBlZTQzYmNjZGMzNjRiZTc1YzVjZjc5NDkw
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MWYwZmE5ZTlkMmYwYzZkNGEwNTQ2YTcxMmY1ZDRmM2MyZWEwYzYxM2QyNTBk
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+
ZjNkNmRkZDc4OTQ3ZDQwMDM2NDYzOGIzZjk2NmIxMDc0NTQ5MjQ=
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@@ -4,20 +4,15 @@ module Circuits
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4
4
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module Component
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5
5
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# Logical AND Operator
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6
6
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class And < Base
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7
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+
def initialize(opts = {})
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8
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inputs = opts[:inputs] || 2
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super(inputs: inputs, outputs: 1)
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10
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end
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11
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+
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7
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# Sets the output to be the result of a logical AND of the inputs
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def tick
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self[:out].set(inputs.map(&:get).inject(:&))
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end
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-
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private
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-
def default_input_count
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2
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-
end
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def default_output_count
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1
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-
end
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end
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end
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end
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@@ -10,15 +10,17 @@ module Circuits
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class Base
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# Creates the Component with inputs and outputs
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# @param opts [Hash] options to create the Component with
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-
# @option opts [FixNum] :
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-
#
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+
# @option opts [FixNum, Array<Symbol>] :inputs The number of inputs or an
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# array of their names
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# @option opts [FixNum, Array<Symbol>] :ouputs The number of outputs or an
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# array of their names
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# @option opts [Hash] :port_mappings The port_mappings to use
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def initialize(opts = {})
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-
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@
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-
@
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@
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@inputs = create_inputs opts[:inputs]
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@outputs = create_outputs opts[:outputs]
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@port_mappings = create_port_mappings opts
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@sub_components = opts[:sub_components] || []
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@ticks = opts[:ticks] || 0
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end
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# the inputs of this component
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@@ -36,6 +38,14 @@ module Circuits
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res
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end
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41
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# Computes the outputs based on the inputs and previous state
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def tick
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@ticks.times.each do
|
44
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@sub_components.each(&:tick)
|
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@sub_components.each(&:tock)
|
46
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+
end
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end
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# Sets all the outputs expose what was set in #tick
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def tock
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outputs.each(&:tock)
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@@ -52,7 +62,7 @@ module Circuits
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# @param port [Symbol] The symbol that represents the terminal
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# @return [Input, Output] The terminal
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def [](port)
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-
port_mapping = port_mappings[port]
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+
port_mapping = @port_mappings[port]
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return nil if port_mapping.nil?
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port_number = port_mapping[:number]
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case port_mapping[:type]
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@@ -65,17 +75,33 @@ module Circuits
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private
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-
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def create_inputs(inputs)
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input_count = inputs.class == Fixnum ? inputs : inputs.length
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input_count.times.map { Circuits::Terminal::Input.new }
|
81
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+
end
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+
|
83
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+
def create_outputs(outputs)
|
84
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output_count = outputs.class == Fixnum ? outputs : outputs.length
|
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output_count.times.map { Circuits::Terminal::Output.new }
|
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+
end
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-
def
|
88
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+
def create_port_mappings(opts = {})
|
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res = {}
|
72
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-
(input_mappings +
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+
(input_mappings(opts[:inputs]) +
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+
output_mappings(opts[:outputs])).each do |mapping|
|
73
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res.merge!(mapping)
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74
93
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end
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res
|
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end
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-
def input_mappings
|
97
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+
def input_mappings(input_names)
|
98
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+
return default_input_mappings unless input_names.class == Array
|
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+
input_names.map.each_with_index do |input_name, num|
|
100
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+
{ input_name => { type: :input, number: num } }
|
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+
end
|
102
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+
end
|
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+
|
104
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+
def default_input_mappings
|
79
105
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input_count = inputs.length
|
80
106
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return [{ in: { type: :input, number: 0 } }] if input_count == 1
|
81
107
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input_count.times.collect do |num|
|
@@ -83,7 +109,14 @@ module Circuits
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109
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end
|
84
110
|
end
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85
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86
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-
def output_mappings
|
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+
def output_mappings(output_names)
|
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return default_output_mappings unless output_names.class == Array
|
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output_names.map.each_with_index do |output_name, num|
|
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+
{ output_name => { type: :output, number: num } }
|
116
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+
end
|
117
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+
end
|
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+
|
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+
def default_output_mappings
|
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output_count = outputs.length
|
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return[{ out: { type: :output, number: 0 } }] if output_count == 1
|
89
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output_count.times.collect do |num|
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data/lib/circuits/component/d.rb
CHANGED
@@ -1,80 +1,58 @@
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1
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require 'circuits/component/base'
|
2
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-
require 'circuits/component/
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2
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+
require 'circuits/component/and'
|
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+
require 'circuits/component/sr_nand'
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3
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5
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module Circuits
|
5
6
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module Component
|
6
7
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# Positive edge triggered D-type flip flop
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8
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class D < Base
|
8
9
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def initialize
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-
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-
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-
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-
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-
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-
link_sub_components
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sub_components = create_sub_components
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super(inputs: [:d, :clk], outputs: [:q, :not_q],
|
12
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+
sub_components: sub_components.map { |_, v| v },
|
13
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+
ticks: 4)
|
14
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+
link sub_components
|
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15
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reset
|
16
16
|
end
|
17
17
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|
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-
# Computes the outputs based on the inputs and previous state
|
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-
def tick
|
20
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-
3.times.each do
|
21
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-
sub_components.each(&:tick)
|
22
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-
sub_components.each(&:tock)
|
23
|
-
end
|
24
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-
end
|
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-
|
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18
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private
|
27
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|
28
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-
attr_reader :and_gate, :sr_nand_clk, :sr_nand_d, :sr_nand_out,
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-
:sub_components
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-
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20
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def create_sub_components
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-
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-
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-
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-
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-
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-
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-
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-
def default_input_count
|
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-
2
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-
end
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-
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-
def default_output_count
|
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-
2
|
45
|
-
end
|
46
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-
|
47
|
-
def link_and_gate
|
48
|
-
and_gate[:a].set sr_nand_clk[:not_q]
|
49
|
-
and_gate[:b].set self[:clk]
|
21
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+
{
|
22
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+
and_gate: Circuits::Component::And.new,
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23
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+
sr_nand_clk: Circuits::Component::SrNand.new,
|
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+
sr_nand_d: Circuits::Component::SrNand.new,
|
25
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+
sr_nand_out: Circuits::Component::SrNand.new
|
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+
}
|
50
27
|
end
|
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52
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-
def
|
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-
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-
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def link(sub_components)
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link_and_gate sub_components
|
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+
link_sr_nand_clk sub_components
|
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+
link_sr_nand_d sub_components
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+
link_sr_nand_out sub_components
|
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q.set sub_components[:sr_nand_out].q
|
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not_q.set sub_components[:sr_nand_out].not_q
|
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end
|
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-
def
|
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-
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-
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+
def link_and_gate(sc)
|
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sc[:and_gate].a.set sc[:sr_nand_clk].not_q
|
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sc[:and_gate].b.set clk
|
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end
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def link_sr_nand_clk
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-
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-
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def link_sr_nand_clk(sc)
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sc[:sr_nand_clk].not_s.set sc[:sr_nand_d].not_q
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sc[:sr_nand_clk].not_r.set clk
|
65
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end
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-
def
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-
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-
|
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+
def link_sr_nand_d(sc)
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sc[:sr_nand_d].not_s.set sc[:and_gate].out
|
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sc[:sr_nand_d].not_r.set d
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end
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def
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-
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link_sr_nand_d
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link_sr_nand_clk
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link_sr_nand_out
|
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+
def link_sr_nand_out(sc)
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sc[:sr_nand_out].not_s.set sc[:sr_nand_clk].not_q
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sc[:sr_nand_out].not_r.set sc[:sr_nand_d].q
|
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56
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end
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80
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def reset
|
@@ -4,20 +4,15 @@ module Circuits
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4
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module Component
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5
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# Logical NAND Operator
|
6
6
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class Nand < Base
|
7
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+
def initialize(opts = {})
|
8
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inputs = opts[:inputs] || 2
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super(inputs: inputs, outputs: 1)
|
10
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+
end
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|
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# Sets the output to be the result of a logical NAND of the inputs
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def tick
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self[:out].set(!inputs.map(&:get).inject(:&))
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end
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-
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private
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-
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-
def default_input_count
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-
2
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end
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-
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def default_output_count
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-
1
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-
end
|
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end
|
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end
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end
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@@ -4,20 +4,15 @@ module Circuits
|
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4
4
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module Component
|
5
5
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# Logical NOR Operator
|
6
6
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class Nor < Base
|
7
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+
def initialize(opts = {})
|
8
|
+
inputs = opts[:inputs] || 2
|
9
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+
super(inputs: inputs, outputs: 1)
|
10
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+
end
|
11
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+
|
7
12
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# Sets the output to be the result of a logical OR of the inputs
|
8
13
|
def tick
|
9
14
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self[:out].set(!inputs.map(&:get).inject(:|))
|
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15
|
end
|
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-
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-
private
|
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-
|
14
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-
def default_input_count
|
15
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-
2
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16
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-
end
|
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-
|
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-
def default_output_count
|
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-
1
|
20
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-
end
|
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|
end
|
22
17
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end
|
23
18
|
end
|
@@ -4,19 +4,13 @@ module Circuits
|
|
4
4
|
module Component
|
5
5
|
# Logical NOT Operator
|
6
6
|
class Not < Base
|
7
|
-
|
8
|
-
|
9
|
-
self[:out].set(!self[:in].get)
|
7
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+
def initialize
|
8
|
+
super(inputs: 1, outputs: 1)
|
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9
|
end
|
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-
|
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-
|
14
|
-
|
15
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-
1
|
16
|
-
end
|
17
|
-
|
18
|
-
def default_output_count
|
19
|
-
1
|
11
|
+
# Sets the output to be the result of a logical NOT of the inputs
|
12
|
+
def tick
|
13
|
+
out.set(!self[:in].get)
|
20
14
|
end
|
21
15
|
end
|
22
16
|
end
|
@@ -4,20 +4,15 @@ module Circuits
|
|
4
4
|
module Component
|
5
5
|
# Logical OR Operator
|
6
6
|
class Or < Base
|
7
|
+
def initialize(opts = {})
|
8
|
+
inputs = opts[:inputs] || 2
|
9
|
+
super(inputs: inputs, outputs: 1)
|
10
|
+
end
|
11
|
+
|
7
12
|
# Sets the output to be the result of a logical OR of the inputs
|
8
13
|
def tick
|
9
14
|
self[:out].set(inputs.map(&:get).inject(:|))
|
10
15
|
end
|
11
|
-
|
12
|
-
private
|
13
|
-
|
14
|
-
def default_input_count
|
15
|
-
2
|
16
|
-
end
|
17
|
-
|
18
|
-
def default_output_count
|
19
|
-
1
|
20
|
-
end
|
21
16
|
end
|
22
17
|
end
|
23
18
|
end
|
@@ -6,67 +6,40 @@ module Circuits
|
|
6
6
|
# SR NAND Latch
|
7
7
|
class SrNand < Base
|
8
8
|
def initialize
|
9
|
-
|
10
|
-
|
11
|
-
|
12
|
-
|
13
|
-
|
14
|
-
|
9
|
+
nand_s = Nand.new
|
10
|
+
nand_r = Nand.new
|
11
|
+
super(inputs: [:not_s, :not_r],
|
12
|
+
outputs: [:q, :not_q],
|
13
|
+
sub_components: [nand_s, nand_r],
|
14
|
+
ticks: 2)
|
15
|
+
link nand_s, nand_r
|
15
16
|
reset
|
16
17
|
end
|
17
18
|
|
18
|
-
# Computes the outputs based on the inputs and previous state
|
19
|
-
def tick
|
20
|
-
2.times.each do
|
21
|
-
sub_components.each(&:tick)
|
22
|
-
sub_components.each(&:tock)
|
23
|
-
end
|
24
|
-
end
|
25
|
-
|
26
19
|
private
|
27
20
|
|
28
|
-
|
29
|
-
|
30
|
-
|
31
|
-
|
32
|
-
|
33
|
-
@sub_components = [@nand_s, @nand_r]
|
34
|
-
end
|
35
|
-
|
36
|
-
def default_input_count
|
37
|
-
2
|
38
|
-
end
|
39
|
-
|
40
|
-
def default_output_count
|
41
|
-
2
|
42
|
-
end
|
43
|
-
|
44
|
-
def link_nand_r
|
45
|
-
nand_r[:a].set self[:not_r]
|
46
|
-
nand_r[:b].set nand_s[:out]
|
47
|
-
end
|
48
|
-
|
49
|
-
def link_nand_s
|
50
|
-
nand_s[:a].set self[:not_s]
|
51
|
-
nand_s[:b].set nand_r[:out]
|
21
|
+
def link(nand_s, nand_r)
|
22
|
+
link_nand_s nand_s, nand_r
|
23
|
+
link_nand_r nand_s, nand_r
|
24
|
+
q.set nand_s.out
|
25
|
+
not_q.set nand_r.out
|
52
26
|
end
|
53
27
|
|
54
|
-
def
|
55
|
-
|
56
|
-
|
28
|
+
def link_nand_s(nand_s, nand_r)
|
29
|
+
nand_s.a.set not_s
|
30
|
+
nand_s.b.set nand_r.out
|
57
31
|
end
|
58
32
|
|
59
|
-
def
|
60
|
-
|
61
|
-
|
62
|
-
link_outputs
|
33
|
+
def link_nand_r(nand_s, nand_r)
|
34
|
+
nand_r.a.set not_r
|
35
|
+
nand_r.b.set nand_s.out
|
63
36
|
end
|
64
37
|
|
65
38
|
def reset
|
66
|
-
|
39
|
+
not_s.set true
|
67
40
|
tick
|
68
41
|
tock
|
69
|
-
|
42
|
+
not_r.set true
|
70
43
|
end
|
71
44
|
end
|
72
45
|
end
|
@@ -6,67 +6,40 @@ module Circuits
|
|
6
6
|
# SR NOR Latch
|
7
7
|
class SrNor < Base
|
8
8
|
def initialize
|
9
|
-
|
10
|
-
|
11
|
-
|
12
|
-
|
13
|
-
|
14
|
-
|
9
|
+
nor_s = Nor.new
|
10
|
+
nor_r = Nor.new
|
11
|
+
super(inputs: [:r, :s],
|
12
|
+
outputs: [:q, :not_q],
|
13
|
+
sub_components: [nor_s, nor_r],
|
14
|
+
ticks: 2)
|
15
|
+
link nor_s, nor_r
|
15
16
|
reset
|
16
17
|
end
|
17
18
|
|
18
|
-
# Computes the outputs based on the inputs and previous state
|
19
|
-
def tick
|
20
|
-
2.times.each do
|
21
|
-
sub_components.each(&:tick)
|
22
|
-
sub_components.each(&:tock)
|
23
|
-
end
|
24
|
-
end
|
25
|
-
|
26
19
|
private
|
27
20
|
|
28
|
-
|
29
|
-
|
30
|
-
|
31
|
-
|
32
|
-
|
33
|
-
@sub_components = [@nor_r, @nor_s]
|
34
|
-
end
|
35
|
-
|
36
|
-
def default_input_count
|
37
|
-
2
|
38
|
-
end
|
39
|
-
|
40
|
-
def default_output_count
|
41
|
-
2
|
42
|
-
end
|
43
|
-
|
44
|
-
def link_nor_r
|
45
|
-
nor_r[:a].set self[:r]
|
46
|
-
nor_r[:b].set nor_s[:out]
|
47
|
-
end
|
48
|
-
|
49
|
-
def link_nor_s
|
50
|
-
nor_s[:a].set self[:s]
|
51
|
-
nor_s[:b].set nor_r[:out]
|
21
|
+
def link(nor_s, nor_r)
|
22
|
+
link_nor_s nor_s, nor_r
|
23
|
+
link_nor_r nor_s, nor_r
|
24
|
+
q.set nor_r.out
|
25
|
+
not_q.set nor_s.out
|
52
26
|
end
|
53
27
|
|
54
|
-
def
|
55
|
-
|
56
|
-
|
28
|
+
def link_nor_s(nor_s, nor_r)
|
29
|
+
nor_s.a.set s
|
30
|
+
nor_s.b.set nor_r.out
|
57
31
|
end
|
58
32
|
|
59
|
-
def
|
60
|
-
|
61
|
-
|
62
|
-
link_outputs
|
33
|
+
def link_nor_r(nor_s, nor_r)
|
34
|
+
nor_r.a.set r
|
35
|
+
nor_r.b.set nor_s.out
|
63
36
|
end
|
64
37
|
|
65
38
|
def reset
|
66
|
-
|
39
|
+
r.set true
|
67
40
|
tick
|
68
41
|
tock
|
69
|
-
|
42
|
+
r.set false
|
70
43
|
end
|
71
44
|
end
|
72
45
|
end
|
@@ -4,20 +4,15 @@ module Circuits
|
|
4
4
|
module Component
|
5
5
|
# Logical XNOR Operator
|
6
6
|
class Xnor < Base
|
7
|
+
def initialize(opts = {})
|
8
|
+
inputs = opts[:inputs] || 2
|
9
|
+
super(inputs: inputs, outputs: 1)
|
10
|
+
end
|
11
|
+
|
7
12
|
# Sets the output to be the result of a logical XNOR of the inputs
|
8
13
|
def tick
|
9
14
|
self[:out].set(!inputs.map(&:get).inject(:^))
|
10
15
|
end
|
11
|
-
|
12
|
-
private
|
13
|
-
|
14
|
-
def default_input_count
|
15
|
-
2
|
16
|
-
end
|
17
|
-
|
18
|
-
def default_output_count
|
19
|
-
1
|
20
|
-
end
|
21
16
|
end
|
22
17
|
end
|
23
18
|
end
|
@@ -4,20 +4,15 @@ module Circuits
|
|
4
4
|
module Component
|
5
5
|
# Logical XOR Operator
|
6
6
|
class Xor < Base
|
7
|
+
def initialize(opts = {})
|
8
|
+
inputs = opts[:inputs] || 2
|
9
|
+
super(inputs: inputs, outputs: 1)
|
10
|
+
end
|
11
|
+
|
7
12
|
# Sets the output to be the result of a logical XOR of the inputs
|
8
13
|
def tick
|
9
14
|
self[:out].set(inputs.map(&:get).inject(:^))
|
10
15
|
end
|
11
|
-
|
12
|
-
private
|
13
|
-
|
14
|
-
def default_input_count
|
15
|
-
2
|
16
|
-
end
|
17
|
-
|
18
|
-
def default_output_count
|
19
|
-
1
|
20
|
-
end
|
21
16
|
end
|
22
17
|
end
|
23
18
|
end
|
data/lib/circuits/version.rb
CHANGED
@@ -49,7 +49,7 @@ describe Circuits::Component::And do
|
|
49
49
|
|
50
50
|
[3, 4, 8].each do |n|
|
51
51
|
context "with #{n} inputs" do
|
52
|
-
subject { Circuits::Component::And.new
|
52
|
+
subject { Circuits::Component::And.new inputs: n }
|
53
53
|
|
54
54
|
before do
|
55
55
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -1,32 +1,10 @@
|
|
1
1
|
require 'spec_helper'
|
2
2
|
require 'circuits/component/base'
|
3
3
|
|
4
|
-
# Mock component to include Circuits::Component::Base
|
5
|
-
class MockComponent1 < Circuits::Component::Base
|
6
|
-
def default_input_count
|
7
|
-
1
|
8
|
-
end
|
9
|
-
|
10
|
-
def default_output_count
|
11
|
-
1
|
12
|
-
end
|
13
|
-
end
|
14
|
-
|
15
|
-
# Mock component to include Circuits::Component::Base
|
16
|
-
class MockComponent2 < Circuits::Component::Base
|
17
|
-
def default_input_count
|
18
|
-
2
|
19
|
-
end
|
20
|
-
|
21
|
-
def default_output_count
|
22
|
-
2
|
23
|
-
end
|
24
|
-
end
|
25
|
-
|
26
4
|
describe Circuits::Component::Base do
|
27
5
|
describe '#[]' do
|
28
6
|
context 'one input and one output' do
|
29
|
-
subject {
|
7
|
+
subject { Circuits::Component::Base.new(inputs: 1, outputs: 1) }
|
30
8
|
|
31
9
|
it 'has the input available as #in' do
|
32
10
|
expect(subject[:in]).to eq(subject.inputs[0])
|
@@ -62,7 +40,7 @@ describe Circuits::Component::Base do
|
|
62
40
|
end
|
63
41
|
|
64
42
|
context 'two inputs and two outputs' do
|
65
|
-
subject {
|
43
|
+
subject { Circuits::Component::Base.new(inputs: 2, outputs: 2) }
|
66
44
|
|
67
45
|
it 'has the inputs available as #a and #b' do
|
68
46
|
expect(subject.a).to eq(subject.inputs[0])
|
@@ -49,7 +49,7 @@ describe Circuits::Component::Nand do
|
|
49
49
|
|
50
50
|
[3, 4, 8].each do |n|
|
51
51
|
context "with #{n} inputs" do
|
52
|
-
subject { Circuits::Component::Nand.new
|
52
|
+
subject { Circuits::Component::Nand.new inputs: n }
|
53
53
|
|
54
54
|
before do
|
55
55
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -49,7 +49,7 @@ describe Circuits::Component::Nor do
|
|
49
49
|
|
50
50
|
[3, 4, 8].each do |n|
|
51
51
|
context "with #{n} inputs" do
|
52
|
-
subject { Circuits::Component::Nor.new
|
52
|
+
subject { Circuits::Component::Nor.new inputs: n }
|
53
53
|
|
54
54
|
before do
|
55
55
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -49,7 +49,7 @@ describe Circuits::Component::Or do
|
|
49
49
|
|
50
50
|
[3, 4, 8].each do |n|
|
51
51
|
context "with #{n} inputs" do
|
52
|
-
subject { Circuits::Component::Or.new
|
52
|
+
subject { Circuits::Component::Or.new inputs: n }
|
53
53
|
|
54
54
|
before do
|
55
55
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -50,7 +50,7 @@ describe Circuits::Component::Xnor do
|
|
50
50
|
context 'when the number of inputs is even' do
|
51
51
|
[2, 4, 8].each do |n|
|
52
52
|
context "with #{n} inputs" do
|
53
|
-
subject { Circuits::Component::Xnor.new
|
53
|
+
subject { Circuits::Component::Xnor.new inputs: n }
|
54
54
|
|
55
55
|
before do
|
56
56
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -99,7 +99,7 @@ describe Circuits::Component::Xnor do
|
|
99
99
|
context 'when the number of inputs is odd' do
|
100
100
|
[3, 5, 7].each do |n|
|
101
101
|
context "with #{n} inputs" do
|
102
|
-
subject { Circuits::Component::Xnor.new
|
102
|
+
subject { Circuits::Component::Xnor.new inputs: n }
|
103
103
|
|
104
104
|
before do
|
105
105
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -50,7 +50,7 @@ describe Circuits::Component::Xor do
|
|
50
50
|
context 'when the number of inputs is even' do
|
51
51
|
[2, 4, 8].each do |n|
|
52
52
|
context "with #{n} inputs" do
|
53
|
-
subject { Circuits::Component::Xor.new
|
53
|
+
subject { Circuits::Component::Xor.new inputs: n }
|
54
54
|
|
55
55
|
before do
|
56
56
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
@@ -99,7 +99,7 @@ describe Circuits::Component::Xor do
|
|
99
99
|
context 'when the number of inputs is odd' do
|
100
100
|
[3, 5, 7].each do |n|
|
101
101
|
context "with #{n} inputs" do
|
102
|
-
subject { Circuits::Component::Xor.new
|
102
|
+
subject { Circuits::Component::Xor.new inputs: n }
|
103
103
|
|
104
104
|
before do
|
105
105
|
n.times { |x| subject.inputs[x].set inputs[x] }
|
metadata
CHANGED
@@ -1,14 +1,14 @@
|
|
1
1
|
--- !ruby/object:Gem::Specification
|
2
2
|
name: circuits
|
3
3
|
version: !ruby/object:Gem::Version
|
4
|
-
version: 0.
|
4
|
+
version: 0.11.0
|
5
5
|
platform: ruby
|
6
6
|
authors:
|
7
7
|
- Henry Muru Paenga
|
8
8
|
autorequire:
|
9
9
|
bindir: bin
|
10
10
|
cert_chain: []
|
11
|
-
date: 2015-
|
11
|
+
date: 2015-11-01 00:00:00.000000000 Z
|
12
12
|
dependencies:
|
13
13
|
- !ruby/object:Gem::Dependency
|
14
14
|
name: bundler
|